static void set_hpll_hdmi_od(unsigned div)
{
check_clk_config(div);
switch (div) {
case 1:
vout_cbus_set_bits(HHI_VID_PLL_CNTL, 0, 18, 2);
break;
case 2:
vout_cbus_set_bits(HHI_VID_PLL_CNTL, 1, 18, 2);
break;
case 4:
/* #if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6 */
if (get_cpu_type() == MESON_CPU_MAJOR_ID_M6)
vout_cbus_set_bits(HHI_VID_PLL_CNTL, 3, 18, 2);
else {
/* #else */
vout_cbus_set_bits(HHI_VID_PLL_CNTL, 2, 18, 2);
}
/* #endif */
break;
case 8:
vout_cbus_set_bits(HHI_VID_PLL_CNTL, 1, 16, 2);
vout_cbus_set_bits(HHI_VID_PLL_CNTL, 3, 18, 2);
break;
default:
break;
}
}
static void set_hpll_clk_out(unsigned clk)
{
unsigned int cpu_type;
check_clk_config(clk);
vout_log_info("config HPLL\n");
if (is_meson_g9tv_cpu()) {
vout_log_info("%s[%d]\n", __FILE__, __LINE__);
vout_log_info("TODO\n");
return;
}
cpu_type = get_cpu_type();
switch (cpu_type) {
case MESON_CPU_MAJOR_ID_M6:
set_hpll_clk_out_m6(clk);
break;
case MESON_CPU_MAJOR_ID_M8:
case MESON_CPU_MAJOR_ID_M8M2:
set_hpll_clk_out_m8(clk);
break;
case MESON_CPU_MAJOR_ID_M8B:
set_hpll_clk_out_m8b(clk);
break;
case MESON_CPU_MAJOR_ID_GXBB:
set_hpll_clk_out_gxbb(clk);
break;
default:
break;
}
vout_log_info("config HPLL done\n");
}
static void set_vid_clk_div(unsigned div)
{
check_clk_config(div);
if(div == 0)
div = 1;
aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 0, 16, 3); // select vid_pll_clk
aml_set_reg32_bits(P_HHI_VID_CLK_DIV, div-1, 0, 8);
aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 7, 0, 3);
}
static void set_clk_final_div(unsigned div)
{
check_clk_config(div);
if (div == 0)
div = 1;
vout_cbus_set_bits(HHI_VID_CLK_CNTL, 1, 19, 1);
vout_cbus_set_bits(HHI_VID_CLK_CNTL, 0, 16, 3);
vout_cbus_set_bits(HHI_VID_CLK_DIV, div - 1, 0, 8);
vout_cbus_set_bits(HHI_VID_CLK_CNTL, 7, 0, 3);
}
static void set_hpll_clk_out(unsigned clk)
{
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL5, 1, 30, 1);
check_clk_config(clk);
printk("config HPLL\n");
switch(clk){
case 2970:
aml_write_reg32(P_HHI_HDMI_PLL_CNTL, 0x5000023d);
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 1, 14, 1); // div mode
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 0xe00, 0, 12); // div_frac
aml_write_reg32(P_HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
aml_write_reg32(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
aml_write_reg32(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
aml_write_reg32(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL, 0x5, 28, 3); //reset hpll
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL, 0x4, 28, 3);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
break;
case 4320:
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 0, 14, 1); // div mode
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 0x000, 0, 12); // div_frac
aml_write_reg32(P_HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
aml_write_reg32(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
aml_write_reg32(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
aml_write_reg32(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
aml_write_reg32(P_HHI_HDMI_PLL_CNTL, 0x0000022d);
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL, 0x5, 28, 3); //reset hpll
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL, 0x4, 28, 3);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
break;
case 2448:
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 1, 14, 1); // div mode
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 0xe00, 0, 12); // div_frac
aml_write_reg32(P_HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
aml_write_reg32(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
aml_write_reg32(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
aml_write_reg32(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
aml_write_reg32(P_HHI_HDMI_PLL_CNTL, 0x00000266);
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL, 0x5, 28, 3); //reset hpll
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL, 0x4, 28, 3);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
break;
default:
printk("error hpll clk: %d\n", clk);
break;
}
printk("config HPLL done\n");
}
/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
static void set_hpll_lvds_od(unsigned div)
{
check_clk_config(div);
switch (div) {
case 1:
vout_cbus_set_bits(HHI_VID_PLL_CNTL, 0, 16, 2);
break;
case 2:
vout_cbus_set_bits(HHI_VID_PLL_CNTL, 1, 16, 2);
break;
case 4:
vout_cbus_set_bits(HHI_VID_PLL_CNTL, 2, 16, 2);
break;
case 8: /* note: need test */
vout_cbus_set_bits(HHI_VID_PLL_CNTL, 3, 16, 2);
break;
default:
break;
}
}
static void set_vdac1_div(unsigned div)
{
check_clk_config(div);
div = check_div(div);
vout_cbus_set_bits(HHI_VIID_CLK_DIV, div, 24, 4);
}
static void set_hdmi_tx_pixel_div(unsigned div)
{
check_clk_config(div);
div = check_div(div);
vout_cbus_set_bits(HHI_HDMI_CLK_CNTL, div, 16, 4);
}
static void set_vid_pll_div(unsigned div)
{
check_clk_config(div);
/* #if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6 */
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) {
/* Gate disable */
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 0, 16, 1);
switch (div) {
case 10:
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 4, 4, 3);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 1, 8, 2);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 1, 12, 3);
break;
case 5:
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 4, 4, 3);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 0, 8, 2);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 0, 12, 3);
break;
default:
break;
}
/* Soft Reset div_post/div_pre */
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 0, 0, 2);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 1, 3, 1);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 1, 7, 1);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 3, 0, 2);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 0, 3, 1);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 0, 7, 1);
/* Gate enable */
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 1, 16, 1);
}
/* #endif */
/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
if (is_meson_m8_cpu() || is_meson_m8m2_cpu()) {
/* Gate disable */
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 0, 16, 1);
switch (div) {
case 10:
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 4, 4, 3);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 1, 8, 2);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 1, 12, 3);
break;
case 5:
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 4, 4, 3);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 0, 8, 2);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 0, 12, 3);
break;
case 6:
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 5, 4, 3);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 0, 8, 2);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 0, 12, 3);
break;
default:
break;
}
/* Soft Reset div_post/div_pre */
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 0, 0, 2);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 1, 3, 1);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 1, 7, 1);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 3, 0, 2);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 0, 3, 1);
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 0, 7, 1);
/* Gate enable */
vout_cbus_set_bits(HHI_VID_DIVIDER_CNTL, 1, 16, 1);
}
/* #endif */
}
static void set_hpll_clk_out(unsigned clk)
{
check_clk_config(clk);
printk("config HPLL = %d\n", clk);
switch(clk){
case 2970:
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL, 0x5000023d);
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 1, 14, 1); // div mode
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 0xe00, 0, 12); // div_frac
aml_read_reg32_d(P_HHI_HDMI_PLL_CNTL2);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL3, 0x135c5091);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL5, 0x71486900); //5940 0x71c86900 // 0x71486900 2970
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL, 0x4000023d);
printk("waiting HPLL lock\n");
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
break;
case 4320:
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 0, 14, 1); // div mode
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 0x000, 0, 12); // div_frac
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL3, 0x135c5091);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL5, 0x71c86900); //5940 0x71c86900 // 0x71486900 2970
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL, 0x0000022d);
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL, 0x5, 28, 3); //reset hpll
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL, 0x4, 28, 3);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
break;
case 2448:
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 1, 14, 1); // div mode
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 0xe00, 0, 12); // div_frac
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL3, 0x135c5091);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL5, 0x71486900); //5940 0x71c86900 // 0x71486900 2970
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL, 0x00000266);
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL, 0x5, 28, 3); //reset hpll
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL, 0x4, 28, 3);
printk("waiting HPLL lock\n");
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
break;
case 1080:
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL, 0x5000022d);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL2, 0x00890000);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL3, 0x135c5091);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
// P_HHI_HDMI_PLL_CNTL5
// 0x71c86900 for div2 disable inside PLL2 of HPLL
// 0x71486900 for div2s enable inside PLL2 of HPLL
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL5, 0x71c86900);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL, 0x4000022d);
printk("waiting HPLL lock\n");
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
break;
default:
printk("error hpll clk: %d\n", clk);
break;
}
printk("config HPLL done\n");
}
