static void configure_per_dpll(const dpll_param *dpll_param_p)
{
/* Unlock the PER dpll */
set_modify(CM_CLKMODE_DPLL_PER, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_PER);
/* Disable autoidle */
set_modify(CM_AUTOIDLE_DPLL_PER, 0x00000007, 0x0);
set_modify(CM_CLKSEL_DPLL_PER, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_PER, 0x0000003f, dpll_param_p->n);
set_modify(CM_DIV_M2_DPLL_PER, 0x0000001f, dpll_param_p->m2);
set_modify(CM_DIV_M2_DPLL_PER, 0x00000100, 0x1 << 8);
set_modify(CM_DIV_M3_DPLL_PER, 0x0000001f, dpll_param_p->m3);
set_modify(CM_DIV_M3_DPLL_PER, 0x00000100, 0x1 << 8);
set_modify(CM_DIV_M4_DPLL_PER, 0x0000001f, dpll_param_p->m4);
set_modify(CM_DIV_M4_DPLL_PER, 0x00000100, 0x1 << 8);
set_modify(CM_DIV_M5_DPLL_PER, 0x0000001f, dpll_param_p->m5);
set_modify(CM_DIV_M5_DPLL_PER, 0x00000100, 0x1 << 8);
set_modify(CM_DIV_M6_DPLL_PER, 0x0000001f, dpll_param_p->m6);
set_modify(CM_DIV_M6_DPLL_PER, 0x00000100, 0x1 << 8);
set_modify(CM_DIV_M7_DPLL_PER, 0x0000001f, dpll_param_p->m7);
set_modify(CM_DIV_M7_DPLL_PER, 0x00000100, 0x1 << 8);
/* Lock the per dpll */
set_modify(CM_CLKMODE_DPLL_PER, 0x00000007, PLL_LOCK);
check_loop(BIT0, 1, CM_IDLEST_DPLL_PER);
}
static void configure_iva_dpll(dpll_param *dpll_param_p)
{
/* Unlock the IVA dpll */
set_modify(CM_CLKMODE_DPLL_IVA, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_IVA);
/* CM_BYPCLK_DPLL_IVA = CORE_X2_CLK/2 */
set_modify(CM_BYPCLK_DPLL_IVA, 0x00000003, 0x1);
/* Disable DPLL autoidle */
set_modify(CM_AUTOIDLE_DPLL_IVA, 0x00000007, 0x0);
/* Set M,N,M4,M5 */
set_modify(CM_CLKSEL_DPLL_IVA, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_IVA, 0x0000007f, dpll_param_p->n);
set_modify(CM_DIV_M4_DPLL_IVA, 0x0000001f, dpll_param_p->m4);
set_modify(CM_DIV_M4_DPLL_IVA, 0x00000100, 0x1 << 8);
set_modify(CM_DIV_M5_DPLL_IVA, 0x0000001f, dpll_param_p->m5);
set_modify(CM_DIV_M5_DPLL_IVA, 0x00000100, 0x1 << 8);
/* Lock the iva dpll */
set_modify(CM_CLKMODE_DPLL_IVA, 0x00000007, PLL_LOCK);
check_loop(BIT0, 1, CM_IDLEST_DPLL_IVA);
}
static void configure_usb_dpll(dpll_param *dpll_param_p)
{
/* Select the 60Mhz clock 480/8 = 60*/
set_modify(CM_CLKSEL_USB_60MHz, 0x00000000, 0x1);
/* Unlock the USB dpll */
set_modify(CM_CLKMODE_DPLL_USB, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_USB);
/* Disable autoidle */
set_modify(CM_AUTOIDLE_DPLL_USB, 0x00000007, 0x0);
set_modify(CM_CLKSEL_DPLL_USB, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_USB, 0x0000003f, dpll_param_p->n);
/* Force DPLL CLKOUT to stay active */
set_modify(CM_DIV_M2_DPLL_USB, 0x00000000, 0x100);
set_modify(CM_DIV_M2_DPLL_USB, 0x0000001f, dpll_param_p->m2);
set_modify(CM_DIV_M2_DPLL_USB, 0x00000100, 0x1 << 8);
set_modify(CM_CLKDCOLDO_DPLL_USB, 0x00000100, 0x1 << 8);
/* Lock the usb dpll */
set_modify(CM_CLKMODE_DPLL_USB, 0x00000007, PLL_LOCK);
check_loop(BIT0, 1, CM_IDLEST_DPLL_USB);
/* force enable the CLKDCOLDO clock */
set_modify(CM_CLKDCOLDO_DPLL_USB, 0x00000000, 0x100);
}
static void configure_abe_dpll(dpll_param *dpll_param_p)
{
/* Select sys_clk as ref clk for ABE dpll */
writel(0, CM_ABE_PLL_REF_CLKSEL);
/* Unlock the ABE dpll */
set_modify(CM_CLKMODE_DPLL_ABE, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_ABE);
/* Disable autoidle */
set_modify(CM_AUTOIDLE_DPLL_ABE, 0x00000007, 0x0);
set_modify(CM_CLKSEL_DPLL_ABE, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_ABE, 0x0000002f, dpll_param_p->n);
/* Force DPLL CLKOUTHIF to stay enabled */
set_modify(CM_DIV_M2_DPLL_ABE, 0x00000000, 0x500);
set_modify(CM_DIV_M2_DPLL_ABE, 0x0000001f, dpll_param_p->m2);
set_modify(CM_DIV_M2_DPLL_ABE, 0x00000100, 0x1 << 8);
/* Force DPLL CLKOUTHIF to stay enabled */
set_modify(CM_DIV_M3_DPLL_ABE, 0x00000000, 0x100);
set_modify(CM_DIV_M3_DPLL_ABE, 0x0000001f, dpll_param_p->m3);
set_modify(CM_DIV_M3_DPLL_ABE, 0x00000100, 0x1 << 8);
/* Lock the abe dpll */
set_modify(CM_CLKMODE_DPLL_ABE, 0x00000007, PLL_LOCK);
check_loop(BIT0, 1, CM_IDLEST_DPLL_ABE);
}
static void configure_mpu_dpll(dpll_param *dpll_param_p,
struct proc_specific_functions *proc_ops)
{
int omap_rev;
u32 emif_div_4, abe_div_8, dcc_en;
/* Unlock the MPU dpll */
set_modify(CM_CLKMODE_DPLL_MPU, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_MPU);
omap_rev = proc_ops->proc_get_proc_id();
if (omap_rev >= OMAP_4470_ES1_DOT_0) {
/*
* Same M, N as for 800 MHz from M2 output will
* give 1600 MHz from M3 output
*/
dpll_param_p = &mpu_dpll_param_800mhz;
} else if (omap_rev >= OMAP_4460_ES1_DOT_0) {
/*
* Same M, N as for 700 MHz from M2 output will
* give 1400 MHz from M3 output
*/
dpll_param_p = &mpu_dpll_param_700mhz;
emif_div_4 = 1;
abe_div_8 = 1;
set_modify(CM_MPU_MPU_CLKCTRL, 0x01000000, emif_div_4 << 24);
set_modify(CM_MPU_MPU_CLKCTRL, 0x02000000, abe_div_8 << 25);
dcc_en = 0;
/* Enable / disable DCC on 4460 */
set_modify(CM_CLKSEL_DPLL_MPU, 0x00400000, dcc_en << 22);
}
/* Disable DPLL autoidle */
set_modify(CM_AUTOIDLE_DPLL_MPU, 0x00000007, 0x0);
/* Set M,N,M2 values */
set_modify(CM_CLKSEL_DPLL_MPU, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_MPU, 0x0000003f, dpll_param_p->n);
set_modify(CM_DIV_M2_DPLL_MPU, 0x0000001f, dpll_param_p->m2);
set_modify(CM_DIV_M2_DPLL_MPU, 0x00000100, 0x1 << 8);
/* Lock the mpu dpll */
set_modify(CM_CLKMODE_DPLL_MPU, 0x00000007, (PLL_LOCK | 10));
check_loop(BIT0, 1, CM_IDLEST_DPLL_MPU);
}
void configure_core_dpll_no_lock(struct proc_specific_functions *proc_ops)
{
int omap_rev;
dpll_param *dpll_param_p;
omap_rev = proc_ops->proc_get_proc_id();
if (omap_rev >= OMAP_4470_ES1_DOT_0)
dpll_param_p = &core_dpll_param_ddr466mhz;
else
dpll_param_p = &core_dpll_param_ddr400mhz;
/* Get the sysclk speed from cm_sys_clksel
* Set it to 38.4 MHz, in case ROM code is bypassed
*/
writel(0x7,CM_SYS_CLKSEL);
/* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */
set_modify(CM_CLKSEL_CORE, 0x00000000, 0x110);
/* Unlock the CORE dpll */
set_modify(CM_CLKMODE_DPLL_CORE, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_CORE);
/* Disable autoidle */
set_modify(CM_AUTOIDLE_DPLL_CORE, 0x00000007, 0x0);
set_modify(CM_CLKSEL_DPLL_CORE, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_CORE, 0x0000003f, dpll_param_p->n);
set_modify(CM_DIV_M2_DPLL_CORE, 0x0000001f, dpll_param_p->m2);
set_modify(CM_DIV_M3_DPLL_CORE, 0x0000001f, dpll_param_p->m3);
set_modify(CM_DIV_M4_DPLL_CORE, 0x0000001f, dpll_param_p->m4);
set_modify(CM_DIV_M5_DPLL_CORE, 0x0000001f, dpll_param_p->m5);
set_modify(CM_DIV_M6_DPLL_CORE, 0x0000001f, dpll_param_p->m6);
set_modify(CM_DIV_M7_DPLL_CORE, 0x0000001f, dpll_param_p->m7);
}
/* ARGSUSED */
void
chargen_dg(int s, struct servtab *sep)
{
struct sockaddr_storage ss;
static char *rs;
int len;
socklen_t size;
char text[LINESIZ+2];
if (endring == 0) {
initring();
rs = ring;
}
size = sizeof(ss);
if (recvfrom(s, text, sizeof(text), 0,
(struct sockaddr *)&ss, &size) < 0)
return;
if (check_loop((struct sockaddr *)&ss, sep))
return;
if ((len = endring - rs) >= LINESIZ)
memmove(text, rs, LINESIZ);
else {
memmove(text, rs, len);
memmove(text + len, ring, LINESIZ - len);
}
if (++rs == endring)
rs = ring;
text[LINESIZ] = '\r';
text[LINESIZ + 1] = '\n';
(void) sendto(s, text, sizeof(text), 0, (struct sockaddr *)&ss, size);
}
void configure_core_dpll_no_lock(void)
{
dpll_param *dpll_param_p = &core_dpll_param_ddr400mhz;
/* Get the sysclk speed from cm_sys_clksel
* Set it to 38.4 MHz, in case ROM code is bypassed
*/
writel(0x7,CM_SYS_CLKSEL);
/* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */
set_modify(CM_CLKSEL_CORE, 0x00000000, 0x110);
/* Unlock the CORE dpll */
set_modify(CM_CLKMODE_DPLL_CORE, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_CORE);
/* Disable autoidle */
set_modify(CM_AUTOIDLE_DPLL_CORE, 0x00000007, 0x0);
set_modify(CM_CLKSEL_DPLL_CORE, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_CORE, 0x0000003f, dpll_param_p->n);
set_modify(CM_DIV_M2_DPLL_CORE, 0x0000001f, dpll_param_p->m2);
set_modify(CM_DIV_M3_DPLL_CORE, 0x0000001f, dpll_param_p->m3);
set_modify(CM_DIV_M4_DPLL_CORE, 0x0000001f, dpll_param_p->m4);
set_modify(CM_DIV_M5_DPLL_CORE, 0x0000001f, dpll_param_p->m5);
set_modify(CM_DIV_M6_DPLL_CORE, 0x0000001f, dpll_param_p->m6);
set_modify(CM_DIV_M7_DPLL_CORE, 0x0000001f, dpll_param_p->m7);
}
static void testchord_thread(node *n, endpoint *endpt, void *arg)
{
testchord_arg *tca = (testchord_arg*)arg;
chordnode nodes[MAX_NODES];
int i;
struct timeval start;
int ncount = 0;
debug_control dbc;
endpointid null_epid;
printf("managers:\n");
for (i = 0; i < tca->nmanagers; i++)
printf(EPID_FORMAT"\n",EPID_ARGS(tca->managerids[i]));
memset(&nodes,0,MAX_NODES*sizeof(chordnode));
memset(&null_epid,0,sizeof(endpointid));
nodes[0] = start_one_chord(n,endpt,null_epid,tca->managerids[rand()%tca->nmanagers]);
ncount = 1;
printf("initial node = #%d ("EPID_FORMAT")\n",nodes[0].id,EPID_ARGS(nodes[0].epid));
for (i = 1; i < NODE_COUNT; i++)
add_node(n,endpt,tca->managerids[rand()%tca->nmanagers],nodes[0].epid);
gettimeofday(&start,NULL);
dbc.n = n;
dbc.epid = endpt->epid;
node_add_thread(n,"debug_control",debug_control_thread,&dbc,NULL);
check_loop(n,endpt,nodes,ncount,start,NODE_COUNT,tca->managerids,tca->nmanagers);
}
void next_frame(void *data)
/* Jump to next frame of temp file, wrapping back to 1st frame if go past
end... */
{
int oix;
int undoix;
(void)data;
if (flix.xf == NULL)
return;
flx_clear_olays();
oix = vs.frame_ix;
undoix = scrub_cur_frame()-1;
++vs.frame_ix;
check_loop();
if(undoix != vs.frame_ix)
{
if (unfli(vb.pencel,vs.frame_ix,1) < 0)
vs.frame_ix = oix;
zoom_it();
save_undo();
}
else
{
zoom_unundo(); /* undo has next frame left in it by sub_cur_frame() */
}
flx_draw_olays();
}
int main(int * argc, char ** argv){
initialize_unit();
while(1){
calc_error(input_data, output_data);
back_propagation();
if(check_loop())break;
}
release_unit();
}
static void configure_mpu_dpll(dpll_param *dpll_param_p)
{
/* Unlock the MPU dpll */
set_modify(CM_CLKMODE_DPLL_MPU, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_MPU);
/* Disable DPLL autoidle */
set_modify(CM_AUTOIDLE_DPLL_MPU, 0x00000007, 0x0);
/* Set M,N,M2 values */
set_modify(CM_CLKSEL_DPLL_MPU, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_MPU, 0x0000003f, dpll_param_p->n);
set_modify(CM_DIV_M2_DPLL_MPU, 0x0000001f, dpll_param_p->m2);
set_modify(CM_DIV_M2_DPLL_MPU, 0x00000100, 0x1 << 8);
/* Lock the mpu dpll */
set_modify(CM_CLKMODE_DPLL_MPU, 0x00000007, (PLL_LOCK | 10));
check_loop(BIT0, 1, CM_IDLEST_DPLL_MPU);
}
/*
* add to the dependecy and selection lists
*/
static void add_depend(struct makenode *node, const char *dst)
{
struct makenode *dep;
dep = add_target(dst);
loop = 0;
if (check_loop(dep, node))
return;
dep->select = new_list(node, dep->select);
dep->num_sels++;
node->depend = new_list(dep, node->depend);
node->num_deps++;
}
void lock_core_dpll_shadow(struct proc_specific_functions *proc_ops)
{
int omap_rev;
dpll_param *dpll_param_p;
u32 temp;
temp = readl(CM_MEMIF_CLKSTCTRL);
temp &= (~3);
temp |= 2;
writel(temp, CM_MEMIF_CLKSTCTRL);
while(readl(CM_MEMIF_EMIF_1_CLKCTRL) & 0x30000)
;
while(readl(CM_MEMIF_EMIF_2_CLKCTRL) & 0x30000)
;
omap_rev = proc_ops->proc_get_proc_id();
if (omap_rev >= OMAP_4470_ES1_DOT_0)
dpll_param_p = &core_dpll_param_ddr466mhz;
else
dpll_param_p = &core_dpll_param_ddr400mhz;
/* Lock the core dpll using freq update method */
/*(CM_CLKMODE_DPLL_CORE) */
writel(0x0A, 0x4A004120);
/* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,
* DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1
*/
writel(0x70D | (dpll_param_p->m2 << 11), 0x4A004260);
/* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */
while((readl(0x4A004260) & 0x1) == 0x1)
;
/* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */
check_loop(BIT0, 1, CM_IDLEST_DPLL_CORE);
//lock_core_dpll();
while(readl(CM_MEMIF_EMIF_1_CLKCTRL) & 0x30000)
;
while(readl(CM_MEMIF_EMIF_2_CLKCTRL) & 0x30000)
;
writel(temp|3, CM_MEMIF_CLKSTCTRL);
}
static int check_loop(struct makenode *dep, struct makenode *src)
{
struct makelist *s;
for (s = dep->depend; s; s = s->next) {
if (s->node == src) {
fprintf(stderr, "loop exists %s in %s!\n", dep->name, src->name);
return 1;
}
if (loop++ > 99999) {
fprintf(stderr, "too many loops! (loop=%d, dep->name=%s, src->name=%s)\n",
loop, dep->name, src->name);
return 1;
}
if (check_loop(s->node, src))
return 1;
}
return 0;
}
int add_to_pile(char *go_back, t_link **last)
{
t_link *link;
int total;
total = 0;
link = (*last)->cas->link;
while (link)
{
if (!link->cas->path && !check_loop(link->cas))
{
if (add_this_link(last, link))
return (1);
++total;
}
link = link->next;
}
*go_back = (total) ? 0 : 1;
return (0);
}
/* ARGSUSED */
void
daytime_dg(int s, struct servtab *sep) /* Return human-readable time of day */
{
char buffer[256];
time_t now;
struct sockaddr_storage ss;
socklen_t size;
now = time(NULL);
size = sizeof(ss);
if (recvfrom(s, buffer, sizeof(buffer), 0,
(struct sockaddr *)&ss, &size) < 0)
return;
if (check_loop((struct sockaddr *)&ss, sep))
return;
sprintf(buffer, "%.24s\r\n", ctime(&now));
sendto(s, buffer, strlen(buffer), 0, (struct sockaddr *)&ss, size);
}
int main(void)
{
node * head;
head = NULL;
printf("1.insert_beg\n2.print\n3.create_loop_k\n4.check_loop\n5.end\n");
int num;
int k;
int test;
int end;
end = 1;
while(end) {
scanf("%d", &test);
switch(test) {
case 1:
scanf("%d", &num);
head = insert_beg(head, num);
break;
case 2:
print(head);
break;
case 3:
scanf("%d", &k);
create_loop(head, k);
break;
case 4:
num = check_loop(head);
if (num == 1) {
printf("LOOP FOUND\n");
} else {
printf("LOOP NOT FOUND\n");
}
case 5:
end = 0;
}
}
return 0;
}
void lock_core_dpll_shadow(void)
{
dpll_param *dpll_param_p = &core_dpll_param_ddr400mhz;
u32 temp;
temp = readl(CM_MEMIF_CLKSTCTRL);
temp &= (~3);
temp |= 2;
writel(temp, CM_MEMIF_CLKSTCTRL);
while(readl(CM_MEMIF_EMIF_1_CLKCTRL) & 0x30000)
;
while(readl(CM_MEMIF_EMIF_2_CLKCTRL) & 0x30000)
;
/* Lock the core dpll using freq update method */
/*(CM_CLKMODE_DPLL_CORE) */
writel(0x0A, 0x4A004120);
/* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,
* DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1
*/
writel(0x70D | (dpll_param_p->m2 << 11), 0x4A004260);
/* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */
while((readl(0x4A004260) & 0x1) == 0x1)
;
/* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */
check_loop(BIT0, 1, CM_IDLEST_DPLL_CORE);
//lock_core_dpll();
while(readl(CM_MEMIF_EMIF_1_CLKCTRL) & 0x30000)
;
while(readl(CM_MEMIF_EMIF_2_CLKCTRL) & 0x30000)
;
writel(temp|3, CM_MEMIF_CLKSTCTRL);
}
/**
* scale_vcore_omap4460() - Scale for OMAP4460
* @rev: OMAP chip revision
*
* PMIC assumed to be used is TWL6030 + TPS62361
*/
static void scale_vcore_omap4460(unsigned int rev)
{
u32 volt;
/* vdd_core - TWL6030 VCORE 1 - OPP100 - 1.127V */
omap_vc_bypass_send_value(TWL6030_SRI2C_SLAVE_ADDR,
TWL6030_SRI2C_REG_ADDR_VCORE1, 0x22);
/* WKUP clocks */
set_modify(CM_WKUP_GPIO1_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_WKUP_GPIO1_CLKCTRL);
/* vdd_mpu - TPS62361 - OPP100 - 1.210V (roundup from 1.2V) */
volt = 1210;
volt -= TPS62361_BASE_VOLT_MV;
volt /= 10;
do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
/* vdd_iva - TWL6030 VCORE 2 - OPP50 - 0.950V */
omap_vc_bypass_send_value(TWL6030_SRI2C_SLAVE_ADDR,
TWL6030_SRI2C_REG_ADDR_VCORE2, 0x14);
}
/* ARGSUSED */
void
daytime_dg(int s, struct servtab *sep)
{
char buffer[256];
time_t now;
struct sockaddr_storage ss;
socklen_t size;
now = time((time_t *) 0);
size = sizeof(ss);
if (recvfrom(s, buffer, sizeof(buffer), 0,
(struct sockaddr *)&ss, &size) < 0)
return;
if (check_loop((struct sockaddr *)&ss, sep))
return;
(void) sprintf(buffer, "%.24s\r\n", ctime(&now));
(void) sendto(s, buffer, strlen(buffer), 0,
(struct sockaddr *)&ss, size);
}
static Errcode vp_playit(LONG frames)
/* Ya, go play dem frames. Replay temp file */
{
Errcode err;
ULONG clock;
flx_clear_olays(); /* undraw cels cursors etc */
if (flix.xf != NULL) {
clock = pj_clock_1000();
hide_mouse();
for (;;)
{
if (frames == 0)
{
err = Success;
break;
}
--frames;
clock += flix.hdr.speed;
if ((err = wait_til(clock)) != Err_timeout)
break;
if (clock > pj_clock_1000()) /* wrap */
clock = pj_clock_1000();
vs.frame_ix++;
if (vs.frame_ix > flix.hdr.frame_count)
vs.frame_ix = 1;
if((err = unfli(vb.pencel,vs.frame_ix,1)) < 0)
break;
zoom_it();
}
show_mouse();
}
check_loop(); /* to go frame frame_count to 0 sometimes... */
flx_draw_olays(); /* undraw cels cursors etc */
return(err);
}
static int load_fli_overlay(char *title, int how)
/* returns ecode if can't do. This reports errors.*/
{
Errcode err;
Rcel *loadcel = NULL;
Cmap *cmap = NULL;
int usr_fit = 0; /* start off not knowing how to fit colors */
Flifile flif;
int i = 0;
int fit_option;
int fcount;
Vabortdat vd;
Boolean overlay_fit;
clear_struct(&flif);
vd.totframes = &flif.hdr.frame_count;
vd.frame = &i;
set_abort_verify(olay_abort_verify,&vd);
if((err = save_pic(screen_name, vb.pencel,0,TRUE)) < 0)
goto error;
if((err = pj_fli_open(title,&flif,JREADONLY)) < 0)
goto error;
/* allocate fli size cel to hold fli frame(s) */
if((err = valloc_ramcel(&loadcel,flif.hdr.width,flif.hdr.height)) < 0)
goto error;
if((err = pj_cmap_alloc(&cmap,COLORS)) < Success)
goto error;
if((err = pj_fli_seek_first(&flif)) < 0)
goto error;
for (i=0; i<flif.hdr.frame_count; i++)
{
if (i != 0 && vs.frame_ix == 0)
{
if (soft_qchoice(NULL, "comp_past") != 0)
goto aborted;
}
if ((err = pj_fli_read_next(title,&flif,loadcel,0)) < 0)
goto error;
if (!cmaps_same(loadcel->cmap, vb.pencel->cmap))
{
if (!usr_fit)
{
if((usr_fit = 1 + soft_qchoice(NULL, "comp_cmap")) <= 0)
goto aborted;
}
fit_option = usr_fit;
}
else
fit_option = 0;
/* switch to get the color map into cmap */
switch (fit_option)
{
case 0: /* both are same. yea! */
case 2: /* keep current */
case 4: /* No Fit */
pj_cmap_copy(vb.pencel->cmap,cmap);
break;
case 3: /*use overlay cmap */
pj_cmap_copy(loadcel->cmap, cmap);
goto do_screen_cfit;
case 1: /* compromise cmap */
compromise_cmap(vb.pencel->cmap, loadcel->cmap, cmap);
do_screen_cfit:
cfit_rcel(vb.pencel,cmap);
pj_cmap_copy(cmap,vb.pencel->cmap);
see_cmap();
break;
}
if (i == 0) /* let user position first frame */
{
save_undo();
switch (fit_option) /* figure out whether to fit cel to display
* for user to position. */
{
case 0: /* both are same. yea! */
case 3: /*use overlay cmap */
case 4: /* No Fit */
overlay_fit = FALSE;
break;
case 1: /* compromise cmap */
case 2: /* keep current */
overlay_fit = TRUE;
break;
}
move_rcel(loadcel,overlay_fit,FALSE);
if(!soft_yes_no_box("olay_start"))
{
load_pic(screen_name, vb.pencel, 0, TRUE);
goto aborted;
}
/* we're committed now */
pj_delete(screen_name);
dirties();
}
switch (how)
{
case 0: /* over/under */
if(i != 0)
save_undo();
if((err = may_cfit_blit_cel(loadcel, fit_option)) < 0)
goto error;
break;
case 2: /* crossfade */
if ((fcount = flif.hdr.frame_count-1) == 0)
fcount = 1;
pj_rcel_copy(vb.pencel, undof);
if((err = transpblit(loadcel, 0, FALSE,
(i*(long)100+flif.hdr.frame_count/2)/fcount)) < Success)
{
goto error;
}
break;
}
if((err = sub_cur_frame()) < Success)
goto error;
if(poll_abort() < Success)
goto aborted;
vs.frame_ix++;
check_loop();
if((err = unfli(vb.pencel,vs.frame_ix,1)) < 0)
goto error;
}
err = 0;
goto OUT;
aborted:
err = Err_abort;
error:
err = softerr(err,"!%s", "comp_load", title);
OUT:
pj_cmap_free(cmap);
pj_rcel_free(loadcel);
pj_fli_close(&flif);
set_abort_verify(NULL);
return(err);
}
Status FileLoader::do_loop() {
TRY_RESULT(check_info,
check_loop(parts_manager_.get_checked_prefix_size(), parts_manager_.get_unchecked_ready_prefix_size(),
parts_manager_.unchecked_ready()));
if (check_info.changed) {
on_progress_impl(narrow_cast<size_t>(parts_manager_.get_ready_size()));
}
for (auto &query : check_info.queries) {
G()->net_query_dispatcher().dispatch_with_callback(
std::move(query), actor_shared(this, UniqueId::next(UniqueId::Type::Default, CommonQueryKey)));
}
if (check_info.need_check) {
parts_manager_.set_need_check();
parts_manager_.set_checked_prefix_size(check_info.checked_prefix_size);
}
if (parts_manager_.ready()) {
TRY_STATUS(parts_manager_.finish());
TRY_STATUS(on_ok(parts_manager_.get_size()));
LOG(INFO) << "Bad download order rate: "
<< (debug_total_parts_ == 0 ? 0.0 : 100.0 * debug_bad_part_order_ / debug_total_parts_) << "% "
<< debug_bad_part_order_ << "/" << debug_total_parts_ << " " << format::as_array(debug_bad_parts_);
stop_flag_ = true;
return Status::OK();
}
TRY_STATUS(before_start_parts());
SCOPE_EXIT {
after_start_parts();
};
while (true) {
if (blocking_id_ != 0) {
break;
}
if (resource_state_.unused() < static_cast<int64>(parts_manager_.get_part_size())) {
VLOG(files) << "Got only " << resource_state_.unused() << " resource";
break;
}
TRY_RESULT(part, parts_manager_.start_part());
if (part.size == 0) {
break;
}
VLOG(files) << "Start part " << tag("id", part.id) << tag("size", part.size);
resource_state_.start_use(static_cast<int64>(part.size));
TRY_RESULT(query_flag, start_part(part, parts_manager_.get_part_count()));
NetQueryPtr query;
bool is_blocking;
std::tie(query, is_blocking) = std::move(query_flag);
uint64 id = UniqueId::next();
if (is_blocking) {
CHECK(blocking_id_ == 0);
blocking_id_ = id;
}
part_map_[id] = std::make_pair(part, query->cancel_slot_.get_signal_new());
// part_map_[id] = std::make_pair(part, query.get_weak());
auto callback = actor_shared(this, id);
if (delay_dispatcher_.empty()) {
G()->net_query_dispatcher().dispatch_with_callback(std::move(query), std::move(callback));
} else {
send_closure(delay_dispatcher_, &DelayDispatcher::send_with_callback_and_delay, std::move(query),
std::move(callback), next_delay_);
next_delay_ = std::max(next_delay_ * 0.8, 0.003);
}
}
return Status::OK();
}
static void enable_all_clocks(void)
{
/* L4PER clocks */
set_modify(CM_L4PER_CLKSTCTRL, 0x00000000, 0x2);
set_modify(CM_L4PER_DMTIMER10_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_DMTIMER10_CLKCTRL);
set_modify(CM_L4PER_DMTIMER11_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_DMTIMER11_CLKCTRL);
set_modify(CM_L4PER_DMTIMER2_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_DMTIMER2_CLKCTRL);
set_modify(CM_L4PER_DMTIMER3_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_DMTIMER3_CLKCTRL);
set_modify(CM_L4PER_DMTIMER4_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_DMTIMER4_CLKCTRL);
set_modify(CM_L4PER_DMTIMER9_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_DMTIMER9_CLKCTRL);
/* GPIO clocks */
set_modify(CM_L4PER_GPIO2_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L4PER_GPIO2_CLKCTRL);
set_modify(CM_L4PER_GPIO3_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L4PER_GPIO3_CLKCTRL);
set_modify(CM_L4PER_GPIO4_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L4PER_GPIO4_CLKCTRL);
set_modify(CM_L4PER_GPIO4_CLKCTRL, 0x00000100, 0x1 << 8);
set_modify(CM_L4PER_GPIO5_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L4PER_GPIO5_CLKCTRL);
set_modify(CM_L4PER_GPIO6_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L4PER_GPIO6_CLKCTRL);
set_modify(CM_L4PER_HDQ1W_CLKCTRL, 0x00000000, 0x2);
/* I2C clocks */
set_modify(CM_L4PER_I2C1_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_I2C1_CLKCTRL);
set_modify(CM_L4PER_I2C2_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_I2C2_CLKCTRL);
set_modify(CM_L4PER_I2C3_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_I2C3_CLKCTRL);
set_modify(CM_L4PER_I2C4_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_I2C4_CLKCTRL);
set_modify(CM_L4PER_MCBSP4_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_MCBSP4_CLKCTRL);
/* MCSPI clocks */
set_modify(CM_L4PER_MCSPI1_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_MCSPI1_CLKCTRL);
set_modify(CM_L4PER_MCSPI2_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_MCSPI2_CLKCTRL);
set_modify(CM_L4PER_MCSPI3_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_MCSPI3_CLKCTRL);
set_modify(CM_L4PER_MCSPI4_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_MCSPI4_CLKCTRL);
/* MMC clocks */
set_modify(CM_L3INIT_HSMMC1_CLKCTRL, 0x00000003, 0x2);
set_modify(CM_L3INIT_HSMMC1_CLKCTRL, 0x01000000, 0x1 << 24);
set_modify(CM_L3INIT_HSMMC2_CLKCTRL, 0x00000003, 0x2);
set_modify(CM_L3INIT_HSMMC2_CLKCTRL, 0x01000000, 0x1 << 24);
set_modify(CM_L4PER_MMCSD3_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL);
set_modify(CM_L4PER_MMCSD4_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD4_CLKCTRL);
set_modify(CM_L4PER_MMCSD5_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_MMCSD5_CLKCTRL);
/* UART clocks */
set_modify(CM_L4PER_UART1_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_UART1_CLKCTRL);
set_modify(CM_L4PER_UART2_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_UART2_CLKCTRL);
set_modify(CM_L4PER_UART3_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_UART3_CLKCTRL);
set_modify(CM_L4PER_UART4_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_UART4_CLKCTRL);
/* WKUP clocks */
set_modify(CM_WKUP_GPIO1_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_WKUP_GPIO1_CLKCTRL);
set_modify(CM_WKUP_TIMER1_CLKCTRL, 0x00000000, 0x01000002);
check_loop(BIT17|BIT16, 0, CM_WKUP_TIMER1_CLKCTRL);
set_modify(CM_WKUP_KEYBOARD_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_WKUP_KEYBOARD_CLKCTRL);
set_modify(CM_SDMA_CLKSTCTRL, 0x00000000, 0x0);
set_modify(CM_MEMIF_CLKSTCTRL, 0x00000000, 0x3);
set_modify(CM_MEMIF_EMIF_1_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_MEMIF_EMIF_1_CLKCTRL);
set_modify(CM_MEMIF_EMIF_2_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_MEMIF_EMIF_2_CLKCTRL);
set_modify(CM_D2D_CLKSTCTRL, 0x00000000, 0x3);
set_modify(CM_L3_2_GPMC_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L3_2_GPMC_CLKCTRL);
set_modify(CM_L3INSTR_L3_3_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L3INSTR_L3_3_CLKCTRL);
set_modify(CM_L3INSTR_L3_INSTR_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L3INSTR_L3_INSTR_CLKCTRL);
set_modify(CM_L3INSTR_OCP_WP1_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L3INSTR_OCP_WP1_CLKCTRL);
/* WDT clocks */
set_modify(CM_WKUP_WDT2_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL);
/* Select DPLL PER CLOCK as source for SGX FCLK */
set_modify(CM_SGX_SGX_CLKCTRL, 0x01000000, 0x1 << 24);
/* Enable clocks for USB fast boot to work */
set_modify(CM_L3INIT_USBPHY_CLKCTRL, 0x00000000, 0x301);
set_modify(CM_L3INIT_HSUSBOTG_CLKCTRL, 0x00000000, 0x1);
return;
}
void advance_frame_ix(void)
/* Move frame counter forward one */
{
vs.frame_ix++;
check_loop();
}
void lock_core_dpll(void)
{
/* Lock the core dpll */
set_modify(CM_CLKMODE_DPLL_CORE, 0x00000007, PLL_LOCK);
check_loop(BIT0, 1, CM_IDLEST_DPLL_CORE);
}
