void __cpuinit platform_secondary_init(unsigned int cpu) { /* Enable the full line of zero */ if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412() || soc_is_exynos4415()) enable_cache_foz(); /* * if any interrupts are already enabled for the primary * core (e.g. timer irq), then they will not have been enabled * for us: do so */ gic_secondary_init(0); /* * let the primary processor know we're out of the * pen, then head off into the C entry point */ write_pen_release(-1); #ifdef CONFIG_ARM_TRUSTZONE clear_boot_flag(cpu, HOTPLUG); #endif /* * Synchronise with the boot thread. */ spin_lock(&boot_lock); spin_unlock(&boot_lock); }
void __cpuinit platform_secondary_init(unsigned int cpu) { /* * if any interrupts are already enabled for the primary * core (e.g. timer irq), then they will not have been enabled * for us: do so */ gic_secondary_init(0); /* * let the primary processor know we're out of the * pen, then head off into the C entry point */ write_pen_release(-1); clear_boot_flag(cpu, HOTPLUG); /* * Synchronise with the boot thread. */ spin_lock(&boot_lock); spin_unlock(&boot_lock); }