// DO NOT MODIFY THE CODE BELOW
int w3_node_init() {
int status;
int ret = XST_SUCCESS;
microblaze_enable_exceptions();
//Initialize the AD9512 clock buffers (RF reference and sampling clocks)
status = clk_init(CLK_BASEADDR, 2);
if(status != XST_SUCCESS) {
xil_printf("w3_node_init: Error in clk_init (%d)\n", status);
ret = XST_FAILURE;
}
status = clk_config_dividers (CLK_BASEADDR, 2, CLK_SAMP_OUTSEL_AD_RFA);
if(status != XST_SUCCESS) {
xil_printf("wclk_config_dividers (%d)\n", status);
ret = XST_FAILURE;
}
//Initialize the AD9963 ADCs/DACs for on-board RF interfaces
ad_init(AD_BASEADDR, (RFA_AD_CS | RFB_AD_CS), 2);
if(status != XST_SUCCESS) {
xil_printf("w3_node_init: Error in ad_init (%d)\n", status);
ret = XST_FAILURE;
}
//Initialize the radio_controller core and MAX2829 transceivers for on-board RF interfaces
status = radio_controller_init(RC_BASEADDR, (RC_RFA | RC_RFB), 1, 1);
if(status != XST_SUCCESS) {
xil_printf("w3_node_init: Error in radioController_initialize (%d)\n", status);
ret = XST_FAILURE;
}
return ret;
}
int w3_node_init() {
int status;
u8 CMswitch;
XTmrCtr *TmrCtrInstancePtr = &TimerCounter;
int ret = XST_SUCCESS;
microblaze_enable_exceptions();
//Initialize the AD9512 clock buffers (RF reference and sampling clocks)
CMswitch = clk_config_read_clkmod_status(CLK_BASEADDR);
status = clk_init(CLK_BASEADDR, 2);
if(status != XST_SUCCESS) {
xil_printf("w3_node_init: Error in clk_init (%d)\n", status);
ret = XST_FAILURE;
}
//Configure this node's clock inputs and outputs, based on the state of the CM-MMCX switch
// If no CM-MMCX is present, CMswitch will read as 0x3 (on-board clock sources, off-board outputs disabled)
switch(CMswitch){
// RF | Sample | Outputs
case 0x0: // Off-Board | Off-Board | Off
clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_OFF, (CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR));
clk_config_input_rf_ref(CLK_BASEADDR, CLK_INSEL_CLKMOD);
xil_printf("\nClock config %d:\n RF: Off-board\n Samp: Off-board\n Off-board Outputs: Disabled\n\n", CMswitch);
break;
case 0x1: // Off-Board | On-Board | Off
clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_OFF, (CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR));
clk_config_input_rf_ref(CLK_BASEADDR, CLK_INSEL_CLKMOD);
xil_printf("\nClock config %d:\n RF: Off-board\n Samp: On-board\n Off-board Outputs: Disabled\n\n", CMswitch);
break;
case 0x2: // On-Board | On-Board | On
clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_ON, (CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR));
clk_config_dividers(CLK_BASEADDR, 1, CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR);
clk_config_input_rf_ref(CLK_BASEADDR, CLK_INSEL_ONBOARD);
xil_printf("\nClock config %d:\n RF: On-board\n Samp: On-board\n Off-board Outputs: Enabled\n\n", CMswitch);
break;
case 0x3: // On-Board | On-Board | Off
clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_OFF, (CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR));
clk_config_input_rf_ref(CLK_BASEADDR, CLK_INSEL_ONBOARD);
//xil_printf("\nClock config %d:\n RF: On-board\n Samp: On-board\n Off-board Outputs: Disabled\n\n", CMswitch);
break;
}
#ifdef WLAN_4RF_EN
//Turn on clocks to FMC
clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_ON, (CLK_SAMP_OUTSEL_FMC | CLK_RFREF_OUTSEL_FMC));
//FMC samp clock divider = 2 (40MHz sampling reference, same as on-board AD9963 ref clk)
clk_config_dividers(CLK_BASEADDR, 2, CLK_SAMP_OUTSEL_FMC);
//FMC RF ref clock divider = 2 (40MHz RF reference, same as on-board MAX2829 ref clk)
clk_config_dividers(CLK_BASEADDR, 2, CLK_RFREF_OUTSEL_FMC);
#endif
//Initialize the AD9963 ADCs/DACs for on-board RF interfaces
ad_init(AD_BASEADDR, AD_ALL_RF, 3);
xil_printf("AD Readback: 0x%08x\n", ad_spi_read(AD_BASEADDR, RFA_AD_CS, 0x32));
if(status != XST_SUCCESS) {
xil_printf("w3_node_init: Error in ad_init (%d)\n", status);
ret = XST_FAILURE;
}
//Initialize the radio_controller core and MAX2829 transceivers for on-board RF interfaces
status = radio_controller_init(RC_BASEADDR, RC_ALL_RF, 1, 1);
if(status != XST_SUCCESS) {
xil_printf("w3_node_init: Error in radioController_initialize (%d)\n", status);
//Comment out allow boot even if an RF interfce doesn't lock (hack for debugging - not for reference release)
ret = XST_FAILURE;
}
//Initialize the EEPROM read/write core
iic_eeprom_init(EEPROM_BASEADDR, 0x64);
#ifdef WLAN_4RF_EN
iic_eeprom_init(FMC_EEPROM_BASEADDR, 0x64);
#endif
//Initialize the timer counter
status = XTmrCtr_Initialize(TmrCtrInstancePtr, TMRCTR_DEVICE_ID);
if (status != XST_SUCCESS) {
xil_printf("w3_node_init: Error in XtmrCtr_Initialize (%d)\n", status);
ret = XST_FAILURE;
}
// Set timer 0 to into a "count down" mode
XTmrCtr_SetOptions(TmrCtrInstancePtr, 0, (XTC_DOWN_COUNT_OPTION));
//Give the PHY control of the red user LEDs (PHY counts 1-hot on SIGNAL errors)
//Note: Uncommenting this line will make the RED LEDs controlled by hardware.
//This will move the LEDs on PHY bad signal events
//userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RED);
return ret;
}
void wlan_radio_init() {
//Setup clocking and filtering (20MSps, 2x interp/decimate in AD9963)
clk_config_dividers(CLK_BASEADDR, 2, (CLK_SAMP_OUTSEL_AD_RFA | CLK_SAMP_OUTSEL_AD_RFB));
ad_config_filters(AD_BASEADDR, AD_ALL_RF, 2, 2);
//Setup RFA
radio_controller_TxRxDisable(RC_BASEADDR, RC_ALL_RF);
radio_controller_apply_TxDCO_calibration(AD_BASEADDR, EEPROM_BASEADDR, (RC_RFA | RC_RFB));
#ifdef WLAN_4RF_EN
radio_controller_apply_TxDCO_calibration(AD_BASEADDR, FMC_EEPROM_BASEADDR, (RC_RFC | RC_RFD));
#endif
radio_controller_setCenterFrequency(RC_BASEADDR, RC_ALL_RF, RC_24GHZ, 4);
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_RSSI_HIGH_BW_EN, 0);
//Filter bandwidths
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_RXHPF_HIGH_CUTOFF_EN, 1);
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_RXLPF_BW, 1);
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_TXLPF_BW, 1);
#if 0
//MGC
radio_controller_setCtrlSource(RC_BASEADDR, RC_ALL_RF, RC_REG0_RXHP_CTRLSRC, RC_CTRLSRC_REG);
radio_controller_setRxHP(RC_BASEADDR, RC_ALL_RF, RC_RXHP_OFF);
radio_controller_setRxGainSource(RC_BASEADDR, RC_ALL_RF, RC_GAINSRC_SPI);
//Set Rx gains
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_RXGAIN_RF, 1);
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_RXGAIN_BB, 8);
#else
//AGC
radio_controller_setCtrlSource(RC_BASEADDR, RC_ALL_RF, RC_REG0_RXHP_CTRLSRC, RC_CTRLSRC_HW);
radio_controller_setRxGainSource(RC_BASEADDR, RC_ALL_RF, RC_GAINSRC_HW);
#endif
//Set Tx gains
//radio_controller_setTxGainSource(RC_BASEADDR, RC_ALL_RF, RC_GAINSRC_REG); //Used for software control of gains
//radio_controller_setTxGainTarget(RC_BASEADDR, RC_ALL_RF, 45);
radio_controller_setTxGainSource(RC_BASEADDR, RC_ALL_RF, RC_GAINSRC_HW); //Used for hardware control of gains
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_TXGAIN_BB, 2);
//Set misc radio params
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_TXLINEARITY_PADRIVER, 0);
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_TXLINEARITY_VGA, 0);
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_TXLINEARITY_UPCONV, 0);
//Set Tx state machine timing (dly_GainRamp, dly_PA, dly_TX, dly_PHY)
radio_controller_setTxDelays(RC_BASEADDR, 40, 20, 0, TX_RC_PHYSTART_DLY); //240 PA time after 180 PHY time is critical point
//Configure the radio_controller Tx/Rx enable control sources
// The Tx PHY drives a 4-bit TxEn, one bit per RF interface
// The Tx PHY drives a 1-bit RxEn, common to all RF interfaces
// MAC software should select active Rx interface by changing RFA/RFB RxEn ctrl src between _HW and _REG
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFA, (RC_REG0_RXEN_CTRLSRC), RC_CTRLSRC_HW);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFB, (RC_REG0_RXEN_CTRLSRC), RC_CTRLSRC_REG);
radio_controller_setCtrlSource(RC_BASEADDR, (RC_RFA | RC_RFB), (RC_REG0_TXEN_CTRLSRC), RC_CTRLSRC_HW);
//Disable any hardware control of RFC/RFD
radio_controller_setCtrlSource(RC_BASEADDR, (RC_RFC | RC_RFD), (RC_REG0_RXEN_CTRLSRC | RC_REG0_TXEN_CTRLSRC), RC_CTRLSRC_REG);
/*
OLD - DELTE WHEN v40 HW WORKS
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFA, (RC_REG0_TXEN_CTRLSRC | RC_REG0_RXEN_CTRLSRC), RC_CTRLSRC_HW);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFB, (RC_REG0_TXEN_CTRLSRC | RC_REG0_RXEN_CTRLSRC), RC_CTRLSRC_REG);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFC, (RC_REG0_TXEN_CTRLSRC | RC_REG0_RXEN_CTRLSRC), RC_CTRLSRC_REG);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFD, (RC_REG0_TXEN_CTRLSRC | RC_REG0_RXEN_CTRLSRC), RC_CTRLSRC_REG);
*/
return;
}
