static void wait_clock(unsigned clk,unsigned dest)
{
char * pszCLK[] = {
NULL,NULL,NULL,"DDR PLL","USB0 CLK","USB1 CLK",
"VID PLL","CLK81",NULL,NULL,NULL,"ETH RMII","VID2 PLL",
};
unsigned cur;
do{
cur=clk_util_clk_msr(clk);
serial_puts("\nSet [");
if(clk < (sizeof(pszCLK)/sizeof(pszCLK[0])) &&
pszCLK[clk])
serial_puts(pszCLK[clk]);
else
serial_puts("N/A");
serial_puts("] to ");
serial_put_dec(dest);
serial_puts("MHz now it is ");
//tolerance +/- 1
if((cur == dest-1) || (cur == dest+1))
serial_put_dec(dest);
else
serial_put_dec(cur);
serial_puts("MHz");
__udelay(100);
}while(cur<dest-1 || cur >dest+1);
serial_puts(" --> OK!\n");
}
static int do_msr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
const char *cmd;
/* need at least two arguments */
if (argc > 2)
goto usage;
int nIndex = 0;
int nCounter = 64;
if( 2 == argc)
{
cmd = argv[1];
char *endp;
nIndex = simple_strtoul(argv[1], &endp, 10);
if(nIndex < 0 || nIndex > 63)
goto usage;
nCounter = 1;
}
extern unsigned long clk_util_clk_msr(unsigned long clk_mux);
//printf("\n");
for(;((nIndex < 64) && nCounter);nCounter--,nIndex++)
printf("MSR clock[%d] = %dMHz\n",nIndex,(int)clk_util_clk_msr(nIndex));
return 0;
usage:
return cmd_usage(cmdtp);
}
__u32 get_misc_pll_clk(void)
{
static __u32 freq=CLK_UNKNOWN;
if(freq==CLK_UNKNOWN)
{
freq=(clk_util_clk_msr(MISC_PLL_CLK)*1000000);
}
return freq;
}
__u32 get_clk_cts_eth_rmii(void)
{
static __u32 freq=CLK_UNKNOWN;
if(freq==CLK_UNKNOWN)
{
freq=(clk_util_clk_msr(CTS_ETH_RMII)*1000000);
}
return freq;
}
__u32 get_clk_ethernet_pad(void)
{
static __u32 freq=CLK_UNKNOWN;
if(freq==CLK_UNKNOWN)
{
freq=(clk_util_clk_msr(MOD_ETH_CLK50_I)*1000000);
}
return freq;
}
__u32 get_clk_ddr(void)
{
static __u32 freq=CLK_UNKNOWN;
if(freq==CLK_UNKNOWN)
{
freq=(clk_util_clk_msr(DDR_PLL_CLK)*1000000);
}
return freq;
}
__u32 get_clk_ddr()
{
static __u32 freq=0;
if(freq==0)
{
freq=(clk_util_clk_msr(DDR_PLL_CLK)*1000000);
}
return freq;
}
__u32 get_cpu_clk(void)
{
static __u32 sys_freq=CLK_UNKNOWN;
if(sys_freq==CLK_UNKNOWN)
{
sys_freq=(clk_util_clk_msr(SYS_PLL_CLK)*1000000);
}
return sys_freq;
}
__u32 get_misc_pll_clk()
{
static __u32 freq=0;
if(freq==0)
{
freq=(clk_util_clk_msr(MISC_PLL_CLK)*1000000);
}
return freq;
}
__u32 get_clk_ethernet_pad()
{
static __u32 freq=0;
if(freq==0)
{
freq=(clk_util_clk_msr(MOD_ETH_CLK50_I)*1000000);
}
return freq;
}
__u32 get_clk_cts_eth_rmii()
{
static __u32 freq=0;
if(freq==0)
{
freq=(clk_util_clk_msr(CTS_ETH_RMII)*1000000);
}
return freq;
}
__u32 get_clk81(void)
{
static __u32 clk81_freq=CLK_UNKNOWN;
if(clk81_freq==CLK_UNKNOWN)
{
clk81_freq=(clk_util_clk_msr(CLK81)*1000000);
}
return clk81_freq;
}
__u32 get_clk81()
{
static __u32 clk81_freq=0;
if(clk81_freq==0)
{
clk81_freq=(clk_util_clk_msr(CLK81)*1000000);
}
return clk81_freq;
}
__u32 get_cpu_clk()
{
static __u32 sys_freq=0;
if(sys_freq==0)
{
sys_freq=(clk_util_clk_msr(SYS_PLL_CLK)*1000000);
}
return sys_freq;
}
STATIC_PREFIX void clk_msr(int argc, char * argv[])
{
unsigned id;
serial_puts(argv[1]);
serial_puts("(Mhz)=");
get_dword(argv[1],&id);
serial_put_dword(clk_util_clk_msr(id));
}
__u32 get_clk81()
{
if(clk81_freq!=0)
return clk81_freq;
if((readl(P_HHI_MPEG_CLK_CNTL)&(1<<8))==0)
{
clk81_freq=CONFIG_CRYSTAL_MHZ*1000000;
return CONFIG_CRYSTAL_MHZ*1000000;
}
clk81_freq=(clk_util_clk_msr(CLK_OTHER_PLL_CLK)*1000000)/((readl(P_HHI_MPEG_CLK_CNTL)&0x7f)+1);
/*
@todo implement this function
*/
return clk81_freq;
}
int sys_clkpll_setting(unsigned crystal_freq, unsigned out_freq)
{
int i, lock_flag;
unsigned lock_time=0;
unsigned long result_freq, target_freq;
unsigned long crys_M, out_M;
unsigned long freq_log[64];
int log_index;
unsigned target_pll_setting;
if (!crystal_freq)
crystal_freq = get_xtal_clock();
crys_M = crystal_freq / 1000000;
out_M = out_freq / 1000000;
i = (out_M-200)/50;
if (i>16) i=16;
target_pll_setting = pll_setting[i][0];
if (READ_MPEG_REG(HHI_SYS_PLL_CNTL)!=target_pll_setting){
WRITE_MPEG_REG(HHI_SYS_PLL_CNTL, target_pll_setting);
WRITE_MPEG_REG(HHI_SYS_PLL_CNTL2, pll_setting[i][1]);
WRITE_MPEG_REG(HHI_SYS_PLL_CNTL3, pll_setting[i][2]);
WRITE_MPEG_REG(RESET5_REGISTER, (1<<2)); // reset sys pll
lock_flag = 0;
log_index = 0;
target_freq = ((target_pll_setting&0x1ff)*crys_M)>>(target_pll_setting>>16);
for (i=0;i<64;i++){
result_freq = clk_util_clk_msr(SYS_PLL_CLK);
if ((result_freq <= target_freq+1)&&(result_freq >= target_freq-1)){
lock_flag++;
if (lock_flag>=1)
break;
}
if (log_index<64)
freq_log[log_index++]=result_freq;
else
break;
lock_time+=64;
}
lock_time-=64;
//printk("sys clk changed");
//for (i=0;i<log_index;i++)
// printk("-%d", freq_log[i]);
//printk("\ncpu_clk_changed: out_freq=%ld,pll_setting=%x,locktime=%dus\n",out_M,target_pll_setting,lock_time);
}
STATIC_PREFIX void pll_clk_list(void)
{
unsigned long clk_freq;
unsigned char clk_list[]={3,10,11};
char *clk_list_name[]={"arm","ddr","other"};
unsigned long i;
for(i=0;i<3;i++)
{
clk_freq = clk_util_clk_msr(clk_list[i] // unsigned long clk_mux, // Measure A9 clock
); // unsigned long uS_gate_time ) // 50us gate time
serial_puts(clk_list_name[i]);
serial_puts("_clk=");
serial_put_dword(clk_freq);
serial_puts("\n");
}
}
int tvoutc_setmode(tvmode_t mode)
{
const reg_t *s;
const tvinfo_t * tvinfo;
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
static int uboot_display_flag = 1;
#else
static int uboot_display_flag = 0;
#endif
if (mode >= TVMODE_MAX) {
printk(KERN_ERR "Invalid video output modes.\n");
return -ENODEV;
}
mutex_lock(&setmode_mutex);
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
//TODO
// switch_mod_gate_by_name("venc", 1);
#endif
tvinfo = tvinfo_mode(mode);
if(!tvinfo) {
printk(KERN_ERR "tvinfo %d not find\n", mode);
mutex_unlock(&setmode_mutex);
return 0;
}
printk("TV mode %s selected.\n", tvinfo->id);
#ifdef CONFIG_ARCH_MESON8B
if( (mode!=TVMODE_480CVBS) && (mode!=TVMODE_576CVBS) )
{
CLK_GATE_OFF(CTS_VDAC);
CLK_GATE_OFF(DAC_CLK);
}
if( (mode!=TVMODE_480I) && (mode!=TVMODE_480CVBS) &&
(mode!=TVMODE_576I) && (mode!=TVMODE_576CVBS) )
{
CLK_GATE_OFF(CTS_ENCI);
CLK_GATE_OFF(VCLK2_ENCI);
CLK_GATE_OFF(VCLK2_VENCI1);
}
#endif
s = tvregs_setting_mode(mode);
if(!s) {
printk("display mode %d regs setting failed\n", mode);
mutex_lock(&setmode_mutex);
return 0;
}
//s = tvregsTab[mode];
if(uboot_display_flag) {
uboot_display_flag = 0;
if(uboot_display_already(mode)) {
printk("already display in uboot\n");
mutex_unlock(&setmode_mutex);
return 0;
}
}
#if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8)
// for hdmi mode, disable HPLL as soon as possible
if( (mode==TVMODE_480I) || (mode==TVMODE_480P) ||
(mode==TVMODE_576I) || (mode==TVMODE_576P) ||
(mode==TVMODE_720P) || (mode==TVMODE_720P_50HZ) ||
(mode==TVMODE_1080I) || (mode==TVMODE_1080I_50HZ) ||
(mode==TVMODE_1080P) || (mode==TVMODE_1080P_50HZ) ||
(mode==TVMODE_1080P_24HZ) || (mode==TVMODE_4K2K_24HZ) ||
(mode==TVMODE_4K2K_25HZ) || (mode==TVMODE_4K2K_30HZ) || (mode==TVMODE_4K2K_FAKE_5G) ||
(mode==TVMODE_4K2K_SMPTE) || (mode==TVMODE_4K2K_60HZ) )
{
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV
// NOTE: for G9TV, DO NOT TURN OFF HPLL
#else
WRITE_CBUS_REG_BITS(HHI_VID_PLL_CNTL, 0x0, 30, 1);
#endif
}
cvbs_cntl_output(0);
#endif
while (MREG_END_MARKER != s->reg)
setreg(s++);
printk("%s[%d]\n", __func__, __LINE__);
#ifdef CONFIG_CVBS_PERFORMANCE_COMPATIBLITY_SUPPORT
cvbs_performance_enhancement(mode);
#endif
if(mode >= TVMODE_VGA && mode <= TVMODE_FHDVGA){ //set VGA pinmux
aml_write_reg32(P_PERIPHS_PIN_MUX_0, (aml_read_reg32(P_PERIPHS_PIN_MUX_0)|(3<<20)));
}else{
aml_write_reg32(P_PERIPHS_PIN_MUX_0, (aml_read_reg32(P_PERIPHS_PIN_MUX_0)&(~(3<<20))));
}
printk("%s[%d] mode is %d\n", __func__, __LINE__, mode);
#if ((defined CONFIG_ARCH_MESON8) || (defined CONFIG_ARCH_MESON8B))
// for hdmi mode, leave the hpll setting to be done by hdmi module.
if( (mode==TVMODE_480CVBS) || (mode==TVMODE_576CVBS) )
set_tvmode_misc(mode);
#else
set_tvmode_misc(mode);
#endif
#ifdef CONFIG_ARCH_MESON1
tvoutc_setclk(mode);
printk("%s[%d]\n", __func__, __LINE__);
enable_vsync_interrupt();
#endif
#ifdef CONFIG_AM_TV_OUTPUT2
switch(mode)
{
case TVMODE_480I:
case TVMODE_480I_RPT:
case TVMODE_480CVBS:
case TVMODE_576I:
case TVMODE_576I_RPT:
case TVMODE_576CVBS:
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 1, 0, 2); //reg0x271a, select ENCI to VIU1
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 1, 4, 4); //reg0x271a, Select encI clock to VDIN
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 1, 8, 4); //reg0x271a,Enable VIU of ENC_I domain to VDIN;
break;
case TVMODE_480P:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_480P_59HZ:
#endif
case TVMODE_480P_RPT:
case TVMODE_576P:
case TVMODE_576P_RPT:
case TVMODE_720P:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_720P_59HZ:
#endif
case TVMODE_720P_50HZ:
case TVMODE_1080I: //??
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_1080I_59HZ:
#endif
case TVMODE_1080I_50HZ: //??
case TVMODE_1080P:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_1080P_59HZ:
#endif
case TVMODE_1080P_50HZ:
case TVMODE_1080P_24HZ:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_1080P_23HZ:
#endif
case TVMODE_4K2K_30HZ:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_4K2K_29HZ:
#endif
case TVMODE_4K2K_25HZ:
case TVMODE_4K2K_24HZ:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_4K2K_23HZ:
#endif
case TVMODE_4K2K_SMPTE:
case TVMODE_4K2K_FAKE_5G:
case TVMODE_4K2K_60HZ:
case TVMODE_VGA:
case TVMODE_SVGA:
case TVMODE_XGA:
case TVMODE_SXGA:
case TVMODE_WSXGA:
case TVMODE_FHDVGA:
default:
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 0, 2); //reg0x271a, select ENCP to VIU1
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 4, 4); //reg0x271a, Select encP clock to VDIN
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 8, 4); //reg0x271a,Enable VIU of ENC_P domain to VDIN;
break;
}
#endif
aml_write_reg32(P_VPP_POSTBLEND_H_SIZE, tvinfo->xres);
#ifdef CONFIG_ARCH_MESON3
printk(" clk_util_clk_msr 6 = %d\n", clk_util_clk_msr(6));
printk(" clk_util_clk_msr 7 = %d\n", clk_util_clk_msr(7));
printk(" clk_util_clk_msr 8 = %d\n", clk_util_clk_msr(8));
printk(" clk_util_clk_msr 9 = %d\n", clk_util_clk_msr(9));
printk(" clk_util_clk_msr 10 = %d\n", clk_util_clk_msr(10));
printk(" clk_util_clk_msr 27 = %d\n", clk_util_clk_msr(27));
printk(" clk_util_clk_msr 29 = %d\n", clk_util_clk_msr(29));
#endif
#ifdef CONFIG_ARCH_MESON6
if( (mode==TVMODE_480CVBS) || (mode==TVMODE_576CVBS) )
{
msleep(1000);
if(get_power_level() == 0) {
aml_write_reg32(P_VENC_VDAC_SETTING, 0x5);
} else {
aml_write_reg32(P_VENC_VDAC_SETTING, 0x7);
}
} else {
if(get_power_level() == 0) {
aml_write_reg32(P_VENC_VDAC_SETTING, 0x0);
} else {
aml_write_reg32(P_VENC_VDAC_SETTING, 0x7);
}
}
#endif
#if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8)
if( (mode==TVMODE_480CVBS) || (mode==TVMODE_576CVBS) )
{
msleep(1000);
CLK_GATE_ON(VCLK2_ENCI);
CLK_GATE_ON(VCLK2_VENCI1);
CLK_GATE_ON(CTS_ENCI);
CLK_GATE_ON(CTS_VDAC);
CLK_GATE_ON(DAC_CLK);
cvbs_cntl_output(1);
}
#endif
//while(1);
mutex_unlock(&setmode_mutex);
return 0;
}
int tvoutc_setmode2(tvmode_t mode)
{
const reg_t *s;
if (mode >= TVMODE_MAX) {
printk(KERN_ERR "Invalid video output modes.\n");
return -ENODEV;
}
printk(KERN_DEBUG "TV mode %s selected.\n", tvinfoTab[mode].id);
s = tvregsTab[mode];
while (MREG_END_MARKER != s->reg)
setreg(s++);
//tvoutc_setclk2(mode);
//enable_vsync_interrupt();
switch(mode)
{
case TVMODE_480I:
case TVMODE_480CVBS:
case TVMODE_480P:
case TVMODE_576I:
case TVMODE_576CVBS:
case TVMODE_576P:
//WRITE_MPEG_REG(HHI_VIID_CLK_DIV, (READ_MPEG_REG(HHI_VIID_CLK_DIV)&(~(0xff)))|0x3); // reg 0x104a
break;
case TVMODE_720P:
case TVMODE_720P_50HZ:
case TVMODE_1080I:
case TVMODE_1080I_50HZ:
//WRITE_MPEG_REG(HHI_VIID_CLK_DIV, (READ_MPEG_REG(HHI_VIID_CLK_DIV)&(~(0xff)))|0x0); // reg 0x104a
break;
case TVMODE_1080P:
case TVMODE_1080P_50HZ:
//WRITE_MPEG_REG(HHI_VIID_CLK_DIV, (READ_MPEG_REG(HHI_VIID_CLK_DIV)&(~(0xff)))|0x1); // reg 0x104a
break;
default:
printk(KERN_ERR "unsupport tv mode,video clk is not set!!\n");
}
//WRITE_MPEG_REG(HHI_VIID_CLK_CNTL, 0x8001f); //reg 0x104b, select vid_pll_clk as source of v2_clk_divN
//WRITE_MPEG_REG(HHI_VID_CLK_DIV, (READ_MPEG_REG(HHI_VID_CLK_DIV)&(~(0xff<<24)))|(0x88<<24)); // reg 0x1059, select cts_encp_clk and cts_enci_clk from v2_clk_div1
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 2, 2); //reg0x271a, select ENCP to VIU2
aml_write_reg32(P_VPP2_POSTBLEND_H_SIZE, tvinfoTab[mode].xres);
// For debug only
#if 0
printk(" clk_util_clk_msr 6 = %d\n", clk_util_clk_msr(6));
printk(" clk_util_clk_msr 7 = %d\n", clk_util_clk_msr(7));
printk(" clk_util_clk_msr 8 = %d\n", clk_util_clk_msr(8));
printk(" clk_util_clk_msr 9 = %d\n", clk_util_clk_msr(9));
printk(" clk_util_clk_msr 10 = %d\n", clk_util_clk_msr(10));
printk(" clk_util_clk_msr 27 = %d\n", clk_util_clk_msr(27));
printk(" clk_util_clk_msr 29 = %d\n", clk_util_clk_msr(29));
#endif
//while(1);
return 0;
}
int tvoutc_setmode(tvmode_t mode)
{
const reg_t *s;
if (mode >= TVMODE_MAX) {
printk(KERN_ERR "Invalid video output modes.\n");
return -ENODEV;
}
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
switch_mod_gate_by_name("venc", 1);
#endif
printk(KERN_DEBUG "TV mode %s selected.\n", tvinfoTab[mode].id);
s = tvregsTab[mode];
while (MREG_END_MARKER != s->reg)
setreg(s++);
printk("%s[%d]\n", __func__, __LINE__);
// if (mode < TVMODE_VGA)
set_tvmode_misc(mode);
#ifdef CONFIG_ARCH_MESON1
tvoutc_setclk(mode);
printk("%s[%d]\n", __func__, __LINE__);
enable_vsync_interrupt();
#endif
#ifdef CONFIG_AM_TV_OUTPUT2
switch(mode)
{
case TVMODE_480I:
case TVMODE_480CVBS:
case TVMODE_576I:
case TVMODE_576CVBS:
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 1, 0, 2); //reg0x271a, select ENCI to VIU1
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 1, 4, 4); //reg0x271a, Select encI clock to VDIN
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 1, 8, 4); //reg0x271a,Enable VIU of ENC_I domain to VDIN;
break;
case TVMODE_480P:
case TVMODE_576P:
case TVMODE_720P:
case TVMODE_720P_50HZ:
case TVMODE_1080I: //??
case TVMODE_1080I_50HZ: //??
case TVMODE_1080P:
case TVMODE_1080P_50HZ:
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 2, 0, 2); //reg0x271a, select ENCP to VIU1
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 2, 4, 4); //reg0x271a, Select encP clock to VDIN
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 2, 8, 4); //reg0x271a,Enable VIU of ENC_P domain to VDIN;
break;
default:
printk(KERN_ERR "unsupport tv mode,video clk is not set!!\n");
}
#endif
WRITE_MPEG_REG(VPP_POSTBLEND_H_SIZE, tvinfoTab[mode].xres);
#ifdef CONFIG_ARCH_MESON3
printk(" clk_util_clk_msr 6 = %d\n", clk_util_clk_msr(6));
printk(" clk_util_clk_msr 7 = %d\n", clk_util_clk_msr(7));
printk(" clk_util_clk_msr 8 = %d\n", clk_util_clk_msr(8));
printk(" clk_util_clk_msr 9 = %d\n", clk_util_clk_msr(9));
printk(" clk_util_clk_msr 10 = %d\n", clk_util_clk_msr(10));
printk(" clk_util_clk_msr 27 = %d\n", clk_util_clk_msr(27));
printk(" clk_util_clk_msr 29 = %d\n", clk_util_clk_msr(29));
#endif
//while(1);
return 0;
}
int tvoutc_setmode2(tvmode_t mode)
{
const reg_t *s;
if (mode >= TVMODE_MAX) {
printk(KERN_ERR "Invalid video output modes.\n");
return -ENODEV;
}
printk(KERN_DEBUG "TV mode %s selected.\n", tvinfoTab[mode].id);
s = tvregsTab[mode];
while (MREG_END_MARKER != s->reg)
setreg(s++);
//tvoutc_setclk2(mode);
//enable_vsync_interrupt();
switch(mode)
{
case TVMODE_480I:
case TVMODE_480CVBS:
case TVMODE_576I:
case TVMODE_576CVBS:
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 1, 2, 2); //reg0x271a, select ENCT to VIU2
/*set VID2 for EncI*/
WRITE_MPEG_REG(HHI_VIID_PLL_CNTL, 0x20224); //reg 0x1047
WRITE_MPEG_REG(HHI_VIID_DIVIDER_CNTL, 0x18803); //reg 0x104c, //VID2_PLL_CLK: 216MHz
WRITE_CBUS_REG_BITS(HHI_VIID_CLK_DIV, 0x3, 0, 8); //0x104a, =>54MHz
WRITE_MPEG_REG(HHI_VIID_CLK_CNTL, 0xc001f); //reg 0x104b, select vid_pll2_clk for vi2_clk_div?
WRITE_CBUS_REG_BITS(HHI_VID_CLK_DIV, 0x9, 28, 4); //reg 0x1059, select v2_clk_div2 for cts_enci_clk , 27MHz
WRITE_CBUS_REG_BITS(HHI_VIID_CLK_DIV, 0x9, 24, 4); //0x104a, select v2_clk_div2 for cts_vdac_clk[1] (DAC3)
WRITE_MPEG_REG(HHI_VIID_PLL_CNTL2, 0x065e31ff);
WRITE_MPEG_REG(HHI_VIID_PLL_CNTL3, 0x1649a941);
break;
case TVMODE_480P:
case TVMODE_576P:
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 2, 2, 2); //reg0x271a, select ENCP to VIU2
break;
case TVMODE_720P:
case TVMODE_720P_50HZ:
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 2, 2, 2); //reg0x271a, select ENCP to VIU2
break;
case TVMODE_1080I:
case TVMODE_1080I_50HZ:
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 2, 2, 2); //reg0x271a, select ENCP to VIU2
break;
case TVMODE_1080P:
case TVMODE_1080P_50HZ:
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 2, 2, 2); //reg0x271a, select ENCP to VIU2
break;
default:
printk(KERN_ERR "unsupport tv mode,video clk is not set!!\n");
}
//WRITE_MPEG_REG(HHI_VIID_CLK_CNTL, 0x8001f); //reg 0x104b, select vid_pll_clk as source of v2_clk_divN
//WRITE_MPEG_REG(HHI_VID_CLK_DIV, (READ_MPEG_REG(HHI_VID_CLK_DIV)&(~(0xff<<24)))|(0x88<<24)); // reg 0x1059, select cts_encp_clk and cts_enci_clk from v2_clk_div1
WRITE_MPEG_REG(VPP2_POSTBLEND_H_SIZE, tvinfoTab[mode].xres);
// For debug only
#if 0
printk(" clk_util_clk_msr 6 = %d\n", clk_util_clk_msr(6));
printk(" clk_util_clk_msr 7 = %d\n", clk_util_clk_msr(7));
printk(" clk_util_clk_msr 8 = %d\n", clk_util_clk_msr(8));
printk(" clk_util_clk_msr 9 = %d\n", clk_util_clk_msr(9));
printk(" clk_util_clk_msr 10 = %d\n", clk_util_clk_msr(10));
printk(" clk_util_clk_msr 27 = %d\n", clk_util_clk_msr(27));
printk(" clk_util_clk_msr 29 = %d\n", clk_util_clk_msr(29));
#endif
//while(1);
return 0;
}
static int do_tv_pll_calc(int argc, char *argv[])
{
printf("DDR_PLL_CLK: %uMHz\n", clk_util_clk_msr(DDR_PLL_CLK));
printf("CTS_A9_CLK: %uMHz\n", clk_util_clk_msr(CTS_A9_CLK));
printf("AUD_PLL_CLK: %uMHz\n", clk_util_clk_msr(AUD_PLL_CLK));
printf("VID_PLL_CLK: %uMHz\n", clk_util_clk_msr(VID_PLL_CLK));
#ifdef CONFIG_AML_MESION_3
printf("SYS_PLL_CLK: %uMHz\n", clk_util_clk_msr(SYS_PLL_CLK));
printf("MISC_PLL_CLK: %uMHz\n", clk_util_clk_msr(MISC_PLL_CLK));
printf("CLK81: %uMHz\n", clk_util_clk_msr(CLK81));
printf("CTS_ENCP_CLK: %uMHz\n", clk_util_clk_msr(CTS_ENCP_CLK));
printf("CTS_ENCL_CLK: %uMHz\n", clk_util_clk_msr(CTS_ENCL_CLK));
printf("CTS_ENCT_CLK: %uMHz\n", clk_util_clk_msr(CTS_ENCT_CLK));
printf("VID2_PLL_CLK: %uMHz\n", clk_util_clk_msr(VID2_PLL_CLK));
printf("CTS_AMCLK: %uMHz\n", clk_util_clk_msr(CTS_AMCLK));
printf("CTS_HDMI_SYS_CLK: %uMHz\n", clk_util_clk_msr(CTS_HDMI_SYS_CLK));
printf("MOD_AUDIN_AMCLK_I: %uMHz\n", clk_util_clk_msr(MOD_AUDIN_AMCLK_I));
printf("HDMI_CH3_TMDSCLK: %uMHz\n", clk_util_clk_msr(HDMI_CH3_TMDSCLK));
printf("LVDS_FIFO_CLK: %uMHz\n", clk_util_clk_msr(LVDS_FIFO_CLK));
printf("CTS_ENCI_CLK: %uMHz\n", clk_util_clk_msr(CTS_ENCI_CLK));
printf("CTS_VDAC_CLK0: %uMHz\n", clk_util_clk_msr(CTS_VDAC_CLK0));
printf("CTS_DDR_CLK: %uMHz\n", clk_util_clk_msr(CTS_DDR_CLK));
printf("CTS_HDMI_TX_PIXEL_CLK: %uMHz\n", clk_util_clk_msr(CTS_HDMI_TX_PIXEL_CLK));
printf("CTS_VDAC_CLK1: %uMHz\n", clk_util_clk_msr(CTS_VDAC_CLK1));
#endif
return 0;
}
int tvoutc_setmode(tvmode_t mode)
{
const reg_t *s;
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
static int uboot_display_flag = 1;
#else
static int uboot_display_flag = 0;
#endif
if (mode >= TVMODE_MAX) {
printk(KERN_ERR "Invalid video output modes.\n");
return -ENODEV;
}
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
//TODO
// switch_mod_gate_by_name("venc", 1);
#endif
printk("TV mode %s selected.\n", tvinfoTab[mode].id);
s = tvregsTab[mode];
if(uboot_display_flag) {
uboot_display_flag = 0;
if(uboot_display_already(mode)) {
printk("already display in uboot\n");
return 0;
}
}
while (MREG_END_MARKER != s->reg)
setreg(s++);
printk("%s[%d]\n", __func__, __LINE__);
if(mode >= TVMODE_VGA || mode <= TVMODE_SXGA){
aml_write_reg32(P_PERIPHS_PIN_MUX_0,aml_read_reg32(P_PERIPHS_PIN_MUX_0)|(3<<20));
}else{
aml_write_reg32(P_PERIPHS_PIN_MUX_0,aml_read_reg32(P_PERIPHS_PIN_MUX_0)&(~(3<<20)));
}
set_tvmode_misc(mode);
#ifdef CONFIG_ARCH_MESON1
tvoutc_setclk(mode);
printk("%s[%d]\n", __func__, __LINE__);
enable_vsync_interrupt();
#endif
#ifdef CONFIG_AM_TV_OUTPUT2
switch(mode)
{
case TVMODE_480I:
case TVMODE_480CVBS:
case TVMODE_576I:
case TVMODE_576CVBS:
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 1, 0, 2); //reg0x271a, select ENCI to VIU1
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 1, 4, 4); //reg0x271a, Select encI clock to VDIN
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 1, 8, 4); //reg0x271a,Enable VIU of ENC_I domain to VDIN;
break;
case TVMODE_480P:
case TVMODE_576P:
case TVMODE_720P:
case TVMODE_720P_50HZ:
case TVMODE_1080I: //??
case TVMODE_1080I_50HZ: //??
case TVMODE_1080P:
case TVMODE_1080P_50HZ:
case TVMODE_1080P_24HZ:
case TVMODE_4K2K_30HZ:
case TVMODE_4K2K_25HZ:
case TVMODE_4K2K_24HZ:
case TVMODE_4K2K_SMPTE:
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 0, 2); //reg0x271a, select ENCP to VIU1
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 4, 4); //reg0x271a, Select encP clock to VDIN
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 8, 4); //reg0x271a,Enable VIU of ENC_P domain to VDIN;
break;
default:
printk(KERN_ERR "unsupport tv mode,video clk is not set!!\n");
}
#endif
aml_write_reg32(P_VPP_POSTBLEND_H_SIZE, tvinfoTab[mode].xres);
#ifdef CONFIG_ARCH_MESON3
printk(" clk_util_clk_msr 6 = %d\n", clk_util_clk_msr(6));
printk(" clk_util_clk_msr 7 = %d\n", clk_util_clk_msr(7));
printk(" clk_util_clk_msr 8 = %d\n", clk_util_clk_msr(8));
printk(" clk_util_clk_msr 9 = %d\n", clk_util_clk_msr(9));
printk(" clk_util_clk_msr 10 = %d\n", clk_util_clk_msr(10));
printk(" clk_util_clk_msr 27 = %d\n", clk_util_clk_msr(27));
printk(" clk_util_clk_msr 29 = %d\n", clk_util_clk_msr(29));
#endif
#ifdef CONFIG_ARCH_MESON8
if( (mode==TVMODE_480CVBS) || (mode==TVMODE_576CVBS) )
{
msleep(1000);
aml_write_reg32(P_HHI_VDAC_CNTL0,0x650001);
aml_write_reg32(P_HHI_VDAC_CNTL1,0x1);
}
#endif
//while(1);
return 0;
}
