void cmd_frequency(int argc, char** argv) {
bufferPrintf("Clock frequency: %d Hz\r\n", clock_get_frequency(FrequencyBaseClock));
bufferPrintf("Memory frequency: %d Hz\r\n", clock_get_frequency(FrequencyBaseMemory));
bufferPrintf("Bus frequency: %d Hz\r\n", clock_get_frequency(FrequencyBaseBus));
bufferPrintf("Unknown frequency: %d Hz\r\n", clock_get_frequency(FrequencyBaseUnknown));
bufferPrintf("Peripheral frequency: %d Hz\r\n", clock_get_frequency(FrequencyBasePeripheral));
bufferPrintf("Display frequency: %d Hz\r\n", clock_get_frequency(FrequencyBaseDisplay));
bufferPrintf("Fixed frequency: %d Hz\r\n", clock_get_frequency(FrequencyBaseFixed));
bufferPrintf("Timebase frequency: %d Hz\r\n", clock_get_frequency(FrequencyBaseTimebase));
bufferPrintf("Usbphy frequency: %d Hz\r\n", clock_get_frequency(FrequencyBaseUsbPhy));
}
void spi_set_baud(int _bus, int _baud, SPIWordSize _wordSize, int _isMaster, int cpol, int cpha)
{
if(_bus < 0 || _bus >= SPICount)
return;
uint32_t wordSize;
switch(_wordSize)
{
case 8:
wordSize = 0;
break;
case 16:
wordSize = 1;
break;
case 32:
wordSize = 2;
break;
default:
return;
}
SPIStruct *spi = &SPIData[_bus];
spi->wordSize = wordSize;
SET_REG(spi->registers->control, 0);
spi->config = (_isMaster)? 0x18 : 0;
uint32_t freq = clock_get_frequency(spi->clockSource == NCLK? FrequencyBaseFixed: FrequencyBasePeripheral);
uint32_t div = 1;
if(_baud > 0)
div = freq/_baud;
spi->config |= (cpha << 1)
| (cpol << 2)
| (wordSize << SPISETUP_WORDSIZE_SHIFT)
| (0x20); // or 0x40, (but this never arises in iBoot).
if(spi->clockSource == NCLK)
spi->config |= SPISETUP_CLOCKSOURCE;
//bufferPrintf("spi: set_baud(%d) isMaster=%d, config=0x%08x, div=%d.\n", _bus, _isMaster, spi->config, div);
SET_REG(spi->registers->clkDiv, div);
SET_REG(spi->registers->config, spi->config);
SET_REG(spi->registers->pin, 2);
SET_REG(spi->registers->control, 1);
}
void usb_phy_init() {
// power on PHY
SET_REG(USB_PHY + OPHYPWR, OPHYPWR_POWERON);
udelay(USB_PHYPWRPOWERON_DELAYUS);
SET_REG(USB_PHY + OPHYUNK1, OPHYUNK1_START);
SET_REG(USB_PHY + OPHYUNK2, OPHYUNK2_START);
// select clock
uint32_t phyClockBits;
switch (clock_get_frequency(FrequencyBaseUsbPhy))
{
case OPHYCLK_SPEED_12MHZ:
phyClockBits = OPHYCLK_CLKSEL_12MHZ;
break;
case OPHYCLK_SPEED_24MHZ:
phyClockBits = OPHYCLK_CLKSEL_24MHZ;
break;
case OPHYCLK_SPEED_48MHZ:
phyClockBits = OPHYCLK_CLKSEL_48MHZ;
break;
default:
phyClockBits = OPHYCLK_CLKSEL_OTHER;
break;
}
SET_REG(USB_PHY + OPHYCLK, (GET_REG(USB_PHY + OPHYCLK) & ~OPHYCLK_CLKSEL_MASK) | phyClockBits);
// reset phy
SET_REG(USB_PHY + ORSTCON, GET_REG(USB_PHY + ORSTCON) | ORSTCON_PHYSWRESET);
udelay(USB_RESET2_DELAYUS);
SET_REG(USB_PHY + ORSTCON, GET_REG(USB_PHY + ORSTCON) & (~ORSTCON_PHYSWRESET));
udelay(USB_RESET_DELAYUS);
}
uint32_t clock_calculate_frequency(uint32_t pdiv, uint32_t mdiv, FrequencyBase freqBase) {
unsigned int y = clock_get_frequency(freqBase) / (0x1 << ClockSDiv);
uint64_t z = (((uint64_t) pdiv) * ((uint64_t) 1000000000)) / ((uint64_t) y);
uint64_t divResult = ((uint64_t)(1000000 * mdiv)) / z;
return divResult - 1;
}
int nand_setup() {
if(HasNANDInit)
return 0;
NANDSetting1 = 7;
NANDSetting2 = 7;
NANDSetting3 = 7;
NANDSetting4 = 7;
bufferPrintf("nand: Probing flash controller...\r\n");
clock_gate_switch(NAND_CLOCK_GATE1, ON);
clock_gate_switch(NAND_CLOCK_GATE2, ON);
int bank;
for(bank = 0; bank < NAND_NUM_BANKS; bank++) {
banksTable[bank] = bank;
}
NumValidBanks = 0;
const NANDDeviceType* nandType = NULL;
SET_REG(NAND + NAND_SETUP, 0);
SET_REG(NAND + NAND_SETUP, GET_REG(NAND + NAND_SETUP) | (ECCType << 4));
for(bank = 0; bank < NAND_NUM_BANKS; bank++) {
nand_bank_reset(bank, 100);
SET_REG(NAND + NAND_CON, NAND_CON_SETTING1);
SET_REG(NAND + NAND_CONFIG,
((NANDSetting1 & NAND_CONFIG_SETTING1MASK) << NAND_CONFIG_SETTING1SHIFT) | ((NANDSetting2 & NAND_CONFIG_SETTING2MASK) << NAND_CONFIG_SETTING2SHIFT)
| (1 << (banksTable[bank] + 1)) | NAND_CONFIG_DEFAULTS);
SET_REG(NAND + NAND_CMD, NAND_CMD_ID);
wait_for_ready(500);
SET_REG(NAND + NAND_CONFIG4, 0);
SET_REG(NAND + NAND_CONFIG3, 0);
SET_REG(NAND + NAND_CON, NAND_CON_ADDRESSDONE);
wait_for_address_complete(500);
nand_bank_reset_helper(bank, 100);
SET_REG(NAND + NAND_TRANSFERSIZE, 8);
SET_REG(NAND + NAND_CON, NAND_CON_BEGINTRANSFER);
wait_for_status_bit_3(500);
uint32_t id = GET_REG(NAND + NAND_DMA_SOURCE);
const NANDDeviceType* candidate = SupportedDevices;
while(candidate->id != 0) {
if(candidate->id == id) {
if(nandType == NULL) {
nandType = candidate;
} else if(nandType != candidate) {
bufferPrintf("nand: Mismatched device IDs (0x%08x after 0x%08x)\r\n", id, nandType->id);
return ERROR_ARG;
}
banksTable[NumValidBanks++] = bank;
}
candidate++;
}
SET_REG(NAND + NAND_CON, NAND_CON_SETTING1);
}
if(nandType == NULL) {
bufferPrintf("nand: No supported NAND found\r\n");
return ERROR_ARG;
}
Data.DeviceID = nandType->id;
Data.banksTable = banksTable;
NANDSetting2 = (((clock_get_frequency(FrequencyBaseBus) * (nandType->NANDSetting2 + 1)) + 99999999)/100000000) - 1;
NANDSetting1 = (((clock_get_frequency(FrequencyBaseBus) * (nandType->NANDSetting1 + 1)) + 99999999)/100000000) - 1;
NANDSetting3 = (((clock_get_frequency(FrequencyBaseBus) * (nandType->NANDSetting3 + 1)) + 99999999)/100000000) - 1;
NANDSetting4 = (((clock_get_frequency(FrequencyBaseBus) * (nandType->NANDSetting4 + 1)) + 99999999)/100000000) - 1;
if(NANDSetting2 > 7)
NANDSetting2 = 7;
if(NANDSetting1 > 7)
NANDSetting1 = 7;
if(NANDSetting3 > 7)
NANDSetting3 = 7;
if(NANDSetting4 > 7)
NANDSetting4 = 7;
Data.blocksPerBank = nandType->blocksPerBank;
Data.banksTotal = NumValidBanks;
Data.sectorsPerPage = nandType->sectorsPerPage;
Data.userSubBlksTotal = nandType->userSubBlksTotal;
Data.bytesPerSpare = nandType->bytesPerSpare;
Data.field_2E = 4;
Data.field_2F = 3;
Data.pagesPerBlock = nandType->pagesPerBlock;
if(Data.sectorsPerPage > 4) {
LargePages = TRUE;
} else {
LargePages = FALSE;
}
if(nandType->ecc1 == 6) {
ECCType = 4;
TotalECCDataSize = Data.sectorsPerPage * 15;
} else if(nandType->ecc1 == 8) {
ECCType = 8;
TotalECCDataSize = Data.sectorsPerPage * 20;
} else if(nandType->ecc1 == 4) {
ECCType = 0;
TotalECCDataSize = Data.sectorsPerPage * 10;
}
if(nandType->ecc2 == 6) {
ECCType2 = 4;
} else if(nandType->ecc2 == 8) {
ECCType2 = 8;
} else if(nandType->ecc2 == 4) {
ECCType2 = 0;
}
Data.field_4 = 5;
Data.bytesPerPage = SECTOR_SIZE * Data.sectorsPerPage;
Data.pagesPerBank = Data.pagesPerBlock * Data.blocksPerBank;
Data.pagesTotal = Data.pagesPerBank * Data.banksTotal;
Data.pagesPerSubBlk = Data.pagesPerBlock * Data.banksTotal;
Data.userPagesTotal = Data.userSubBlksTotal * Data.pagesPerSubBlk;
Data.subBlksTotal = (Data.banksTotal * Data.blocksPerBank) / Data.banksTotal;
Data2.field_2 = Data.subBlksTotal - Data.userSubBlksTotal - 28;
Data2.field_0 = Data2.field_2 + 4;
Data2.field_4 = Data2.field_2 + 5;
Data2.field_6 = 3;
Data2.field_8 = 23;
if(Data2.field_8 == 0)
Data.field_22 = 0;
int bits = 0;
int i = Data2.field_8;
while((i <<= 1) != 0) {
bits++;
}
Data.field_22 = bits;
bufferPrintf("nand: DEVICE: %08x\r\n", Data.DeviceID);
bufferPrintf("nand: BANKS_TOTAL: %d\r\n", Data.banksTotal);
bufferPrintf("nand: BLOCKS_PER_BANK: %d\r\n", Data.blocksPerBank);
bufferPrintf("nand: SUBLKS_TOTAL: %d\r\n", Data.subBlksTotal);
bufferPrintf("nand: USER_SUBLKS_TOTAL: %d\r\n", Data.userSubBlksTotal);
bufferPrintf("nand: PAGES_PER_SUBLK: %d\r\n", Data.pagesPerSubBlk);
bufferPrintf("nand: PAGES_PER_BANK: %d\r\n", Data.pagesPerBank);
bufferPrintf("nand: SECTORS_PER_PAGE: %d\r\n", Data.sectorsPerPage);
bufferPrintf("nand: BYTES_PER_SPARE: %d\r\n", Data.bytesPerSpare);
bufferPrintf("nand: BYTES_PER_PAGE: %d\r\n", Data.bytesPerPage);
bufferPrintf("nand: PAGES_PER_BLOCK: %d\r\n", Data.pagesPerBlock);
aTemporaryReadEccBuf = (uint8_t*) malloc(Data.bytesPerPage);
memset(aTemporaryReadEccBuf, 0xFF, SECTOR_SIZE);
aTemporarySBuf = (uint8_t*) malloc(Data.bytesPerSpare);
HasNANDInit = TRUE;
return 0;
}
int nand_setup() {
if(HasNANDInit)
return 0;
WEHighHoldTime = 7;
WPPulseTime = 7;
NANDSetting3 = 7;
NANDSetting4 = 7;
bufferPrintf("nand: Probing flash controller...\r\n");
clock_gate_switch(NAND_CLOCK_GATE1, ON);
clock_gate_switch(NAND_CLOCK_GATE2, ON);
int bank;
for(bank = 0; bank < NAND_NUM_BANKS; bank++) {
banksTable[bank] = bank;
}
NumValidBanks = 0;
const NANDDeviceType* nandType = NULL;
SET_REG(NAND + RSCTRL, 0);
SET_REG(NAND + RSCTRL, GET_REG(NAND + RSCTRL) | (ECCType << 4));
for(bank = 0; bank < NAND_NUM_BANKS; bank++) {
nand_bank_reset(bank, 100);
SET_REG(NAND + FMCTRL1, FMCTRL1_FLUSHFIFOS);
SET_REG(NAND + FMCTRL0,
((WEHighHoldTime & FMCTRL_TWH_MASK) << FMCTRL_TWH_SHIFT) | ((WPPulseTime & FMCTRL_TWP_MASK) << FMCTRL_TWP_SHIFT)
| (1 << (banksTable[bank] + 1)) | FMCTRL0_ON | FMCTRL0_WPB);
SET_REG(NAND + NAND_CMD, NAND_CMD_ID);
wait_for_ready(500);
SET_REG(NAND + FMANUM, 0);
SET_REG(NAND + FMADDR0, 0);
SET_REG(NAND + FMCTRL1, FMCTRL1_DOTRANSADDR);
wait_for_address_done(500);
wait_for_command_done(bank, 100);
SET_REG(NAND + FMDNUM, 8);
SET_REG(NAND + FMCTRL1, FMCTRL1_DOREADDATA);
wait_for_transfer_done(500);
uint32_t id = GET_REG(NAND + FMFIFO);
const NANDDeviceType* candidate = SupportedDevices;
while(candidate->id != 0) {
if(candidate->id == id) {
if(nandType == NULL) {
nandType = candidate;
} else if(nandType != candidate) {
bufferPrintf("nand: Mismatched device IDs (0x%08x after 0x%08x)\r\n", id, nandType->id);
return ERROR_ARG;
}
banksTable[NumValidBanks++] = bank;
}
candidate++;
}
SET_REG(NAND + FMCTRL1, FMCTRL1_FLUSHFIFOS);
}
if(nandType == NULL) {
bufferPrintf("nand: No supported NAND found\r\n");
return ERROR_ARG;
}
Geometry.DeviceID = nandType->id;
Geometry.banksTable = banksTable;
WPPulseTime = (((clock_get_frequency(FrequencyBaseBus) * (nandType->WPPulseTime + 1)) + 99999999)/100000000) - 1;
WEHighHoldTime = (((clock_get_frequency(FrequencyBaseBus) * (nandType->WEHighHoldTime + 1)) + 99999999)/100000000) - 1;
NANDSetting3 = (((clock_get_frequency(FrequencyBaseBus) * (nandType->NANDSetting3 + 1)) + 99999999)/100000000) - 1;
NANDSetting4 = (((clock_get_frequency(FrequencyBaseBus) * (nandType->NANDSetting4 + 1)) + 99999999)/100000000) - 1;
if(WPPulseTime > 7)
WPPulseTime = 7;
if(WEHighHoldTime > 7)
WEHighHoldTime = 7;
if(NANDSetting3 > 7)
NANDSetting3 = 7;
if(NANDSetting4 > 7)
NANDSetting4 = 7;
Geometry.blocksPerBank = nandType->blocksPerBank;
Geometry.banksTotal = NumValidBanks;
Geometry.sectorsPerPage = nandType->sectorsPerPage;
Geometry.userSuBlksTotal = nandType->userSuBlksTotal;
Geometry.bytesPerSpare = nandType->bytesPerSpare;
Geometry.field_2E = 4;
Geometry.field_2F = 3;
Geometry.pagesPerBlock = nandType->pagesPerBlock;
if(Geometry.sectorsPerPage > 4) {
LargePages = TRUE;
} else {
LargePages = FALSE;
}
if(nandType->ecc1 == 6) {
ECCType = 4;
TotalECCDataSize = Geometry.sectorsPerPage * 15;
} else if(nandType->ecc1 == 8) {
ECCType = 8;
TotalECCDataSize = Geometry.sectorsPerPage * 20;
} else if(nandType->ecc1 == 4) {
ECCType = 0;
TotalECCDataSize = Geometry.sectorsPerPage * 10;
}
if(nandType->ecc2 == 6) {
ECCType2 = 4;
} else if(nandType->ecc2 == 8) {
ECCType2 = 8;
} else if(nandType->ecc2 == 4) {
ECCType2 = 0;
}
Geometry.field_4 = 5;
Geometry.bytesPerPage = SECTOR_SIZE * Geometry.sectorsPerPage;
Geometry.pagesPerBank = Geometry.pagesPerBlock * Geometry.blocksPerBank;
Geometry.pagesTotal = Geometry.pagesPerBank * Geometry.banksTotal;
Geometry.pagesPerSuBlk = Geometry.pagesPerBlock * Geometry.banksTotal;
Geometry.userPagesTotal = Geometry.userSuBlksTotal * Geometry.pagesPerSuBlk;
Geometry.suBlksTotal = (Geometry.banksTotal * Geometry.blocksPerBank) / Geometry.banksTotal;
FTLData.field_2 = Geometry.suBlksTotal - Geometry.userSuBlksTotal - 28;
FTLData.sysSuBlks = FTLData.field_2 + 4;
FTLData.field_4 = FTLData.field_2 + 5;
FTLData.field_6 = 3;
FTLData.field_8 = 23;
if(FTLData.field_8 == 0)
Geometry.field_22 = 0;
int bits = 0;
int i = FTLData.field_8;
while((i <<= 1) != 0) {
bits++;
}
Geometry.field_22 = bits;
bufferPrintf("nand: DEVICE: %08x\r\n", Geometry.DeviceID);
bufferPrintf("nand: BANKS_TOTAL: %d\r\n", Geometry.banksTotal);
bufferPrintf("nand: BLOCKS_PER_BANK: %d\r\n", Geometry.blocksPerBank);
bufferPrintf("nand: SUBLKS_TOTAL: %d\r\n", Geometry.suBlksTotal);
bufferPrintf("nand: USER_SUBLKS_TOTAL: %d\r\n", Geometry.userSuBlksTotal);
bufferPrintf("nand: PAGES_PER_SUBLK: %d\r\n", Geometry.pagesPerSuBlk);
bufferPrintf("nand: PAGES_PER_BANK: %d\r\n", Geometry.pagesPerBank);
bufferPrintf("nand: SECTORS_PER_PAGE: %d\r\n", Geometry.sectorsPerPage);
bufferPrintf("nand: BYTES_PER_SPARE: %d\r\n", Geometry.bytesPerSpare);
bufferPrintf("nand: BYTES_PER_PAGE: %d\r\n", Geometry.bytesPerPage);
bufferPrintf("nand: PAGES_PER_BLOCK: %d\r\n", Geometry.pagesPerBlock);
aTemporaryReadEccBuf = (uint8_t*) malloc(Geometry.bytesPerPage);
memset(aTemporaryReadEccBuf, 0xFF, SECTOR_SIZE);
aTemporarySBuf = (uint8_t*) malloc(Geometry.bytesPerSpare);
HasNANDInit = TRUE;
return 0;
}
void spi_set_baud(int port, int baud, SPIWordSize wordSize, int isMaster, int isActiveLow, int lastClockEdgeMissing) {
if(port > (NUM_SPIPORTS - 1)) {
return;
}
SET_REG(SPIRegs[port].control, 0);
switch(wordSize) {
case SPIWordSize8:
spi_info[port].wordSize = 0;
break;
case SPIWordSize16:
spi_info[port].wordSize = 1;
break;
case SPIWordSize32:
spi_info[port].wordSize = 2;
break;
}
spi_info[port].isActiveLow = isActiveLow;
spi_info[port].lastClockEdgeMissing = lastClockEdgeMissing;
uint32_t clockFrequency;
if(spi_info[port].clockSource == PCLK) {
clockFrequency = clock_get_frequency(FrequencyBasePeripheral);
} else {
clockFrequency = clock_get_frequency(FrequencyBaseFixed);
}
uint32_t divider;
if(chipid_spi_clocktype() != 0) {
divider = clockFrequency / baud;
if(divider < 2)
divider = 2;
} else {
divider = clockFrequency / (baud * 2 - 1);
}
if(divider > MAX_DIVIDER) {
return;
}
SET_REG(SPIRegs[port].clkDivider, divider);
spi_info[port].baud = baud;
spi_info[port].isMaster = isMaster;
uint32_t options = (lastClockEdgeMissing << 1)
| (isActiveLow << 2)
| ((isMaster ? 0x3 : 0) << 3)
| ((spi_info[port].option5 ? 0x2 : 0x3D) << 5)
| (spi_info[port].clockSource << CLOCK_SHIFT)
| spi_info[port].wordSize << 13;
SET_REG(SPIRegs[port].setup, options);
SET_REG(SPIRegs[port].pin, 0);
SET_REG(SPIRegs[port].control, 1);
}
