void _EntryPoint(void)
{
/* ### MC9S08SC4_16 "Cpu" init code ... */
/* PE initialization code after reset */
/* Common initialization of the write once registers */
/* SOPT1: COPT=1,STOPE=0,??=0,??=0,??=0,??=0,??=0 */
setReg8(SOPT1, 0x40U);
/* SOPT2: COPCLKS=0,COPW=0,??=0,??=0,??=0,??=0,??=0,??=0 */
setReg8(SOPT2, 0x00U);
/* SPMSC1: LVWF=0,LVWACK=0,LVWIE=0,LVDRE=1,LVDSE=1,LVDE=1,??=0,BGBE=0 */
setReg8(SPMSC1, 0x1CU);
/* SPMSC2: ??=0,??=0,LVDV=0,LVWV=0,PPDF=0,PPDACK=0,??=0,PPDC=0 */
setReg8(SPMSC2, 0x00U);
/* System clock initialization */
/* ICSC1: CLKS=0,RDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
setReg8(ICSC1, 0x06U); /* Initialization of the ICS control register 1 */
/* ICSC2: BDIV=0,RANGE=0,HGO=0,LP=0,EREFS=0,ERCLKEN=0,EREFSTEN=0 */
setReg8(ICSC2, 0x00U); /* Initialization of the ICS control register 2 */
while(ICSSC_IREFST == 0U) { /* Wait until the source of reference clock is internal clock */
SRS = 0x55U; /* Reset watchdog counter write 55, AA */
SRS = 0xAAU;
}
/* ICSSC: DRST_DRS=1,DMX32=0 */
clrSetReg8Bits(ICSSC, 0xA0U, 0x40U); /* Initialization of the ICS status and control */
while((ICSSC & 0xC0U) != 0x40U) { /* Wait until the FLL switches to Mid range DCO mode */
SRS = 0x55U; /* Reset watchdog counter write 55, AA */
SRS = 0xAAU;
}
/*** End of PE initialization code after reset ***/
/*lint -save -e950 Disable MISRA rule (1.1) checking. */
__asm jmp _Startup ; /* Jump to C startup code */
/*lint -restore Enable MISRA rule (1.1) checking. */
}
/*
** ===================================================================
** Method : M_1_Enable (component PWM)
** Description :
** This method enables the component - it starts the signal
** generation. Events may be generated (<DisableEvent>
** /<EnableEvent>).
** Parameters : None
** Returns :
** --- - Error code, possible codes:
** ERR_OK - OK
** ERR_SPEED - This device does not work in
** the active speed mode
** ===================================================================
*/
byte M_1_Enable(void)
{
(void)getReg8(TPM1SC); /* Dummy read of the TPM1SC register to reset flag */
/* TPM1SC: TOF=0,TOIE=1 */
clrSetReg8Bits(TPM1SC, 0x80U, 0x40U); /* Clear Overflow interrupt flag and enable Overflow interrupt */
/* TPM1C1SC: CH1F=0,CH1IE=0,MS1B=1,MS1A=1,ELS1B=1,ELS1A=1,??=0,??=0 */
setReg8(TPM1C1SC, 0x3CU); /* Set up PWM mode with output signal level low */
return ERR_OK; /* OK */
}
extern "C" void _EntryPoint(void)
{
#ifdef debug
clrSetReg8Bits(COPCTL, 131, 68);
#else
clrSetReg8Bits(COPCTL, 131, 4);
#endif
/* ### MC9S12GC16_80 "Cpu" init code ... */
/* PE initialization code after reset */
/* Initialization of the registers INITRG, INITRM, INITEE is done to protect them to be written accidentally later by the application */
*(byte*)INITRG_ADR = 0; /* Set the register map position */
asm("nop"); /* nop instruction */
/* INITRM: RAM15=0,RAM14=0,RAM13=0,RAM12=1,RAM11=0,??=0,??=0,RAMHAL=1 */
setReg8(INITRM, 17); /* Set the RAM map position */
/* MISC: ??=0,??=0,??=0,??=0,EXSTR1=1,EXSTR0=1,ROMHM=0,ROMON=1 */
setReg8(MISC, 13);
/* PEAR: NOACCE=0,??=0,PIPOE=0,NECLK=1,LSTRE=0,RDWE=0,??=0,??=0 */
setReg8(PEAR, 16);
/* System clock initialization */
/* CLKSEL: PLLSEL=0,PSTP=0,SYSWAI=0,ROAWAI=0,PLLWAI=0,CWAI=0,RTIWAI=0,COPWAI=0 */
setReg8(CLKSEL, 0); /* Select clock source from XTAL and set bits in CLKSEL reg. */
/* PLLCTL: CME=1,PLLON=0,AUTO=1,ACQ=1,??=0,PRE=0,PCE=0,SCME=0 */
setReg8(PLLCTL, 178);//setReg8(PLLCTL, 177); /* Disable the PLL */
/* SYNR: ??=0,??=0,SYN5=0,SYN4=0,SYN3=0,SYN2=0,SYN1=0,SYN0=1 */
setReg8(SYNR, 1); /* Set the multiplier register */
/* REFDV: ??=0,??=0,??=0,??=0,REFDV3=0,REFDV2=0,REFDV1=0,REFDV0=0 */
setReg8(REFDV, 0); /* Set the divider register */
/* PLLCTL: CME=1,PLLON=1,AUTO=1,ACQ=1,??=0,PRE=0,PCE=1,SCME=0 */
/*SCME=0 mejora la estabilidad*/
setReg8(PLLCTL, 242);//setReg8(PLLCTL, 243); //PERMITO CLOCK MON, HABILITO PLL, SINCRONIZO PLL AUTO, ?????, Y HABILITO SELF CLOCK;
while(!CRGFLG_LOCK) { /* Wait until the PLL is within the desired tolerance of the target frequency */
}
/* CLKSEL: PLLSEL=1 */
setReg8Bits(CLKSEL, 128); /* Select clock source from PLL */
/*** End of PE initialization code after reset ***/
__asm("jmp _Startup"); /* Jump to C startup code */
}
void _EntryPoint(void)
{
/* ### MC9S08PA16_32 "Cpu" init code ... */
/* PE initialization code after reset */
/* WDOG_CNT: CNT=0xC520 */
setReg16(WDOG_CNT, 0xC520U); /* First part of the WDG unlock sequence */
/* WDOG_CNT: CNT=0xD928 */
setReg16(WDOG_CNT, 0xD928U); /* Second part of the WDG unlock sequence */
/* Initialization of Init_WDOG */
/* WDOG_CS1: EN=1,INT=0,UPDATE=1,TST=0,DBG=0,WAIT=1,STOP=1 */
setReg8(WDOG_CS1, 0xA3U);
/* WDOG_CS2: WIN=0,FLG=0,??=0,PRES=1,??=0,??=0,CLK=0 */
setReg8(WDOG_CS2, 0x10U);
/* WDOG_TOVAL: TOVAL=0xF800 */
setReg16(WDOG_TOVAL, 0xF800U);
/* Common initialization of the write once registers */
/* SYS_SOPT1: SCI0PS=0,BKGDPE=1,RSTPE=1,FWAKE=0,STOPE=0 */
clrSetReg8Bits(SYS_SOPT1, 0x83U, 0x0CU);
/* PMC_SPMSC1: LVWIE=0,LVDRE=1,LVDSE=1,LVDE=1,BGBDS=0,BGBE=0 */
clrSetReg8Bits(PMC_SPMSC1, 0x23U, 0x1CU);
/* PMC_SPMSC2: LVDV=0,LVWV=0 */
clrReg8Bits(PMC_SPMSC2, 0x70U);
/* System clock initialization */
/*lint -save -e923 Disable MISRA rule (11.3) checking. */
if (*(uint8_t*)0xFF6FU != 0xFFU) { /* Test if the device trim value is stored on the specified address */
ICS_C3 = *(uint8_t*)0xFF6FU; /* Initialize ICS_C3 register from a non volatile memory */
ICS_C4 = (uint8_t)((*(uint8_t*)0xFF6EU) & (uint8_t)0x01U); /* Initialize ICS_C4 register from a non volatile memory */
}
/*lint -restore Enable MISRA rule (11.3) checking. */
/* ICS_C1: CLKS=0,RDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
setReg8(ICS_C1, 0x06U); /* Initialization of the ICS control register 1 */
/* ICS_C2: BDIV=1,LP=0,??=0,??=0,??=0,??=0 */
setReg8(ICS_C2, 0x20U); /* Initialization of the ICS control register 2 */
/* ICS_C4: LOLIE=0,CME=0 */
clrReg8Bits(ICS_C4, 0xA0U);
/*** End of PE initialization code after reset ***/
/*lint -save -e950 Disable MISRA rule (1.1) checking. */
__asm jmp _Startup ; /* Jump to C startup code */
/*lint -restore Enable MISRA rule (1.1) checking. */
}
/*
** ===================================================================
** Method : M_1_Init (component PWM)
**
** Description :
** Initializes the associated peripheral(s) and the components
** internal variables. The method is called automatically as a
** part of the application initialization code.
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
void M_1_Init(void)
{
/* TPM1SC: TOF=0,TOIE=0,CPWMS=0,CLKSB=0,CLKSA=0,PS2=0,PS1=0,PS0=0 */
setReg8(TPM1SC, 0x00U); /* Disable device */
/* TPM1C1SC: CH1F=0,CH1IE=0,MS1B=1,MS1A=1,ELS1B=1,ELS1A=1,??=0,??=0 */
setReg8(TPM1C1SC, 0x3CU); /* Set up PWM mode with output signal level low */
ActualRatio.Value = 0xFFFFU; /* Store initial value of the ratio */
/* TPM1MOD: BIT15=1,BIT14=1,BIT13=1,BIT12=1,BIT11=0,BIT10=1,BIT9=0,BIT8=1,BIT7=1,BIT6=1,BIT5=0,BIT4=0,BIT3=0,BIT2=0,BIT1=1,BIT0=0 */
setReg16(TPM1MOD, 0xF5C2U); /* Set modulo register */
SetRatio(); /* Calculate and set up new values of the compare according to the selected speed CPU mode */
(void)getReg8(TPM1SC); /* Dummy read of the TPM1SC register to reset flag */
/* TPM1SC: TOF=0,TOIE=1 */
clrSetReg8Bits(TPM1SC, 0x80U, 0x40U); /* Clear Overflow interrupt flag and enable Overflow interrupt */
}
void __initialize_hardware(void)
{
/*** !!! Here you can place your own code using property "User code before PE initialization" on the build options tab of the CPU component. !!! ***/
/* ### MCF51QE128_64 "Cpu" init code ... */
/* PE initialization code after reset */
/* Common initialization of the write once registers */
/* SOPT1: COPE=0,COPT=1,STOPE=0,WAITE=1,??=0,RSTOPE=0,BKGDPE=1,RSTPE=1 */
setReg8(SOPT1, 0x53U);
/* SPMSC1: LVDF=0,LVDACK=0,LVDIE=0,LVDRE=1,LVDSE=1,LVDE=0,??=0,BGBE=0 */
setReg8(SPMSC1, 0x18U);
/* SPMSC2: LPR=0,LPRS=0,LPWUI=0,??=0,PPDF=0,PPDACK=0,PPDE=1,PPDC=0 */
setReg8(SPMSC2, 0x02U);
/* SPMSC3: LVDV=0,LVWV=0,LVWIE=0 */
clrReg8Bits(SPMSC3, 0x38U);
/* Initialization of CPU registers */
/*lint -save -e950 Disable MISRA rule (1.1) checking. */
asm {
/* VBR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,ADDRESS=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
clr.l d0
movec d0,VBR
/* CPUCR: ARD=0,IRD=0,IAE=0,IME=0,BWD=0,??=0,FSD=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
clr.l d0
movec d0,CPUCR
}
/*lint -restore Enable MISRA rule (1.1) checking. */
/* System clock initialization */
/*lint -save -e923 Disable MISRA rule (11.3) checking. */
if (*(unsigned char*)0x03FFU != 0xFFU) { /* Test if the device trim value is stored on the specified address */
ICSTRM = *(unsigned char*)0x03FFU; /* Initialize ICSTRM register from a non volatile memory */
ICSSC = (unsigned char)((*(unsigned char*)0x03FEU) & (unsigned char)0x01U); /* Initialize ICSSC register from a non volatile memory */
}
/*lint -restore Enable MISRA rule (11.3) checking. */
/* ICSC1: CLKS=0,RDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
setReg8(ICSC1, 0x06U); /* Initialization of the ICS control register 1 */
/* ICSC2: BDIV=0,RANGE=0,HGO=0,LP=0,EREFS=0,ERCLKEN=0,EREFSTEN=0 */
setReg8(ICSC2, 0x00U); /* Initialization of the ICS control register 2 */
while(ICSSC_IREFST == 0U) { /* Wait until the source of reference clock is internal clock */
}
/* ICSSC: DRST_DRS=2,DMX32=0 */
clrSetReg8Bits(ICSSC, 0x60U, 0x80U); /* Initialization of the ICS status and control */
while((ICSSC & 0xC0U) != 0x80U) { /* Wait until the FLL switches to High range DCO mode */
}
/*** End of PE initialization code after reset ***/
/*** !!! Here you can place your own code using property "User code after PE initialization" on the build options tab of the CPU component. !!! ***/
}
/*
** ===================================================================
** Method : PE_low_level_init (component MC9S08JM60_64)
**
** Description :
** Initializes components and provides common register
** initialization. The method is called automatically as a part
** of the application initialization code.
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
void PE_low_level_init(void)
{
/* Common initialization of the CPU registers */
/* PTGD: PTGD1=0,PTGD0=1 */
clrSetReg8Bits(PTGD, 0x02U, 0x01U);
/* PTGPE: PTGPE1=0,PTGPE0=0 */
clrReg8Bits(PTGPE, 0x03U);
/* PTGDD: PTGDD1=1,PTGDD0=1 */
setReg8Bits(PTGDD, 0x03U);
/* PTASE: PTASE5=0,PTASE4=0,PTASE3=0,PTASE2=0,PTASE1=0,PTASE0=0 */
clrReg8Bits(PTASE, 0x3FU);
/* PTBSE: PTBSE7=0,PTBSE6=0,PTBSE5=0,PTBSE4=0,PTBSE3=0,PTBSE2=0,PTBSE1=0,PTBSE0=0 */
setReg8(PTBSE, 0x00U);
/* PTCSE: PTCSE6=0,PTCSE5=0,PTCSE4=0,PTCSE3=0,PTCSE2=0,PTCSE1=0,PTCSE0=0 */
clrReg8Bits(PTCSE, 0x7FU);
/* PTDSE: PTDSE7=0,PTDSE6=0,PTDSE5=0,PTDSE4=0,PTDSE3=0,PTDSE2=0,PTDSE1=0,PTDSE0=0 */
setReg8(PTDSE, 0x00U);
/* PTESE: PTESE7=0,PTESE6=0,PTESE5=0,PTESE4=0,PTESE3=0,PTESE2=0,PTESE1=0,PTESE0=0 */
setReg8(PTESE, 0x00U);
/* PTFSE: PTFSE7=0,PTFSE6=0,PTFSE5=0,PTFSE4=0,PTFSE3=0,PTFSE2=0,PTFSE1=0,PTFSE0=0 */
setReg8(PTFSE, 0x00U);
/* PTGSE: PTGSE5=0,PTGSE4=0,PTGSE3=0,PTGSE2=0,PTGSE1=0,PTGSE0=0 */
clrReg8Bits(PTGSE, 0x3FU);
/* PTADS: ??=0,??=0,PTADS5=1,PTADS4=1,PTADS3=1,PTADS2=1,PTADS1=1,PTADS0=1 */
setReg8(PTADS, 0x3FU);
/* PTBDS: PTBDS7=1,PTBDS6=1,PTBDS5=1,PTBDS4=1,PTBDS3=1,PTBDS2=1,PTBDS1=1,PTBDS0=1 */
setReg8(PTBDS, 0xFFU);
/* PTCDS: ??=0,PTCDS6=1,PTCDS5=1,PTCDS4=1,PTCDS3=1,PTCDS2=1,PTCDS1=1,PTCDS0=1 */
setReg8(PTCDS, 0x7FU);
/* PTDDS: PTDDS7=1,PTDDS6=1,PTDDS5=1,PTDDS4=1,PTDDS3=1,PTDDS2=1,PTDDS1=1,PTDDS0=1 */
setReg8(PTDDS, 0xFFU);
/* PTEDS: PTEDS7=1,PTEDS6=1,PTEDS5=1,PTEDS4=1,PTEDS3=1,PTEDS2=1,PTEDS1=1,PTEDS0=1 */
setReg8(PTEDS, 0xFFU);
/* PTFDS: PTFDS7=1,PTFDS6=1,PTFDS5=1,PTFDS4=1,PTFDS3=1,PTFDS2=1,PTFDS1=1,PTFDS0=1 */
setReg8(PTFDS, 0xFFU);
/* PTGDS: ??=0,??=0,PTGDS5=1,PTGDS4=1,PTGDS3=1,PTGDS2=1,PTGDS1=1,PTGDS0=1 */
setReg8(PTGDS, 0x3FU);
/* ### Shared modules init code ... */
/* ### BitIO "powerLED" init code ... */
Shadow_PTG &= 0xFDU; /* Initialize pin shadow variable bit */
/* ### BitIO "statusLED" init code ... */
Shadow_PTG |= (byte)0x01U; /* Initialize pin shadow variable bit */
/* ### TimerInt "sampleTimer" init code ... */
sampleTimer_Init();
__EI(); /* Enable interrupts */
}
/*
** ===================================================================
** Method : PE_low_level_init (component MC9S08SC4_16)
**
** Description :
** Initializes components and provides common register
** initialization. The method is called automatically as a part
** of the application initialization code.
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
void PE_low_level_init(void)
{
#ifdef PEX_RTOS_INIT
PEX_RTOS_INIT(); /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */
#endif
/* Common initialization of the CPU registers */
/* PTBD: PTBD7=0,PTBD6=0,PTBD5=0,PTBD4=0 */
clrReg8Bits(PTBD, 0xF0U);
/* PTBPE: PTBPE7=0,PTBPE6=0,PTBPE5=0,PTBPE4=0,PTBPE3=0,PTBPE2=0,PTBPE1=0,PTBPE0=0 */
setReg8(PTBPE, 0x00U);
/* PTBDD: PTBDD7=1,PTBDD6=1,PTBDD5=1,PTBDD4=1,PTBDD3=0,PTBDD2=0,PTBDD1=0,PTBDD0=0 */
setReg8(PTBDD, 0xF0U);
/* PTAD: PTAD3=0 */
clrReg8Bits(PTAD, 0x08U);
/* PTAPE: PTAPE3=0,PTAPE1=0 */
clrReg8Bits(PTAPE, 0x0AU);
/* PTADD: PTADD3=1,PTADD1=0 */
clrSetReg8Bits(PTADD, 0x02U, 0x08U);
/* PTASE: PTASE3=0,PTASE2=0,PTASE1=0,PTASE0=0 */
clrReg8Bits(PTASE, 0x0FU);
/* PTBSE: PTBSE7=0,PTBSE6=0,PTBSE5=0,PTBSE4=0,PTBSE3=0,PTBSE2=0,PTBSE1=0,PTBSE0=0 */
setReg8(PTBSE, 0x00U);
/* PTADS: ??=0,??=0,??=0,??=0,PTADS3=0,PTADS2=1,PTADS1=1,PTADS0=1 */
setReg8(PTADS, 0x07U);
/* PTBDS: PTBDS7=0,PTBDS6=0,PTBDS5=0,PTBDS4=0,PTBDS3=0,PTBDS2=0,PTBDS1=0,PTBDS0=0 */
setReg8(PTBDS, 0x00U);
/* ### Shared modules init code ... */
/* ### BitsIO "Signal_In" init code ... */
/* ### BitsIO "Lever_Pos_MPND" init code ... */
/* ### BitIO "Lever_Pos_R" init code ... */
/* ### BitIO "AD1" init code ... */
/* ### Timer capture encapsulation "PWM_In" init code ... */
PWM_In_Init();
/* ### TimerInt "PWM_Timer" init code ... */
PWM_Timer_Init();
/* ### WatchDog "WDT" init code ... */
/* SRS: POR=0,PIN=1,COP=0,ILOP=1,ILAD=0,??=1,LVD=0,??=1 */
setReg8(SRS, 0x55U);
/* SRS: POR=1,PIN=0,COP=1,ILOP=0,ILAD=1,??=0,LVD=1,??=0 */
setReg8(SRS, 0xAAU);
CCR_lock = (byte)0;
__EI(); /* Enable interrupts */
/* TPM2SC: TOIE=0 */
clrReg8Bits(TPM2SC, 0x40U); /* Disable overflow interrupt */
}
/*
** ===================================================================
** Method : PE_low_level_init (component MCF51AC256A_80)
**
** Description :
** Initializes components and provides common register
** initialization. The method is called automatically as a part
** of the application initialization code.
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
void PE_low_level_init(void)
{
/* SCGC1: TPM3=1,FTM2=1,FTM1=1,ADC=1,CAN=1,IIC=1,SCI2=1,SCI1=1 */
setReg8(SCGC1, 0xFFU);
/* SCGC2: CRC=1,FLS=1,IRQ=1,KBI=1,ACMP=1,RTI=1,SPI2=1,SPI1=1 */
setReg8(SCGC2, 0xFFU);
/* Common initialization of the CPU registers */
/* PTGPE: PTGPE4=0,PTGPE3=0,PTGPE2=0,PTGPE1=0,PTGPE0=0 */
clrReg8Bits(PTGPE, 0x1FU);
/* PTDPE: PTDPE7=0,PTDPE3=0,PTDPE2=0 */
clrReg8Bits(PTDPE, 0x8CU);
/* PTGDD: PTGDD4=0,PTGDD3=0,PTGDD2=0,PTGDD1=0,PTGDD0=0 */
clrReg8Bits(PTGDD, 0x1FU);
/* PTDDD: PTDDD7=0,PTDDD3=0,PTDDD2=0 */
clrReg8Bits(PTDDD, 0x8CU);
/* PTCDD: PTCDD5=0,PTCDD3=1 */
clrSetReg8Bits(PTCDD, 0x20U, 0x08U);
/* PTCD: PTCD3=1 */
setReg8Bits(PTCD, 0x08U);
/* PTHD: PTHD1=0 */
clrReg8Bits(PTHD, 0x02U);
/* PTHPE: PTHPE1=0 */
clrReg8Bits(PTHPE, 0x02U);
/* PTHDD: PTHDD1=1 */
setReg8Bits(PTHDD, 0x02U);
/* PTASE: PTASE7=0,PTASE6=0,PTASE5=0,PTASE4=0,PTASE3=0,PTASE2=0,PTASE1=0,PTASE0=0 */
setReg8(PTASE, 0x00U);
/* PTBSE: PTBSE7=0,PTBSE6=0,PTBSE5=0,PTBSE4=0,PTBSE3=0,PTBSE2=0,PTBSE1=0,PTBSE0=0 */
setReg8(PTBSE, 0x00U);
/* PTCSE: PTCSE6=0,PTCSE5=0,PTCSE4=0,PTCSE3=0,PTCSE2=0,PTCSE1=0,PTCSE0=0 */
clrReg8Bits(PTCSE, 0x7FU);
/* PTDSE: PTDSE7=0,PTDSE6=0,PTDSE5=0,PTDSE4=0,PTDSE3=0,PTDSE2=0,PTDSE1=0,PTDSE0=0 */
setReg8(PTDSE, 0x00U);
/* PTESE: PTESE7=0,PTESE6=0,PTESE5=0,PTESE4=0,PTESE3=0,PTESE2=0,PTESE1=0,PTESE0=0 */
setReg8(PTESE, 0x00U);
/* PTFSE: PTFSE7=0,PTFSE6=0,PTFSE5=0,PTFSE4=0,PTFSE3=0,PTFSE2=0,PTFSE1=0,PTFSE0=0 */
setReg8(PTFSE, 0x00U);
/* PTGSE: PTGSE6=0,PTGSE5=0,PTGSE4=0,PTGSE3=0,PTGSE2=0,PTGSE1=0,PTGSE0=0 */
clrReg8Bits(PTGSE, 0x7FU);
/* PTHSE: PTHSE6=0,PTHSE5=0,PTHSE4=0,PTHSE3=0,PTHSE2=0,PTHSE1=0,PTHSE0=0 */
clrReg8Bits(PTHSE, 0x7FU);
/* PTJSE: PTJSE7=0,PTJSE6=0,PTJSE5=0,PTJSE4=0,PTJSE3=0,PTJSE2=0,PTJSE1=0,PTJSE0=0 */
setReg8(PTJSE, 0x00U);
/* PTADS: PTADS7=1,PTADS6=1,PTADS5=1,PTADS4=1,PTADS3=1,PTADS2=1,PTADS1=1,PTADS0=1 */
setReg8(PTADS, 0xFFU);
/* PTBDS: PTBDS7=1,PTBDS6=1,PTBDS5=1,PTBDS4=1,PTBDS3=1,PTBDS2=1,PTBDS1=1,PTBDS0=1 */
setReg8(PTBDS, 0xFFU);
/* PTCDS: ??=0,PTCDS6=1,PTCDS5=1,PTCDS4=1,PTCDS3=1,PTCDS2=1,PTCDS1=1,PTCDS0=1 */
setReg8(PTCDS, 0x7FU);
/* PTDDS: PTDDS7=1,PTDDS6=1,PTDDS5=1,PTDDS4=1,PTDDS3=1,PTDDS2=1,PTDDS1=1,PTDDS0=1 */
setReg8(PTDDS, 0xFFU);
/* PTEDS: PTEDS7=1,PTEDS6=1,PTEDS5=1,PTEDS4=1,PTEDS3=1,PTEDS2=1,PTEDS1=1,PTEDS0=1 */
setReg8(PTEDS, 0xFFU);
/* PTFDS: PTFDS7=1,PTFDS6=1,PTFDS5=1,PTFDS4=1,PTFDS3=1,PTFDS2=1,PTFDS1=1,PTFDS0=1 */
setReg8(PTFDS, 0xFFU);
/* PTGDS: ??=0,PTGDS6=1,PTGDS5=1,PTGDS4=1,PTGDS3=1,PTGDS2=1,PTGDS1=1,PTGDS0=1 */
setReg8(PTGDS, 0x7FU);
/* PTHDS: ??=0,PTHDS6=1,PTHDS5=1,PTHDS4=1,PTHDS3=1,PTHDS2=1,PTHDS1=1,PTHDS0=1 */
setReg8(PTHDS, 0x7FU);
/* PTJDS: PTJDS7=1,PTJDS6=1,PTJDS5=1,PTJDS4=1,PTJDS3=1,PTJDS2=1,PTJDS1=1,PTJDS0=1 */
setReg8(PTJDS, 0xFFU);
/* ### Shared modules init code ... */
KB1_Init();
/* ### Free running 8-bit counter "FC321" init code ... */
FC321_Init();
/* ### Asynchro serial "AS2" init code ... */
AS2_Init();
/* ### BitIO "Bit1" init code ... */
/* INTC_WCR: ENB=1,??=0,??=0,??=0,??=0,MASK=0 */
setReg8(INTC_WCR, 0x80U);
SR_lock = 0x00;
/* Set initial interrupt priority 0 */
asm {
move.w SR,D0;
andi.l #0xF8FF,D0;
move.w D0,SR;
}
}
/*
** ===================================================================
** Method : PE_low_level_init (bean MC9S12GC16_80)
**
** Description :
** Initializes beans and provides common register initialization.
** The method is called automatically as a part of the
** application initialization code.
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
void PE_low_level_init(void)
{
/* Int. priority initialization */
/* HPRIO: PSEL7=1,PSEL6=1,PSEL5=0,PSEL4=1,PSEL3=0,PSEL2=0,PSEL1=1,??=0 */
setReg8(HPRIO, 210); /* Set the highest interrupt priority to the ivVatd0 interrupt
/* Common initialization of the CPU registers */
/* PORTA: BIT7=0,BIT6=0,BIT5=0,BIT4=0,BIT3=0,BIT2=0,BIT1=0,BIT0=0 */
setReg8(PORTA, 0);
/* PUCR: PUPEE=0,PUPAE=0 */
clrReg8Bits(PUCR, 1);
/* DDRA: BIT7=1,BIT6=1,BIT5=1,BIT4=1,BIT3=1,BIT2=1,BIT1=1,BIT0=1 */
setReg8(DDRA, 255);
/* PORTB: BIT7=0,BIT6=0,BIT5=0,BIT4=0,BIT3=0,BIT2=0,BIT1=0,BIT0=0 */
setReg8(PORTB, 0);
/* DDRB: BIT7=1,BIT6=1,BIT5=1,BIT4=1,BIT3=1,BIT2=1,BIT1=1,BIT0=1 */
setReg8(DDRB, 255);
/* PTM: PTM5=0,PTM4=0,PTM3=0,PTM2=0,PTM1=0,PTM0=0 */
clrReg8Bits(PTM, 63);
/* DDRM: DDRM5=1,DDRM4=1,DDRM3=1,DDRM2=1,DDRM1=1,DDRM0=1 */
setReg8Bits(DDRM, 63);
/* PIEJ: PIEJ7=0,PIEJ6=0 */
clrReg8Bits(PIEJ, 192);
/* PTJ: PTJ7=0,PTJ6=0 */
clrReg8Bits(PTJ, 192);
/* PERJ: PERJ7=0,PERJ6=0 */
clrReg8Bits(PERJ, 192);
/* DDRJ: DDRJ7=1,DDRJ6=1 */
setReg8Bits(DDRJ, 192);
/* PTS: PTS2=0 */
clrReg8Bits(PTS, 4);
/* WOMS: WOMS2=0 */
clrReg8Bits(WOMS, 4);
/* DDRS: DDRS2=1 */
setReg8Bits(DDRS, 4);
/* PIEP: PIEP4=0,PIEP3=0,PIEP2=0,PIEP1=0,PIEP0=0 */
clrReg8Bits(PIEP, 31);
/* PTP: PTP4=0,PTP3=0,PTP2=0,PTP1=0,PTP0=0 */
clrReg8Bits(PTP, 31);
/* PERP: PERP4=0,PERP3=0,PERP2=0,PERP1=0,PERP0=0 */
clrReg8Bits(PERP, 31);
/* DDRP: DDRP4=1,DDRP3=1,DDRP2=1,DDRP1=1,DDRP0=1 */
setReg8Bits(DDRP, 31);
/* PEAR: RDWE=0 */
clrReg8Bits(PEAR, 4);
/* DDRE: BIT2=0 */
clrReg8Bits(DDRE, 4);
/* COPCTL: WCOP=0,RSBCK=1,CR2=1,CR1=1,CR0=1 */
clrSetReg8Bits(COPCTL, 128, 71);
/* TSCR1: TEN=0,TSWAI=1,TSFRZ=1,TFFCA=0 */
clrSetReg8Bits(TSCR1, 144, 96);
/* OC7M: OC7M3=0 */
clrReg8Bits(OC7M, OC7M_OC7M3_MASK);
/* TCTL1: OM7=0,OL7=0,OM6=0,OL6=0,OM5=0,OL5=0,OM4=0,OL4=0 */
setReg8(TCTL1, 0);
/* TCTL2: OM3=0,OL3=0,OM2=0,OL2=0,OM1=0,OL1=0,OM0=0,OL0=0 */
setReg8(TCTL2, 0);
/* TIE: C7I=1,C6I=0,C5I=0,C4I=0,C3I=0,C2I=0,C1I=0,C0I=0 */
setReg8(TIE, 0);
/* TIOS: IOS7=1,IOS6=1,IOS5=1,IOS4=1,IOS3=1,IOS2=1,IOS1=1,IOS0=1 */
setReg8(TIOS, 255);
/* TTOV: TOV7=0,TOV6=0,TOV5=0,TOV4=0,TOV3=0,TOV2=0,TOV1=0,TOV0=0 */
setReg8(TTOV, 0);
/* TSCR2: TCRE=0,PR2=1,PR1=0,PR0=1 */
clrSetReg8Bits(TSCR2, 10, 5);
/* TFLG1: C7F=1,C6F=1,C5F=1,C4F=1,C3F=1,C2F=1,C1F=1,C0F=1 */
setReg8(TFLG1, 255);
/* PTT: PTT7=0,PTT6=0,PTT5=0,PTT4=0,PTT3=0,PTT2=0,PTT1=0,PTT0=0 */
clrReg8Bits(PTT, 255);
/* DDRT: DDRT7=1,DDRT6=1,DDRT5=1,DDRT4=1,DDRT3=1,DDRT2=1,DDRT1=1,DDRT0=1 */
setReg8Bits(DDRT, 255);
/* ATDDIEN: IEN1=1,IEN0=1 */
setReg8Bits(ATDDIEN, 3);
/* PTAD: PTAD1=0,PTAD0=0 */
clrReg8Bits(PTAD, 3);
/* PERAD: PERAD1=0,PERAD0=0 */
clrReg8Bits(PERAD, 3);
/* DDRAD: DDRAD1=1,DDRAD0=1 */
setReg8Bits(DDRAD, 3);
/* PWMCTL: PSWAI=0,PFRZ=0 */
clrReg8Bits(PWMCTL, 12);
/* PWMSDN: PWMIF=0,PWMIE=0,PWMRSTRT=0,PWMLVL=0,??=0,PWM5IN=0,PWM5INL=0,PWM5ENA=0 */
setReg8(PWMSDN, 0);
/* ### MC9S12GC16_80 "Cpu" init code ... */
/* ### ByteIO "Display1" init code ... */
/* ### BitsIO "bits5ULN" init code ... */
/* ### BitsIO "bits2ULN" init code ... */
/* ### BitIO "trx" init code ... */
/* ### BitsIO "PTSL" init code ... */
/* ### BitIO "PWSN" init code ... */
/* ### InputPin "PUL" init code ... */
/* ### WatchDog "WDog1" init code ... */
/* ### Asynchro serial "AS1" init code ... */
TI1_Init();
/* Common peripheral initialization - ENABLE */
/* TSCR1: TEN=1 */
setReg8Bits(TSCR1, 192);
__EI(); /* Enable interrupts */
}
/*
** ===================================================================
** Method : PE_low_level_init (component MCF51QE128_64)
**
** Description :
** Initializes components and provides common register
** initialization. The method is called automatically as a part
** of the application initialization code.
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
void PE_low_level_init(void)
{
/* SCGC1: TPM3=1,TPM2=1,TPM1=1,ADC=1,IIC2=1,IIC1=1,SCI2=1,SCI1=1 */
setReg8(SCGC1, 0xFFU);
/* SCGC2: ??=1,FLS=1,IRQ=1,KBI=1,ACMP=1,RTC=1,SPI2=1,SPI1=1 */
setReg8(SCGC2, 0xFFU);
/* Common initialization of the CPU registers */
/* PTCD: PTCD3=0,PTCD2=1,PTCD1=0,PTCD0=1 */
clrSetReg8Bits(PTCD, 0x0AU, 0x05U);
/* PTCDD: PTCDD3=1,PTCDD2=1,PTCDD1=1,PTCDD0=1 */
setReg8Bits(PTCDD, 0x0FU);
/* PTCPE: PTCPE3=1,PTCPE1=1 */
setReg8Bits(PTCPE, 0x0AU);
/* PTBDD: PTBDD1=1,PTBDD0=0 */
clrSetReg8Bits(PTBDD, 0x01U, 0x02U);
/* PTBD: PTBD1=1 */
setReg8Bits(PTBD, 0x02U);
/* PTAPE: PTAPE3=0,PTAPE2=0 */
clrReg8Bits(PTAPE, 0x0CU);
/* PTADD: PTADD3=0,PTADD2=0 */
clrReg8Bits(PTADD, 0x0CU);
/* PTASE: PTASE7=0,PTASE6=0,PTASE4=0,PTASE3=0,PTASE2=0,PTASE1=0,PTASE0=0 */
clrReg8Bits(PTASE, 0xDFU);
/* PTBSE: PTBSE7=0,PTBSE6=0,PTBSE5=0,PTBSE4=0,PTBSE3=0,PTBSE2=0,PTBSE1=0,PTBSE0=0 */
setReg8(PTBSE, 0x00U);
/* PTCSE: PTCSE7=0,PTCSE6=0,PTCSE5=0,PTCSE4=0,PTCSE3=0,PTCSE2=0,PTCSE1=0,PTCSE0=0 */
setReg8(PTCSE, 0x00U);
/* PTDSE: PTDSE7=0,PTDSE6=0,PTDSE5=0,PTDSE4=0,PTDSE3=0,PTDSE2=0,PTDSE1=0,PTDSE0=0 */
setReg8(PTDSE, 0x00U);
/* PTESE: PTESE7=0,PTESE6=0,PTESE5=0,PTESE4=0,PTESE3=0,PTESE2=0,PTESE1=0,PTESE0=0 */
setReg8(PTESE, 0x00U);
/* PTFSE: PTFSE7=0,PTFSE6=0,PTFSE5=0,PTFSE4=0,PTFSE3=0,PTFSE2=0,PTFSE1=0,PTFSE0=0 */
setReg8(PTFSE, 0x00U);
/* PTGSE: PTGSE3=0,PTGSE2=0,PTGSE1=0,PTGSE0=0 */
clrReg8Bits(PTGSE, 0x0FU);
/* PTHSE: PTHSE7=0,PTHSE6=0,PTHSE1=0,PTHSE0=0 */
clrReg8Bits(PTHSE, 0xC3U);
/* PTADS: PTADS7=1,PTADS6=1,PTADS5=0,PTADS4=1,PTADS3=1,PTADS2=1,PTADS1=1,PTADS0=1 */
setReg8(PTADS, 0xDFU);
/* PTBDS: PTBDS7=1,PTBDS6=1,PTBDS5=1,PTBDS4=1,PTBDS3=1,PTBDS2=1,PTBDS1=1,PTBDS0=1 */
setReg8(PTBDS, 0xFFU);
/* PTCDS: PTCDS7=1,PTCDS6=1,PTCDS5=1,PTCDS4=1,PTCDS3=1,PTCDS2=1,PTCDS1=1,PTCDS0=1 */
setReg8(PTCDS, 0xFFU);
/* PTDDS: PTDDS7=1,PTDDS6=1,PTDDS5=1,PTDDS4=1,PTDDS3=1,PTDDS2=1,PTDDS1=1,PTDDS0=1 */
setReg8(PTDDS, 0xFFU);
/* PTEDS: PTEDS7=1,PTEDS6=1,PTEDS5=1,PTEDS4=1,PTEDS3=1,PTEDS2=1,PTEDS1=1,PTEDS0=1 */
setReg8(PTEDS, 0xFFU);
/* PTFDS: PTFDS7=1,PTFDS6=1,PTFDS5=1,PTFDS4=1,PTFDS3=1,PTFDS2=1,PTFDS1=1,PTFDS0=1 */
setReg8(PTFDS, 0xFFU);
/* PTGDS: PTGDS7=0,PTGDS6=0,PTGDS5=0,PTGDS4=0,PTGDS3=1,PTGDS2=1,PTGDS1=1,PTGDS0=1 */
setReg8(PTGDS, 0x0FU);
/* PTHDS: PTHDS7=1,PTHDS6=1,PTHDS5=0,PTHDS4=0,PTHDS3=0,PTHDS2=0,PTHDS1=1,PTHDS0=1 */
setReg8(PTHDS, 0xC3U);
/* PTGDD: PTGDD7=1,PTGDD6=1,PTGDD5=1,PTGDD4=1 */
setReg8Bits(PTGDD, 0xF0U);
/* PTHDD: PTHDD5=1,PTHDD4=1,PTHDD3=1,PTHDD2=1 */
setReg8Bits(PTHDD, 0x3CU);
/* PTJDD: PTJDD7=1,PTJDD6=1,PTJDD5=1,PTJDD4=1,PTJDD3=1,PTJDD2=1,PTJDD1=1,PTJDD0=1 */
setReg8(PTJDD, 0xFFU);
/* ### Shared modules init code ... */
/* ### Programable pulse generation "MotorD1" init code ... */
MotorD1_Init();
/* ### BitIO "MotorD2" init code ... */
/* ### Programable pulse generation "MotorI1" init code ... */
MotorI1_Init();
/* ### BitIO "MotorI2" init code ... */
/* ### Asynchro serial "Terminal" init code ... */
Terminal_Init();
/* ### BitsIO "Encoders" init code ... */
/* Common peripheral initialization - ENABLE */
/* TPM3SC: CLKSB=0,CLKSA=1 */
clrSetReg8Bits(TPM3SC, 0x10U, 0x08U);
/* INTC_WCR: ENB=0,??=0,??=0,??=0,??=0,MASK=0 */
setReg8(INTC_WCR, 0x00U);
SR_lock = 0x00;
/* Set initial interrupt priority 0 */
asm {
move.w SR,D0;
andi.l #0xF8FF,D0;
move.w D0,SR;
}
}
/*
** ===================================================================
** Method : PE_low_level_init (component MC9S08PA16_32)
**
** Description :
** Initializes components and provides common register
** initialization. The method is called automatically as a part
** of the application initialization code.
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
void PE_low_level_init(void)
{
#ifdef PEX_RTOS_INIT
PEX_RTOS_INIT(); /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */
#endif
/* SCG_C1: FTM2=1,??=0,FTM0=1,??=0,??=0,??=0,MTIM0=1,RTC=1 */
setReg8(SCG_C1, 0xA3U);
/* SCG_C2: ??=0,??=0,DBG=1,NVM=1,IPC=1,CRC=1,??=0,??=0 */
setReg8(SCG_C2, 0x3CU);
/* SCG_C3: ??=0,??=0,SCI1=1,SCI0=1,??=0,SPI0=1,IIC=1,??=0 */
setReg8(SCG_C3, 0x36U);
/* SCG_C4: ACMP=1,??=0,ADC=1,??=0,IRQ=1,??=0,??=0,KBI0=1 */
setReg8(SCG_C4, 0xA9U);
/* Common initialization of the CPU registers */
/* SYS_SOPT2: TXDME=0 */
clrReg8Bits(SYS_SOPT2, 0x80U);
/* PORT_PTBOE: PTBOE1=1,PTBOE0=0 */
clrSetReg8Bits(PORT_PTBOE, 0x01U, 0x02U);
/* PORT_PTBIE: PTBIE1=0,PTBIE0=1 */
clrSetReg8Bits(PORT_PTBIE, 0x02U, 0x01U);
/* PORT_PTBD: PTBD1=1 */
setReg8Bits(PORT_PTBD, 0x02U);
/* PORT_PTCOE: PTCOE7=1,PTCOE6=0 */
clrSetReg8Bits(PORT_PTCOE, 0x40U, 0x80U);
/* PORT_PTCIE: PTCIE7=0,PTCIE6=1 */
clrSetReg8Bits(PORT_PTCIE, 0x80U, 0x40U);
/* PORT_PTCD: PTCD7=1 */
setReg8Bits(PORT_PTCD, 0x80U);
/* PORT_PTAD: PTAD0=0 */
clrReg8Bits(PORT_PTAD, 0x01U);
/* PORT_PTAPE: PTAPE0=0 */
clrReg8Bits(PORT_PTAPE, 0x01U);
/* PORT_PTAOE: PTAOE0=1 */
setReg8Bits(PORT_PTAOE, 0x01U);
/* PORT_PTAIE: PTAIE0=0 */
clrReg8Bits(PORT_PTAIE, 0x01U);
/* PORT_PTDD: PTDD0=0 */
clrReg8Bits(PORT_PTDD, 0x01U);
/* PORT_PTDPE: PTDPE0=0 */
clrReg8Bits(PORT_PTDPE, 0x01U);
/* PORT_PTDOE: PTDOE0=1 */
setReg8Bits(PORT_PTDOE, 0x01U);
/* PORT_PTDIE: PTDIE0=0 */
clrReg8Bits(PORT_PTDIE, 0x01U);
/* SYS_SOPT3: CLKOE=0,BUSREF=0 */
clrReg8Bits(SYS_SOPT3, 0x0FU);
/* IPC_ILRS9: ILRn3=0,ILRn2=0,ILRn1=0,ILRn0=0 */
setReg8(IPC_ILRS9, 0x00U);
/* IPC_ILRS8: ILRn3=0,ILRn2=0,ILRn1=0,ILRn0=0 */
setReg8(IPC_ILRS8, 0x00U);
/* IPC_ILRS7: ILRn3=0,ILRn2=0,ILRn1=0,ILRn0=2 */
setReg8(IPC_ILRS7, 0x02U);
/* IPC_ILRS6: ILRn3=2,ILRn2=2,ILRn1=2,ILRn0=2 */
setReg8(IPC_ILRS6, 0xAAU);
/* IPC_ILRS5: ILRn3=2,ILRn2=0,ILRn1=0,ILRn0=0 */
setReg8(IPC_ILRS5, 0x80U);
/* IPC_ILRS4: ILRn3=2,ILRn2=0,ILRn1=2,ILRn0=2 */
setReg8(IPC_ILRS4, 0x8AU);
/* IPC_ILRS3: ILRn3=0,ILRn2=0,ILRn1=0,ILRn0=0 */
setReg8(IPC_ILRS3, 0x00U);
/* IPC_ILRS2: ILRn3=0,ILRn2=0,ILRn1=0,ILRn0=0 */
setReg8(IPC_ILRS2, 0x00U);
/* IPC_ILRS1: ILRn3=2,ILRn2=2,ILRn1=0,ILRn0=0 */
setReg8(IPC_ILRS1, 0xA0U);
/* IPC_ILRS0: ILRn3=0,ILRn2=0,ILRn1=0,ILRn0=0 */
setReg8(IPC_ILRS0, 0x00U);
/* IPC_SC: IPCE=1,??=0,PSE=0,PSF=0,PULIPM=0,??=0,IPM=0 */
setReg8(IPC_SC, 0x80U);
/* Initialization of the PORT module */
/* ### Shared modules init code ... */
/* ### Asynchro serial "AS_CCTALK" init code ... */
AS_CCTALK_Init();
/* ### Free running 8-bit counter "FC_CCTALK" init code ... */
FC_CCTALK_Init();
/* ### TimerInt "TI_CCTALK" init code ... */
TI_CCTALK_Init();
/* ### WatchDog "WDOG" init code ... */
WDOG_Init();
/* WDOG_CNT: CNT=0xA602 */
setReg16(WDOG_CNT, 0xA602U);
/* WDOG_CNT: CNT=0xB480 */
setReg16(WDOG_CNT, 0xB480U);
/* ### Asynchro serial "AS_DATABUS" init code ... */
AS_DATABUS_Init();
/* ### BitIO "LED_RUN" init code ... */
/* ### BitIO "LED_CCTALK" init code ... */
/* ### Free running 8-bit counter "FC_DATABUS" init code ... */
FC_DATABUS_Init();
/* ### TimerInt "TI_LEDS" init code ... */
TI_LEDS_Init();
/* ### IntEEPROM "EEPROM" init code ... */
EEPROM_Init();
/* ### Free running 8-bit counter "FC_HOPPER" init code ... */
FC_HOPPER_Init();
/* Common peripheral initialization - ENABLE */
/* FTM0_SC: CLKS=1 */
clrSetReg8Bits(FTM0_SC, 0x10U, 0x08U);
/* FTM2_SC: CLKS=1 */
clrSetReg8Bits(FTM2_SC, 0x10U, 0x08U);
CCR_lock = (byte)0;
__EI(); /* Enable interrupts */
}
/*
** ===================================================================
** Method : PE_low_level_init (bean MC9S12DG128_112)
**
** Description :
** Initializes beans and provides common register initialization.
** The method is called automatically as a part of the
** application initialization code.
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
void PE_low_level_init(void)
{
/* Common initialization of the CPU registers */
/* PIEP: PIEP5=0 */
clrReg8Bits(PIEP, 32);
/* PTP: PTP5=0,PTP4=0,PTP3=0,PTP1=0 */
clrReg8Bits(PTP, 58);
/* PERP: PERP5=0 */
clrReg8Bits(PERP, 32);
/* DDRP: DDRP5=1,DDRP4=1,DDRP3=1,DDRP1=1 */
setReg8Bits(DDRP, 58);
/* PEAR: NOACCE=0,PIPOE=0,NECLK=1,LSTRE=0,RDWE=0 */
clrSetReg8Bits(PEAR, 172, 16);
/* PUCR: PUPKE=0,PUPEE=0,PUPBE=0,PUPAE=0 */
clrReg8Bits(PUCR, 147);
/* DDRE: BIT7=0,BIT6=0,BIT5=0,BIT4=0,BIT3=0,BIT2=0 */
clrReg8Bits(DDRE, 252);
/* PTM: PTM4=0,PTM3=0 */
clrReg8Bits(PTM, 24);
/* WOMM: WOMM4=0,WOMM3=0 */
clrReg8Bits(WOMM, 24);
/* DDRM: DDRM4=1,DDRM3=1 */
setReg8Bits(DDRM, 24);
/* PERM: PERM4=0 */
clrReg8Bits(PERM, 16);
/* PORTK: BIT3=0,BIT0=0 */
clrReg8Bits(PORTK, 9);
/* DDRK: BIT3=1,BIT0=1 */
setReg8Bits(DDRK, 9);
/* PTS: PTS1=1 */
setReg8Bits(PTS, 2);
/* DDRS: DDRS1=1,DDRS0=0 */
clrSetReg8Bits(DDRS, 1, 2);
/* PWME: PWME7=0,PWME6=0,PWME5=0,PWME4=0,PWME3=0,PWME2=0,PWME1=0,PWME0=0 */
setReg8(PWME, 0);
/* PWMCTL: CON45=0,CON23=1,CON01=1,PSWAI=0,PFRZ=0 */
clrSetReg8Bits(PWMCTL, 76, 48);
/* PWMCAE: CAE4=0,CAE3=0,CAE1=0 */
clrReg8Bits(PWMCAE, 26);
/* PWMPOL: PPOL4=0,PPOL3=0,PPOL1=0 */
clrReg8Bits(PWMPOL, 26);
/* PBCTL: PBEN=0 */
clrReg8Bits(PBCTL, 64);
/* TSCR1: TEN=0,TSWAI=0,TSFRZ=0,TFFCA=0 */
clrReg8Bits(TSCR1, 240);
/* DLYCT: ??=0,??=0,??=0,??=0,??=0,??=0,DLY1=0,DLY0=0 */
setReg8(DLYCT, 0);
/* ICSYS: SH37=0,SH26=0,SH15=0,SH04=0,TFMOD=0,PACMX=0,BUFEN=0,LATQ=0 */
setReg8(ICSYS, 0);
/* ICOVW: NOVW7=0,NOVW5=0,NOVW0=0 */
clrReg8Bits(ICOVW, 161);
/* TCTL4: EDG0B=1,EDG0A=1 */
setReg8Bits(TCTL4, 3);
/* TCTL3: EDG7B=0,EDG7A=0,EDG5B=0,EDG5A=0 */
clrReg8Bits(TCTL3, 204);
/* TIOS: IOS7=0,IOS5=0,IOS0=0 */
clrReg8Bits(TIOS, 161);
/* PERT: PERT7=0,PERT5=0,PERT0=0 */
clrReg8Bits(PERT, 161);
/* PORTA: BIT7=0,BIT6=0,BIT5=0,BIT4=0,BIT3=0,BIT2=0,BIT1=0,BIT0=0 */
setReg8(PORTA, 0);
/* DDRA: BIT7=1,BIT6=1,BIT5=1,BIT4=1,BIT3=1,BIT2=1,BIT1=1,BIT0=1 */
setReg8(DDRA, 255);
/* PORTB: BIT7=0,BIT6=0,BIT5=0,BIT4=0,BIT3=0,BIT2=0,BIT1=0,BIT0=0 */
setReg8(PORTB, 0);
/* DDRB: BIT7=1,BIT6=1,BIT5=1,BIT4=1,BIT3=1,BIT2=1,BIT1=1,BIT0=1 */
setReg8(DDRB, 255);
/* TIE: C7I=0,C5I=0 */
clrReg8Bits(TIE, 160);
/* PACTL: CLK1=0,CLK0=0 */
clrReg8Bits(PACTL, 12);
/* ATD0DIEN: IEN0=0 */
clrReg8Bits(ATD0DIEN, 1);
/* ATD1DIEN: IEN0=0 */
clrReg8Bits(ATD1DIEN, 1);
/* CRGINT: LOCKIE=0,SCMIE=0 */
clrReg8Bits(CRGINT, 18);
/* COPCTL: RSBCK=0 */
clrReg8Bits(COPCTL, 64);
/* RDRIV: RDPK=0,RDPE=0,RDPB=0,RDPA=0 */
clrReg8Bits(RDRIV, 147);
/* RDRH: RDRH7=0,RDRH6=0,RDRH5=0,RDRH4=0,RDRH3=0,RDRH2=0,RDRH1=0,RDRH0=0 */
setReg8(RDRH, 0);
/* RDRJ: RDRJ7=0,RDRJ6=0,RDRJ1=0,RDRJ0=0 */
clrReg8Bits(RDRJ, 195);
/* RDRM: RDRM7=0,RDRM6=0,RDRM5=0,RDRM4=0,RDRM3=0,RDRM2=0,RDRM1=0,RDRM0=0 */
setReg8(RDRM, 0);
/* RDRP: RDRP7=0,RDRP6=0,RDRP5=0,RDRP4=0,RDRP3=0,RDRP2=0,RDRP1=0,RDRP0=0 */
setReg8(RDRP, 0);
/* RDRS: RDRS7=0,RDRS6=0,RDRS5=0,RDRS4=0,RDRS3=0,RDRS2=0,RDRS1=0,RDRS0=0 */
setReg8(RDRS, 0);
/* RDRT: RDRT7=0,RDRT6=0,RDRT5=0,RDRT4=0,RDRT3=0,RDRT2=0,RDRT1=0,RDRT0=0 */
setReg8(RDRT, 0);
/* INTCR: IRQEN=0 */
clrReg8Bits(INTCR, 64);
/* PACN10: BIT15=0,BIT14=0,BIT13=0,BIT12=0,BIT11=0,BIT10=0,BIT9=0,BIT8=0,BIT7=0,BIT6=0,BIT5=0,BIT4=0,BIT3=0,BIT2=0,BIT1=0,BIT0=0 */
setReg16(PACN10, 0);
/* ### MC9S12DG128_112 "Cpu112" init code ... */
/* ### BitIO "ForwardOrBackward" init code ... */
/* ### ByteIO "E" init code ... */
/* ### BitIO "MotorEnableM3" init code ... */
/* ### BitIO "M4" init code ... */
Shadow_M &= (byte)~16; /* Initialize pin shadow variable bit */
/* ### BitIO "K0" init code ... */
Shadow_K &= (byte)~1; /* Initialize pin shadow variable bit */
/* ### BitIO "MotorEnableK3" init code ... */
/* ### Asynchro serial "SCI" init code ... */
SCI_Init();
/* ### Programable pulse generation "Servo1" init code ... */
Servo1_Init();
/* ### Programable pulse generation "Servo2" init code ... */
Servo2_Init();
/* ### Programable pulse generation "MainMotor" init code ... */
MainMotor_Init();
/* ### PulseAccumulator "SpeedSensor" init code ... */
SpeedSensor_Init();
/* ### ByteIO "PORTA" init code ... */
/* ### ByteIO "PORTB" init code ... */
/* ### Timer capture encapsulation "Cap1" init code ... */
Cap1_Init();
/* ### Timer capture encapsulation "Cap2" init code ... */
Cap2_Init();
/* ### "ATC0" init code ... */
ATC0_Init();
/* ### "ATC1" init code ... */
ATC1_Init();
/* Common peripheral initialization - ENABLE */
/* TSCR1: TEN=1 */
setReg8Bits(TSCR1, 128);
__EI(); /* Enable interrupts */
}
/*
** ===================================================================
** Method : PE_low_level_init (bean MC9S12GC16_80)
**
** Description :
** Initializes beans and provides common register initialization.
** The method is called automatically as a part of the
** application initialization code.
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
void PE_low_level_init(void)
{
/* Int. priority initialization */
/* HPRIO: PSEL7=1,PSEL6=1,PSEL5=0,PSEL4=1,PSEL3=0,PSEL2=0,PSEL1=1,??=0 */
setReg8(HPRIO, 210); /* Set the highest interrupt priority to the ivVatd0 interrupt */
/* Common initialization of the CPU registers */
/* PORTA: BIT7=0,BIT6=0,BIT5=0,BIT4=0,BIT3=0,BIT2=0,BIT1=0,BIT0=0 */
setReg8(PORTA, 0);
/* PUCR: PUPEE=0,PUPAE=0 */
clrReg8Bits(PUCR, 18);
/* DDRA: BIT7=1,BIT6=1,BIT5=1,BIT4=1,BIT3=1,BIT2=1,BIT1=1,BIT0=1 */
setReg8(DDRA, 255);
/* PORTB: BIT7=0,BIT6=0,BIT5=0,BIT4=0,BIT3=0,BIT2=0,BIT1=0,BIT0=0 */
setReg8(PORTB, 0);
/* DDRB: BIT7=1,BIT6=1,BIT5=1,BIT4=1,BIT3=1,BIT2=1,BIT1=1,BIT0=1 */
setReg8(DDRB, 255);
/* PTM: PTM5=0,PTM4=0,PTM3=0,PTM2=0,PTM1=0,PTM0=0 */
clrReg8Bits(PTM, 63);
/* WOMM: WOMM5=0,WOMM4=0,WOMM3=0,WOMM2=0,WOMM1=0,WOMM0=0 */
clrReg8Bits(WOMM, 63);
/* DDRM: DDRM5=1,DDRM4=1,DDRM3=1,DDRM2=1,DDRM1=1,DDRM0=1 */
setReg8Bits(DDRM, 63);
/* PIEJ: PIEJ7=0,PIEJ6=0 */
clrReg8Bits(PIEJ, 192);
/* PTJ: PTJ7=0,PTJ6=0 */
clrReg8Bits(PTJ, 192);
/* PERJ: PERJ7=0,PERJ6=0 */
clrReg8Bits(PERJ, 192);
/* DDRJ: DDRJ7=1,DDRJ6=1 */
setReg8Bits(DDRJ, 192);
/* PTS: PTS2=0,PTS1=1 */
clrSetReg8Bits(PTS, 4, 2);
/* WOMS: WOMS2=0 */
clrReg8Bits(WOMS, 4);
/* DDRS: DDRS2=1,DDRS1=1,DDRS0=0 */
clrSetReg8Bits(DDRS, 1, 6);
/* TSCR1: TEN=0,TSWAI=1,TSFRZ=1,TFFCA=0 */
clrSetReg8Bits(TSCR1, 144, 96);
/* PTT: PTT6=0,PTT5=0,PTT4=0,PTT3=0,PTT2=0,PTT1=0 */
clrReg8Bits(PTT, 126);
/* PERT: PERT3=0,PERT2=0 */
clrReg8Bits(PERT, 12);
/* DDRT: DDRT6=1,DDRT5=1,DDRT4=1,DDRT3=1,DDRT2=1,DDRT1=1 */
//#ifndef RPM
//setReg8Bits(DDRT, 126);
//#else
// setReg8Bits(DDRT, 114);
//#endif
/* PEAR: RDWE=0 */
clrReg8Bits(PEAR, 4);
/* DDRE: BIT2=0 */
clrReg8Bits(DDRE, 4);
setReg8Bits(CRGINT, 18); ///DDD clrReg8Bits(CRGINT, 18) BLOQUEO LA INT DEL RTI. PERMITO LA DEL LOCK Y LA DEL SELF CLOCK;
/* PACTL: CLK1=0,CLK0=0 */
clrReg8Bits(PACTL, 12);
/* OC7M: OC7M0=0 */
clrReg8Bits(OC7M, 1);
/* TCTL2: OM1=0,OL1=0,OM0=0,OL0=0 */
clrReg8Bits(TCTL2, 15);
/* TIE: C6I=0,C5I=0,C4I=0,C1I=0,C0I=1 */
clrSetReg8Bits(TIE, 114, 1);
/* TIOS: IOS6=1,IOS5=1,IOS4=1,IOS1=1,IOS0=1 */
setReg8Bits(TIOS, 255);
/* TTOV: TOV6=0,TOV5=0,TOV4=0,TOV1=0,TOV0=0 */
clrReg8Bits(TTOV, 0);
/* TSCR2: TCRE=0,PR2=1,PR1=0,PR0=1 */
clrSetReg8Bits(TSCR2, 10, 5);
/* TFLG1: C7F=1,C6F=1,C5F=1,C4F=1,C3F=1,C2F=1,C1F=1,C0F=1 */
setReg8(TFLG1, 255);
/* MODRR: ??=0,??=0,MODRR4=0,MODRR1=0 */
clrReg8Bits(MODRR, 114);
/* TCTL1: OM6=0,OL6=0,OM5=0,OL5=0,OM4=0,OL4=0 */
clrReg8Bits(TCTL1, 63);
/* PIEP: PIEP7=0,PIEP5=0,PIEP3=0,PIEP1=0 */
clrReg8Bits(PIEP, 170);
/* PTP: PTP7=0,PTP5=0,PTP3=0,PTP1=0 */
clrReg8Bits(PTP, 170);
/* PERP: PERP7=0,PERP5=0,PERP3=0,PERP1=0 */
clrReg8Bits(PERP, 170);
/* DDRP: DDRP7=1,DDRP5=1,DDRP3=1,DDRP1=1 */
setReg8Bits(DDRP, 170);
/* ATDDIEN: IEN3=1,IEN2=1 */
setReg8Bits(ATDDIEN, 12);
/* VREGCTRL: LVIE=0 */
clrReg8Bits(VREGCTRL, 2);
/* RDRIV: RDPE=0,RDPB=0,RDPA=0 */
clrReg8Bits(RDRIV, 19);
/* RDRAD: RDRAD7=0,RDRAD6=0,RDRAD5=0,RDRAD4=0,RDRAD3=0,RDRAD2=0,RDRAD1=0,RDRAD0=0 */
setReg8(RDRAD, 0);
/* RDRJ: RDRJ7=0,RDRJ6=0 */
clrReg8Bits(RDRJ, 192);
/* RDRM: RDRM5=0,RDRM4=0,RDRM3=0,RDRM2=0,RDRM1=0,RDRM0=0 */
clrReg8Bits(RDRM, 63);
/* RDRP: RDRP7=0,RDRP6=0,RDRP5=0,RDRP4=0,RDRP3=0,RDRP2=0,RDRP1=0,RDRP0=0 */
setReg8(RDRP, 0);
/* RDRS: RDRS3=0,RDRS2=0,RDRS1=0,RDRS0=0 */
clrReg8Bits(RDRS, 15);
/* RDRT: RDRT7=0,RDRT6=0,RDRT5=0,RDRT4=0,RDRT3=0,RDRT2=0,RDRT1=0,RDRT0=0 */
setReg8(RDRT, 0);
/* INTCR: IRQEN=0 */
clrReg8Bits(INTCR, 64);
/* ### MC9S12GC16_80 "Cpu" init code ... */
/* ### ByteIO "Display1" init code ... */
/* ### BitsIO "bits5ULN" init code ... */
/* ### BitsIO "bits2ULN" init code ... */
/* ### BitIO "trx" init code ... */
/* ### BitsIO "PTSL" init code ... */
/* ### BitIO "PWSN" init code ... */
/* ### InputPin "PUL" init code ... */
/* ### WatchDog "WDog1" init code ... */
/* ### Asynchro serial "AS1" init code ... */
AS1_Init();
/* ### Init_ADC "ADC1" init code ... */
#ifndef RPM
ADC1_Init();
#endif
/* ### Init_FLASH "FLASH1" init code ... */
FLASH1_Init();
/* ### TimerInt "TI1" init code ... */
TI1_Init();
/* ### TimerOut "PWM" init code ... */
PWM_Init();
/* ### TimerOut "PWM4" init code ... */
PWM4_Init();
/* ### TimerOut "PWM5" init code ... */
PWM5_Init();
/* ### TimerOut "PWM6" init code ... */
PWM6_Init();
EI2C1_Init();
/* TSCR1: TEN=1 */
setReg8Bits(TSCR1, 128);
__EI(); /* Enable interrupts */
}
