Пример #1
0
int fecpin_setclear(struct eth_device *dev, int setclear)
{
    gpio_t *gpio = (gpio_t *) MMAP_GPIO;
    struct fec_info_s *info = (struct fec_info_s *)dev->priv;

#ifdef CONFIG_MCF5445x
    if (setclear) {
#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
        if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
            setbits_be16(&gpio->par_feci2c,
                         GPIO_PAR_FECI2C_MDC0_MDC0 |
                         GPIO_PAR_FECI2C_MDIO0_MDIO0);
        else
            setbits_be16(&gpio->par_feci2c,
                         GPIO_PAR_FECI2C_MDC1_MDC1 |
                         GPIO_PAR_FECI2C_MDIO1_MDIO1);
#else
        setbits_be16(&gpio->par_feci2c,
                     GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
#endif

        if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
            setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
        else
            setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
    } else {
        clrbits_be16(&gpio->par_feci2c,
                     GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);

        if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
#ifdef CONFIG_SYS_FEC_FULL_MII
            setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
#else
            clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
#endif
        } else {
#ifdef CONFIG_SYS_FEC_FULL_MII
            setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
#else
            clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
#endif
        }
    }
#endif	/* CONFIG_MCF5445x */

#ifdef CONFIG_MCF5441x
    if (setclear) {
        out_8(&gpio->par_fec, 0x03);
        out_8(&gpio->srcr_fec, 0x0F);
        clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
                     GPIO_PAR_SIMP0H_DAT_GPIO);
        clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
                     GPIO_PDDR_G4_OUTPUT);
        clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);

    } else
        clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
#endif
    return 0;
}
Пример #2
0
int fecpin_setclear(struct eth_device *dev, int setclear)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	struct fec_info_s *info = (struct fec_info_s *)dev->priv;

	if (setclear) {
		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
			setbits_8(&gpio->par_fec,
				GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
			setbits_8(&gpio->par_feci2c,
				GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0);
		} else {
			setbits_8(&gpio->par_fec,
				GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
			setbits_8(&gpio->par_feci2c,
				GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1);
		}
	} else {
		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
			clrbits_8(&gpio->par_fec,
				GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
			clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK);
		} else {
			clrbits_8(&gpio->par_fec,
				GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
			clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK);
		}
	}
	return 0;
}
Пример #3
0
void uart_port_conf(int port)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Setup Ports: */
	switch (port) {
	case 0:
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
		break;
	case 1:
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
		break;
	case 2:
#ifdef CONFIG_SYS_UART2_ALT1_GPIO
		clrbits_8(&gpio->par_timer, 0xf0);
		setbits_8(&gpio->par_timer,
			GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
		clrbits_8(&gpio->par_feci2c, 0x00ff);
		setbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
#elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
		clrbits_be16(&gpio->par_ssi, 0x0f00);
		setbits_be16(&gpio->par_ssi,
			GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
#endif
		break;
	}
}
Пример #4
0
static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
{
	u8 icic = SH_IC_TACK;

	debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
				__func__, chip, addr, iccl, icch);
	clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
	setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);

	writeb(iccl & 0xff, &dev->iccl);
	writeb(icch & 0xff, &dev->icch);
#ifdef CONFIG_SH_I2C_8BIT
	if (iccl > 0xff)
		icic |= SH_I2C_ICIC_ICCLB8;
	if (icch > 0xff)
		icic |= SH_I2C_ICIC_ICCHB8;
#endif
	writeb(icic, &dev->icic);

	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
	sh_irq_dte(dev);

	clrbits_8(&dev->icsr, SH_IC_TACK);
	writeb(chip << 1, &dev->icdr);
	if (sh_irq_dte_with_tack(dev) != 0)
		return -1;

	writeb(addr, &dev->icdr);
	if (stop)
		writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);

	if (sh_irq_dte_with_tack(dev) != 0)
		return -1;
	return 0;
}
Пример #5
0
int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	int which_tsec = -1;
	u8 *pixis_base = (u8 *)PIXIS_BASE;
	uchar mask;
	uchar switch_mask;

	if (argc > 2)
		if (strcmp(argv[1], "all") != 0)
			which_tsec = simple_strtoul(argv[1], NULL, 0);

	switch (which_tsec) {
#ifdef CONFIG_TSEC1
	case 1:
		mask = PIXIS_VSPEED2_TSEC1SER;
		switch_mask = PIXIS_VCFGEN1_TSEC1SER;
		break;
#endif
#ifdef CONFIG_TSEC2
	case 2:
		mask = PIXIS_VSPEED2_TSEC2SER;
		switch_mask = PIXIS_VCFGEN1_TSEC2SER;
		break;
#endif
#ifdef CONFIG_TSEC3
	case 3:
		mask = PIXIS_VSPEED2_TSEC3SER;
		switch_mask = PIXIS_VCFGEN1_TSEC3SER;
		break;
#endif
#ifdef CONFIG_TSEC4
	case 4:
		mask = PIXIS_VSPEED2_TSEC4SER;
		switch_mask = PIXIS_VCFGEN1_TSEC4SER;
		break;
#endif
	default:
		mask = PIXIS_VSPEED2_MASK;
		switch_mask = PIXIS_VCFGEN1_MASK;
		break;
	}

	/* Toggle whether the switches or FPGA control the settings */
	if (!strcmp(argv[argc - 1], "switch"))
		clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
	else
		setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);

	/* If it's not the switches, enable or disable SGMII, as specified */
	if (!strcmp(argv[argc - 1], "on"))
		clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
	else if (!strcmp(argv[argc - 1], "off"))
		setbits_8(pixis_base + PIXIS_VSPEED2, mask);

	return 0;
}
Пример #6
0
void uart_port_conf(int port)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Setup Ports: */
	switch (port) {
	case 0:
		clrbits_8(&gpio->par_uart,
			GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
		setbits_8(&gpio->par_uart,
			GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
		break;
	case 1:
#ifdef CONFIG_SYS_UART1_ALT1_GPIO
		clrbits_8(&gpio->par_simp1h,
			GPIO_PAR_SIMP1H_DATA1_UNMASK |
			GPIO_PAR_SIMP1H_VEN1_UNMASK);
		setbits_8(&gpio->par_simp1h,
			GPIO_PAR_SIMP1H_DATA1_U1TXD |
			GPIO_PAR_SIMP1H_VEN1_U1RXD);
#elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
		clrbits_8(&gpio->par_ssih,
			GPIO_PAR_SSIH_RXD_UNMASK |
			GPIO_PAR_SSIH_TXD_UNMASK);
		setbits_8(&gpio->par_ssih,
			GPIO_PAR_SSIH_RXD_U1RXD |
			GPIO_PAR_SSIH_TXD_U1TXD);
#endif
		break;
	case 2:
#ifdef CONFIG_SYS_UART2_PRI_GPIO
		setbits_8(&gpio->par_uart,
			GPIO_PAR_UART_U2TXD |
			GPIO_PAR_UART_U2RXD);
#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
		clrbits_8(&gpio->par_dspih,
			GPIO_PAR_DSPIH_SIN_UNMASK |
			GPIO_PAR_DSPIH_SOUT_UNMASK);
		setbits_8(&gpio->par_dspih,
			GPIO_PAR_DSPIH_SIN_U2RXD |
			GPIO_PAR_DSPIH_SOUT_U2TXD);
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
		clrbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_SDA_UNMASK |
			GPIO_PAR_FECI2C_SCL_UNMASK);
		setbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_SDA_U2TXD |
			GPIO_PAR_FECI2C_SCL_U2RXD);
#endif
		break;
	}
}
Пример #7
0
/*
 * Enable the max77686 register
 *
 * @param reg		register number of buck/ldo to be enabled
 * @param enable	enable or disable bit
 *
 *			REG_DISABLE = 0,
			needed to set the buck/ldo enable bit OFF
 * @return		Return 0 if ok, else -1
 */
static int max77686_enablereg(unsigned int bus, enum max77686_regnum reg, int enable)
{
	struct max77686_para *pmic;
	unsigned char read_data;
	int ret;

	pmic = &max77686_param[reg];

	ret = max77686_i2c_read(bus, MAX77686_I2C_ADDR, pmic->reg_enaddr,
				&read_data);
	if (ret != 0) {
		printk(BIOS_DEBUG, "max77686 i2c read failed.\n");
		return -1;
	}

	if (enable == REG_DISABLE) {
		clrbits_8(&read_data,
				pmic->reg_enbitmask << pmic->reg_enbitpos);
	} else {
		clrsetbits_8(&read_data,
				pmic->reg_enbitmask << pmic->reg_enbitpos,
				pmic->reg_enbiton << pmic->reg_enbitpos);
	}

	ret = max77686_i2c_write(bus, MAX77686_I2C_ADDR,
				 pmic->reg_enaddr, read_data);
	if (ret != 0) {
		printk(BIOS_DEBUG, "max77686 i2c write failed.\n");
		return -1;
	}

	return 0;
}
Пример #8
0
/*
 * Enable the s5m8767 register
 *
 * @param reg		register number of buck/ldo to be enabled
 * @param enable	enable or disable bit
 *
 *			S5M8767_REG_DISABLE = 0,
			needed to set the buck/ldo enable bit OFF
 * @return		Return 0 if ok, else -1
 */
static int s5m8767_enablereg(enum s5m8767_regnum reg, int enable)
{
	struct s5m8767_para *pmic;
	unsigned char read_data;
	int ret;

	pmic = &s5m8767_param[reg];

	ret = s5m8767_i2c_read(S5M8767_I2C_ADDR, pmic->reg_enaddr,
				&read_data);
	if (ret != 0) {
		debug("s5m8767 i2c read failed.\n");
		return -1;
	}

	if (enable == S5M8767_REG_DISABLE) {
		clrbits_8(&read_data,
				pmic->reg_enbitmask << pmic->reg_enbitpos);
	} else {
		clrsetbits_8(&read_data,
				pmic->reg_enbitmask << pmic->reg_enbitpos,
				pmic->reg_enbiton << pmic->reg_enbitpos);
	}

	ret = s5m8767_i2c_write(S5M8767_I2C_ADDR,
				 pmic->reg_enaddr, read_data);
	if (ret != 0) {
		debug("s5m8767 i2c write failed.\n");
		return -1;
	}

	return 0;
}
Пример #9
0
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
	     void *din, unsigned long flags)
{
	struct ka2000_spi *spi = (struct ka2000_spi *)ka2000_SPI;
	int i, iter = bitlen >> 3;
	const uchar *txp = dout;
	uchar *rxp = din;

	debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
	      slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen);

	if (flags & SPI_XFER_BEGIN)
		setbits_8(&spi->pdr, SPI_PDR_SS);

	for (i = 0; i < iter; i++) {
		udelay(1000);
		debug("spi_xfer: sending %x\n", txp[i]);
		out_8(&spi->dr, txp[i]);
		while (!(in_8(&spi->sr) & SPI_SR_SPIF)) {
			udelay(1000);
			if (in_8(&spi->sr) & SPI_SR_WCOL) {
				rxp[i] = in_8(&spi->dr);
				puts("spi_xfer: write collision\n");
				return -1;
			}
		}
		rxp[i] = in_8(&spi->dr);
		debug("spi_xfer: received %x\n", rxp[i]);
	}
	if (flags & SPI_XFER_END)
		clrbits_8(&spi->pdr, SPI_PDR_SS);

	return 0;
}
Пример #10
0
void uart_port_conf(int port)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Setup Ports: */
	switch (port) {
	case 0:
		clrbits_be16(&gpio->par_uart,
			~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
		break;
	case 1:
		clrbits_be16(&gpio->par_uart,
			~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
		break;
	case 2:
		clrbits_8(&gpio->par_dspi,
			~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
		out_8(&gpio->par_dspi,
			GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
		break;
	}
}
Пример #11
0
void uart_port_conf(int port)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Setup Ports: */
	switch (port) {
	case 0:
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
		break;
	case 1:
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
		break;
	case 2:
#ifdef CONFIG_SYS_UART2_PRI_GPIO
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
		clrbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
		setbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
#endif
		break;
	}
}
Пример #12
0
int fecpin_setclear(struct eth_device *dev, int setclear)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	if (setclear) {
		setbits_8(&gpio->par_fec,
			GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
		setbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
	} else {
		clrbits_8(&gpio->par_fec,
			GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
		clrbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
	}
	return 0;
}
Пример #13
0
static void dp501_clrbits(u8 addr, u8 reg, u8 mask)
{
	u8 val;

	val = i2c_reg_read(addr, reg);
	clrbits_8(&val, mask);
	i2c_reg_write(addr, reg, val);
}
Пример #14
0
void board_mem_sleep_setup(void)
{
	void __iomem *qixis_base = (void *)QIXIS_BASE;

	/* does not provide HW signals for power management */
	clrbits_8(qixis_base + 0x21, 0x2);
	udelay(1);
}
Пример #15
0
/* Disable the watchdog
 *
 */
static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
				      char *argv[])
{
	/* Disable the VELA sequencer and the watchdog */
	clrbits_8(pixis_base + PIXIS_VCTL, 9);

	return 0;
}
Пример #16
0
void cfspi_release_bus(uint bus, uint cs)
{
	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Clear FIFO */
	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);

	switch (cs) {
	case 0:
		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
		break;
	case 2:
		clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
		break;
	}
}
Пример #17
0
/*
 * I2C is a synchronous protocol and resets of the processor in the middle
 * of an access can block the I2C Bus until a powerdown of the full unit is
 * done. This function toggles the SCL until the SCL and SCA line are
 * released, but max. 16 times, after this a I2C start-sequence is sent.
 * This I2C Deblocking mechanism was developed by Keymile in association
 * with Anatech and Atmel in 1998.
 */
int i2c_make_abort(void)
{

#if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD)
	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
	i2c8260_t *i2c	= (i2c8260_t *)&immap->im_i2c;

	/*
	 * disable I2C controller first, otherwhise it thinks we want to
	 * talk to the slave port...
	 */
	clrbits_8(&i2c->i2c_i2mod, 0x01);

	/* Set the PortPins to GPIO */
	setports(1);
#endif

	int	scl_state = 0;
	int	sda_state = 0;
	int	i = 0;
	int	ret = 0;

	if (!get_sda()) {
		ret = -1;
		while (i < 16) {
			i++;
			set_scl(0);
			udelay(DELAY_ABORT_SEQ);
			set_scl(1);
			udelay(DELAY_ABORT_SEQ);
			scl_state = get_scl();
			sda_state = get_sda();
			if (scl_state && sda_state) {
				ret = 0;
				printf("[INFO] i2c abort after %d clocks\n", i);
				break;
			}
		}
	}
	if (ret == 0)
		for (i = 0; i < 5; i++)
			i2c_write_start_seq();
	else
		printf("[ERROR] i2c abort failed\n");

	/* respect stop setup time */
	udelay(DELAY_ABORT_SEQ);
	set_scl(1);
	udelay(DELAY_ABORT_SEQ);
	set_sda(1);
	get_sda();

#if defined(CONFIG_HARD_I2C)
	/* Set the PortPins back to use for I2C */
	setports(0);
#endif
	return ret;
}
Пример #18
0
/* Reset the board with watchdog disabled.
 *
 * This respects the altbank setting.
 */
static void set_px_go(void)
{
	/* Disable the VELA sequencer and watchdog */
	clrbits_8(pixis_base + PIXIS_VCTL, 9);

	/* Reboot by starting the VELA sequencer */
	setbits_8(pixis_base + PIXIS_VCTL, 0x1);

	while (1);
}
Пример #19
0
/* Reset the board with watchdog enabled.
 *
 * This respects the altbank setting.
 */
static void set_px_go_with_watchdog(void)
{
	/* Disable the VELA sequencer */
	clrbits_8(pixis_base + PIXIS_VCTL, 1);

	/* Enable the watchdog and reboot by starting the VELA sequencer */
	setbits_8(pixis_base + PIXIS_VCTL, 0x9);

	while (1);
}
Пример #20
0
int fpga_pgm_fn(int assert, int flush, int cookie)
{
	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;

	if (!assert)
		setbits_8(&gpio->sint_dvo, FPGA_STATUS);
	else
		clrbits_8(&gpio->sint_dvo, FPGA_STATUS);

	return assert;
}
Пример #21
0
int checkboard(void)
{
	u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR;

	printf("Board: P1023 RDS\n");

	clrbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG_CLR);
	setbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG0);

	return 0;
}
Пример #22
0
static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
{
	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;

	if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
		clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
	else
		setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);

	if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
		clrbits_8(&bcsr[17], BCSR17_USBVCC);
		clrbits_8(&bcsr[17], BCSR17_USBMODE);
		do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
				   "peripheral", sizeof("peripheral"), 1);
	} else {
		setbits_8(&bcsr[17], BCSR17_USBVCC);
		setbits_8(&bcsr[17], BCSR17_USBMODE);
	}

	clrbits_8(&bcsr[17], BCSR17_nUSBEN);
}
Пример #23
0
void cfspi_release_bus(uint bus, uint cs)
{
    dspi_t *dspi = (dspi_t *) MMAP_DSPI;
    gpio_t *gpio = (gpio_t *) MMAP_GPIO;

    /* Clear FIFO */
    clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);

#ifdef CONFIG_MCF5445x
    switch (cs) {
    case 0:
        clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
        break;
    case 1:
        clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
        break;
    case 2:
        clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
        break;
    case 3:
        clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
        break;
    case 5:
        clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
        break;
    }
#endif

#ifdef CONFIG_MCF5441x
    if (cs == 1)
        clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
#endif
}
Пример #24
0
void enable_8569mds_qe_uec(void)
{
#if defined(CONFIG_SYS_UCC_RGMII_MODE)
	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
			BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
			BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
			BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
			BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
#elif defined(CONFIG_SYS_UCC_RMII_MODE)
	/* Set UCC1-4 working at RMII mode */
	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
			BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
			BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
			BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
			BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
#endif
}
Пример #25
0
int cfspi_claim_bus(uint bus, uint cs)
{
	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
		return -1;

	/* Clear FIFO and resume transfer */
	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);

	switch (cs) {
	case 0:
		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
		break;
	case 2:
		clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
		setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
		break;
	}

	return 0;
}
Пример #26
0
int cfspi_claim_bus(uint bus, uint cs)
{
    dspi_t *dspi = (dspi_t *) MMAP_DSPI;
    gpio_t *gpio = (gpio_t *) MMAP_GPIO;

    if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
        return -1;

    /* Clear FIFO and resume transfer */
    clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);

#ifdef CONFIG_MCF5445x
    switch (cs) {
    case 0:
        clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
        setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
        break;
    case 1:
        clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
        setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
        break;
    case 2:
        clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
        setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
        break;
    case 3:
        clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
        setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
        break;
    case 5:
        clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
        setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
        break;
    }
#endif

#ifdef CONFIG_MCF5441x
    switch (cs) {
    case 0:
        clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
        setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
        break;
    case 1:
        clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
        setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
        break;
    }
#endif

    return 0;
}
Пример #27
0
int board_nand_init(struct nand_chip *nand)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/*
	 * set up pin configuration - enabled 2nd output buffer's signals
	 * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
	 * to use nCE signal
	 */
	clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
	setbits_8(&gpio->pddr_timer, 0x08);
	setbits_8(&gpio->ppd_timer, 0x08);
	out_8(&gpio->pclrr_timer, 0);
	out_8(&gpio->podr_timer, 0);

	nand->chip_delay = 60;
	nand->ecc.mode = NAND_ECC_SOFT;
	nand->cmd_ctrl = nand_hwcontrol;

	return 0;
}
Пример #28
0
int board_eth_init(bd_t *bis)
{
	u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR;
	ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
	struct fsl_pq_mdio_info dtsec_mdio_info;

	/*
	 * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
	 * is not correct.
	 */
	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);

	dtsec_mdio_info.regs =
		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;

	/* Register the 1G MDIO bus */
	fsl_pq_mdio_init(bis, &dtsec_mdio_info);

	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);

	fm_info_set_mdio(FM1_DTSEC1,
		miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
	fm_info_set_mdio(FM1_DTSEC2,
		miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));

	/* Make SERDES connected to SGMII by cleaing bcsr19[7] */
	if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII)
		clrbits_8(&bcsr[19], BCSR19_SGMII_SEL_L);

#ifdef CONFIG_FMAN_ENET
	cpu_eth_init(bis);
#endif

	return pci_eth_init(bis);
}
Пример #29
0
void disable_8569mds_brd_eeprom_write_protect(void)
{
	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
}
Пример #30
0
void disable_8569mds_flash_write(void)
{
	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
}