/*
* Set up the clock source and clock events devices
*/
static void __init __cns3xxx_timer_init(unsigned int timer_irq)
{
u32 val;
u32 irq_mask;
/*
* Initialise to a known state (all timers off)
*/
/* disable timer1 and timer2 */
writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
/* stop free running timer3 */
writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
/* timer1 */
writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
/* mask irq, non-mask timer1 overflow */
irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
irq_mask &= ~(1 << 2);
irq_mask |= 0x03;
writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
/* down counter */
val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
val |= (1 << 9);
writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
/* timer2 */
writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
/* mask irq */
irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
/* down counter */
val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
val |= (1 << 10);
writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
/* Make irqs happen for the system timer */
setup_irq(timer_irq, &cns3xxx_timer_irq);
cns3xxx_clockevents_init(timer_irq);
}
/*
* Set up the clock source and clock events devices
*/
void __init __ts43xx_timer_init(unsigned int timer_irq)
{
u32 val, irq_mask;
/*
* Initialise to a known state (all timers off)
*/
writel(0, timer1_va_base + TIMER1_2_CONTROL_OFFSET); /* Disable timer1, 2 and 3 */
writel(0, timer1_va_base + TIMER_FREERUN_CONTROL_OFFSET); /* Stop free running timer4 */
/************ timer1 ************/
#ifdef CONFIG_SILICON
timer1_reload = NR_CYCLES_PER_TICK;
#else
timer1_reload = 0x25000;
#endif
writel(timer1_reload, timer1_va_base + TIMER1_COUNTER_OFFSET);
writel(timer1_reload, timer1_va_base + TIMER1_AUTO_RELOAD_OFFSET);
writel(0xFFFFFFFF, timer1_va_base + TIMER1_MATCH_V1_OFFSET);
writel(0xFFFFFFFF, timer1_va_base + TIMER1_MATCH_V2_OFFSET);
/* mask irq, non-mask timer1 overflow */
irq_mask = readl(timer1_va_base + TIMER1_2_INTERRUPT_MASK_OFFSET);
irq_mask &= ~(1 << 2);
irq_mask |= 0x03;
writel(irq_mask, timer1_va_base + TIMER1_2_INTERRUPT_MASK_OFFSET);
/* down counter */
val = readl(timer1_va_base + TIMER1_2_CONTROL_OFFSET);
val |= TIMER1_DOWN_COUNT;
writel(val, timer1_va_base + TIMER1_2_CONTROL_OFFSET);
/************ timer2 ************/
/* Configure timer2 as periodic free-running clocksource, interrupt disabled. */
writel(0, timer1_va_base + TIMER2_COUNTER_OFFSET);
writel(0xFFFFFFFF, timer1_va_base + TIMER2_AUTO_RELOAD_OFFSET);
writel(0xFFFFFFFF, timer1_va_base + TIMER2_MATCH_V1_OFFSET);
writel(0xFFFFFFFF, timer1_va_base + TIMER2_MATCH_V2_OFFSET);
/* mask irq */
irq_mask = readl(timer1_va_base + TIMER1_2_INTERRUPT_MASK_OFFSET);
irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
writel(irq_mask, timer1_va_base + TIMER1_2_INTERRUPT_MASK_OFFSET);
/* Enable timer2 /Use 1K Hz clock source / Up count */
val = readl(timer1_va_base + TIMER1_2_CONTROL_OFFSET);
val |= TIMER2_ENABLE | TIMER2_USE_1KHZ_SOURCE;
writel(val, timer1_va_base + TIMER1_2_CONTROL_OFFSET);
/************ timer3 ************/
/* Not enabled */
/************ timer4 ************/
writel(TIMER4_RESET, timer1_va_base + TIMER_FREERUN_CONTROL_OFFSET);
writel(TIMER4_ENABLE, timer1_va_base + TIMER_FREERUN_CONTROL_OFFSET);
/*
* Make irqs happen for the system timer
*/
/* Clear all interrupts */
writel(0x000001FF, timer1_va_base + TIMER1_2_INTERRUPT_STATUS_OFFSET);
setup_irq(timer_irq, &cns3xxx_timer1_irq);
cns3xxx_clocksource_init();
cns3xxx_clockevents_init(timer_irq);
}
