kal_int32 arm_enter_standby_mode(kal_int32 mode)
{
#if defined(MT6280)
// if 0x8000001c[13]=1, arm clock force on
if (*(volatile kal_uint32*)(0x8000001c) & (1<<13))
*MDMCU_DCM_CON_0 |= (1<<26);
else
*MDMCU_DCM_CON_0 &= ~(1<<26);
#endif
#if defined(MT6572) || defined(MT6582) || defined(MT6592) || defined(MT6571) || defined(MT6580)
#if defined (DCM_ENABLE)
/**
* workaround: to disable prefecth buffer that is affected while TOP MDMCU DCM gating MDMCU clock.
* TOP MDMCU DCM will gating mcu_clock, thus make prefecth buffer broken out.
**/
Bus_PFB_Disable();
#endif //#if defined (DCM_ENABLE)
#endif //#if defined(MT6572) || defined(MT6582) || defined(MT6592) || defined(MT6571) || defined(MT6580)
cp15_enter_low_pwr_state();
#if defined(MT6572) || defined(MT6582) || defined(MT6592) || defined(MT6571) || defined(MT6580)
#if defined (DCM_ENABLE)
Bus_PFB_Enable();
#endif //#if defined (DCM_ENABLE)
#endif //#if defined(MT6572) || defined(MT6582) || defined(MT6592) || defined(MT6571) || defined(MT6580)
return 0;
}
/*****************************************************************************
*
* Filename:
* ---------
* dcm_service.c
*
* Project:
* --------
* MOLY
*
* Description:
* ------------
* This file provides dcm APIs to get device information
*
* Author:
* -------
* -------
*
*============================================================================
* HISTORY
* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
*------------------------------------------------------------------------------
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
*------------------------------------------------------------------------------
* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
*============================================================================
****************************************************************************/
#ifdef __MTK_TARGET__
#if defined(MT6290) && defined(__ARM7EJ_S__)
#include "mpu_mtk_mmu_v2_int.h"
#else /* end of "defined(MT6290) && defined(__ARM7EJ_S__)" */
#include "cp15.h"
#endif /* end of else of "defined(MT6290) && defined(__ARM7EJ_S__)" */
#include "drv_comm.h"
#include "drv_dcm.h"
//#include "dcm_sw.h"
#include "intrCtrl.h"
#include "devdrv_ls.h"
#include "pll.h"
#include "sleepdrv_interface.h"
#include "sync_data.h"
volatile kal_uint32 dcm_mcubus_dcm_off = 0;
#if defined(MT6290) && defined(__ARM7EJ_S__)
__attribute__ ((section("COPRO_INTSRAM_RW")))
#else /* end of "defined(MT6290) && defined(__ARM7EJ_S__)" */
DEVDRV_LS_INTSRAM_ROCODE
#endif /* end of else of "defined(MT6290) && defined(__ARM7EJ_S__)" */
kal_int32 arm_enter_standby_mode(kal_int32 mode)
{
#if defined(MT6290) && defined(__ARM7EJ_S__)
MCU_ENTER_POWER_SAVING_MODE();
#else /* end of "defined(MT6290) && defined(__ARM7EJ_S__)" */
cp15_enter_low_pwr_state();
#endif /* end of else of "defined(MT6290) && defined(__ARM7EJ_S__)" */
return 0;
}
/* Note that idle task is only created when MTK_SLEEP_ENABLE is defined. */
void IdleTask( task_entry_struct * task_entry_ptr )
{
#if defined(KAL_ON_NUCLEUS)
IdleTaskTCB = (NU_TASK*)task_info_g[task_entry_ptr->task_indx].task_id;
#elif defined(KAL_ON_THREADX)
IdleTaskTCB = (TX_THREAD *)task_info_g[task_entry_ptr->task_indx].task_id;
#endif
while(1)
{
/* Partial sleep mode for MCU and AVB block.
To force MCU and AVB bus CLK stopped when system is in idle task.
System will run again and CLK resume automatically only when IRQ comes.
*/
#if defined(MTK_SLEEP_ENABLE) || defined(L1D_TEST)
#if defined( DCM_ENABLE )
kal_uint32 _savedMask;
volatile kal_uint16 i,j=0;
register kal_uint32 start, end, duration, tqwrap;
_savedMask = LockIRQ();
start = *((volatile kal_uint16 *)(TDMA_base + 0x00));
/* Check if DMA, GMC and LCD_DMA is in Power Down Mode. */
if (
#if (IS_CHIP_MT6229)
(((*(volatile kal_uint32 *)0x80030000) & 0x00055555)==0) && /* Check DMA1~10, ignore DMA11~14 */
(((*PDN_CON0) & 0x0078) == 0x0078) && /* Check PDN_CON0 IRDMA, PPP, CHE, and WAVETABLE down */
((*PDN_CON1) & 0x0080) && /* Check PDN_CON1 LCD down */
((*PDN_CON3) == 0xFFFF) && /* Check PDN_CON3 all down [GMC]*/
*MCUCLK_CON == 0x0703 &&
#elif ( (IS_CHIP_MT6238) || (IS_CHIP_MT6235) ) //add by jerry
(((*DMA_GLBSTA) & 0x00055555)==0) && /* Check DMA1~10, ignore DMA11~14 */
(((*PDN_CON0) & 0x0078) == 0x0078) && /* Check PDN_CON0 IRDMA, PPP, CHE, and WAVETABLE down */
((*PDN_CON1) & 0x0080) && /* Check PDN_CON1 LCD down */
((*PDN_CON3) == 0xFFFF) && /* Check PDN_CON3 all down [GMC]*/
*MCUCLK_CON == 0x7F37 && /*EMICLK,ARMCLK,AHBX4CLK,AHBX8CLK,104,208,52,104*/
#elif (IS_CHIP_MT6228)
(((*(volatile kal_uint32 *)0x80030000) & 0x00055555)==0) && /* Check DMA1~10, ignore DMA11~14 */
(((*PDN_CON0) & 0x0038) == 0x0038) && /* Check PDN_CON0 PPP, CHE, and WAVETABLE down */
((*PDN_CON1) & 0x0080) && /* Check PDN_CON1 LCD down */
((*PDN_CON3) == 0xFFFF) && /* Check PDN_CON3 all down [GMC]*/
*MCUCLK_CON == 0x0703 &&
#elif ( IS_CHIP_MT6223)
(((*(volatile kal_uint32 *)0x80030000) & 0x00055555)==0) && /* Check DMA1~10, ignore DMA11~14 */
(((*PDN_CON0) & 0x0048) == 0x0048) && /* Check PDN_CON0 IRDMA, and WAVETABLE down */
((*PDN_CON1) & 0x0080) && /* Check PDN_CON1 LCD down */
((*PDN_CON3) == 0x0001) && /* Check PDN_CON3 all down [GMC]*/
*MCUCLK_CON == 0x0303 &&
#elif ( IS_CHIP_MT6225)
(((*(volatile kal_uint32 *)0x80030000) & 0x00055555)==0) && /* Check DMA1~10, ignore DMA11~14 */
(((*PDN_CON0) & 0x0048) == 0x0048) && /* Check PDN_CON0 IRDMA, and WAVETABLE down */
((*PDN_CON1) & 0x0080) && /* Check PDN_CON1 LCD down */
((*PDN_CON3) == 0x1801) && /* Check PDN_CON3 all down [GMC]*/
*MCUCLK_CON == 0x0703 &&
#elif ( IS_CHIP_MT6227)
(((*(volatile kal_uint32 *)0x80030000) & 0x00055555)==0) && /* Check DMA1~10, ignore DMA11~14 */
((*PDN_CON0) & 0x0008) && /* Check PDN_CON0 WAVETABLE down */
((*PDN_CON1) & 0x0080) && /* Check PDN_CON1 LCD down */
(((*PDN_CON3) & 0x7F91) == 0x7F91)&& /* Check PDN_CON3 all down [GMC] (valid:0x7F91) */
*MCUCLK_CON == 0x0003 &&
#elif ( IS_CHIP_MT6217 )
(((*(volatile kal_uint32 *)0x80030000) & 0x00015555)==0) && /* Check DMA1~10, ignore DMA10~13 for 6217 */
(((*PDN_CON0) & 0x0038) == 0x0038) && /* Check PDN_CON0 RESIZER, JPEG, and WAVETABLE down */
((*PDN_CON1) & 0x0080) && /* Check PDN_CON1 LCD down */
*MCUCLK_CON == 0x0003 &&
#endif
dcm.dcmDisable == 0
)
{
#if ( (IS_CHIP_MT6228) || (IS_CHIP_MT6229)||(IS_CHIP_MT6235)||(IS_CHIP_MT6238))
/* Gate GMC DMA */
kal_uint32 tmp;
tmp = GateDG();
for (i = 0; i < 20; i++)
;
#endif
/*To access an address not in existance will ensure that EMI access is complete.*/
#if ( (IS_CHIP_MT6238) || (IS_CHIP_MT6235) )
j = *(volatile kal_uint16 *)0x28000000;
#else
j = *(volatile kal_uint16 *)0x24000000;
#endif
/*A26=1 means will not get data via data cache, it will access EMI directly.*/
dcm_state = 1; /* DCM @ 104/52->13/26Mhz */
/* Change WS and clock rate. */
/* mtk01940
======================================
Idle Dedi
MT6217 13MHz x
MT6229 26MHz 26MHz
MT6227 13MHZ 26MHz
MT6223 13MHz 13MHz
MT6225
MT6228
MT6229
MT6227D
======================================
*/
#if (IS_CHIP_MT6227 || IS_CHIP_MT6228)
#ifdef MT6227D
custom_DynamicClockSwitch( MCU_13MHZ );
#else
if(dcm.isIdleMode)
{
custom_DynamicClockSwitch( MCU_13MHZ );
}
else
{
custom_DynamicClockSwitch( MCU_26MHZ );
}
#endif
#elif (IS_CHIP_MT6229)
custom_DynamicClockSwitch( MCU_26MHZ );
#else
custom_DynamicClockSwitch( MCU_13MHZ );
#endif
/* mtk01940 */
dcm_state = 2; /* DCM @ 13/26MHz */
#if ((IS_CHIP_MT6228) || (IS_CHIP_MT6229)||(IS_CHIP_MT6235)||(IS_CHIP_MT6238))
/* Recover GMC DMA gating */
UngateDG(tmp);
#endif
/* check if IRQ is disabled for more than 60 qbits */
end = *((volatile kal_uint16 *)(TDMA_base + 0x00));
if (end >= start) {
duration = end - start;
} else {
tqwrap = *(volatile kal_uint16 *)(TDMA_base + 0x04);
duration = (tqwrap - start) + end;
}
if (duration > 60) {
EXT_ASSERT(0, duration, start, end);
}
*SLEEP_CON = 0x0003;
#if ( (IS_CHIP_MT6238) || (IS_CHIP_MT6235) )
cp15_enter_low_pwr_state();
#endif /* MT6238 */
}
else
{
*SLEEP_CON = 0x0001;
#if ( (IS_CHIP_MT6238) || (IS_CHIP_MT6235) )
cp15_enter_low_pwr_state();
#endif /* MT6238 */
}
RestoreIRQ(_savedMask);
#elif defined(MT6218B)
kal_uint32 _savedMask;
_savedMask = LockIRQ();
if ( (((*(volatile kal_uint16 *)0x80000300) & 0x0038)==0x0038) &&
((*(volatile kal_uint16 *)0x80000304) & 0x0080) )
{
/* Power down AHB only when WT & JPEG & Resizer & LCD is turned off. */
*SLEEP_CON = 0x0003;
}
else
{
*SLEEP_CON = 0x0001;
}
RestoreIRQ(_savedMask);
#else
/*To temporarily avoid the problem on AHB.*/
*SLEEP_CON = 0x0001;
#endif /* End #if defined(DCM_ENABLE)*/
#endif /* End #if defined(MTK_SLEEP_ENABLE) || defined(L1D_TEST) */
} /* Infinite loop */
}
/** @argu mode : to be defined, currently no usage.
*
**/
kal_int32 arm_enter_standby_mode(kal_int32 mode)
{
#if defined (__CPU_ARM7EJ_S__) || defined (__CPU_ARM7TDMI__) //without cp15 wfi
#if defined (MT6250)
#if !defined (SLEEP_CON)
#define ARM_SLEEP_CON ((volatile UINT16P)(ARM_CONFG_base+0x0040))
#define SLEEP_CON ARM_SLEEP_CON
#endif
kal_uint32 tmp;
tmp = *PLL_CLK_CONDA;
ASSERT(((tmp >> 10) & 0x3f) == 0x21); // assert RG_ARM_PLLCK_SEL1 as 87Mhz, and RG_ARM_PLLCK_SEL2 as 260Mhz
*PLL_CLK_CONDC = (*PLL_CLK_CONDC & ~(0x7<<3)) | (0x2<<3);
*PLL_CLK_CONDC;
/** ASTONE,
* "READ-modify-write" is good for flushing bus transaction, instead of write directly.
* BUT, take care about side effect of read-modify-write, esp. about read-clear bit.
**/
*SLEEP_CON |= 1;
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
/* debug code of long irq latency of TDMA issue. Should be removed after W12.26 */
{
extern kal_uint32 irq_dbg_time_leave_from_sleep;
irq_dbg_time_leave_from_sleep = ust_get_current_time();
}
*PLL_CLK_CONDC = (*PLL_CLK_CONDC & ~(0x7<<3)) | (0x4<<3);
*PLL_CLK_CONDC;
#elif defined (MT6260)
#if !defined (SLEEP_CON)
#define ARM_SLEEP_CON ((volatile UINT16P)(ARM_CONFG_base+0x0040))
#define SLEEP_CON ARM_SLEEP_CON
#endif
{
register kal_uint32 conda, condc, conde;
kal_uint32 _savedmask;
kal_uint32 LockIRQ(void);
void RestoreIRQ(kal_uint32);
_savedmask = LockIRQ();
conda = *PLL_CLK_CONDA;
condc = *PLL_CLK_CONDC;
/* if (mode != 0) { */
/* conde = *PLL_CLK_CONDE; */
/* *PLL_CLK_CONDE = conde & (3<<14); */
/* } */
// switch MCU to MPLL/3 clock;
/* *PLL_CLK_CONDA = (conda | (1<<13)); */
/* *PLL_CLK_CONDC = (condc & ~(0x7<<3) | (0x04 << 3)); */
*PLL_CLK_CONDC = (condc & ~(0x7<<3) | (0x01 << 3));
*PLL_CLK_CONDC;
#if defined(MT6260) && defined(__ESD_LU_NEW_SOLUTION__)
#if !defined(__ESD_LU_NEW_SOLUTION_TEST__)
if (*((volatile unsigned int *)(0xA0700E24)))
#endif /* defined(__ESD_LU_NEW_SOLUTION_TEST__) */
{
kal_uint32 t1, t2;
#if !defined(__ESD_LU_NEW_SOLUTION_TEST__)
if (++dropVoltageCount > 100)
{
// 0.8V
*((volatile kal_uint16 *)(0xA0700230)) = 0x8541;
*((volatile kal_uint16 *)(0xA0700230));
EXT_ASSERT(0, 0, 0, 0);
}
#endif /* defined(__ESD_LU_NEW_SOLUTION_TEST__) */
// 0.975V
*((volatile kal_uint16 *)(0xA0700230)) = 0x85B1;
*((volatile kal_uint16 *)(0xA0700230));
t1 = ust_get_current_time();
do
{
t2 = ust_get_current_time();
} while(ust_get_duration(t1, t2) < 500);
// 1.3V
*((volatile kal_uint16 *)(0xA0700230)) = 0x8481;
*((volatile kal_uint16 *)(0xA0700230));
t1 = ust_get_current_time();
do
{
t2 = ust_get_current_time();
} while(ust_get_duration(t1, t2) < 200);
}
#endif /* defined(__ESD_LU_NEW_SOLUTION__) */
*SLEEP_CON |= 1;
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
*PLL_CLK_CONDA = conda;
*PLL_CLK_CONDC = condc;
*PLL_CLK_CONDC;
/* if (mode != 0) { */
/* *PLL_CLK_CONDE = conde; */
/* } */
/** disable EMI HW DCM,
* 1. to workaround EMI DCM having long DCM recovery time.
* 2. to workaround EMI DCM that has slow reponse MMSYS idle that make normal clock too late to reponse MMSYS request.
**/
MT6260_EMI_DCM_DISABLE();
RestoreIRQ(_savedmask);
}
#else //#if defined (MT6250)
ASSERT(0);
#endif //#if defined (MT6250)
#else //#if defined (__CPU_ARM7EJ_S__) || defined (__CPU_ARM7TDMI__) //without cp15 wfi
cp15_enter_low_pwr_state();
#endif //#if defined (__CPU_ARM7EJ_S__) || defined (__CPU_ARM7TDMI__) //without cp15 wfi
return 0;
}
