static void msg_ind_set_blink(struct msg_ind_led_data *msg_ind_data, bool enable)
{
unsigned short led_reg;
unsigned int i;
if (enable) {
if (!(msg_ind_data->regulator_state&LD_LED_BLINK)) {
cpcap_uc_start(msg_ind_data->cpcap, CPCAP_BANK_PRIMARY, CPCAP_MACRO_6);
printk_cpcap("%s: cpcap_uc_start(CPCAP_MACRO_6)\n", __func__);
if (msg_ind_data->cpcap_leds->rgb_led.regulator_macro_controlled) {
/* Wait for the macro to start. */
cpcap_regacc_read(msg_ind_data->cpcap, CPCAP_REG_REDC, &led_reg);
i = 21;
while ((!(led_reg & LD_MSG_IND_CPCAP_BLINK_ON)) &&
(--i > 0)) {
cpcap_uc_start(msg_ind_data->cpcap, CPCAP_BANK_PRIMARY,
CPCAP_MACRO_6);
msleep(10);
cpcap_regacc_read(msg_ind_data->cpcap, CPCAP_REG_REDC, &led_reg);
}
if (i == 0)
printk(KERN_ERR "%s: Unable to sync CPCAP blink on macro.\n", __func__);
printk_cpcap("%s: Blink macro started.\n", __func__);
/* Shutdown the regulator since the macro handles the regulator. */
msg_ind_set_regulator(msg_ind_data, false, true);
}
msg_ind_data->regulator_state |= LD_LED_BLINK;
}
}
else {
if (msg_ind_data->regulator_state&LD_LED_BLINK) {
cpcap_uc_stop(msg_ind_data->cpcap, CPCAP_BANK_PRIMARY,
CPCAP_MACRO_6);
printk_cpcap("%s: cpcap_uc_stop(CPCAP_MACRO_6)\n", __func__);
if (msg_ind_data->cpcap_leds->rgb_led.regulator_macro_controlled) {
/* Wait for the macro to be stopped before moving on. */
cpcap_regacc_read(msg_ind_data->cpcap, CPCAP_REG_REDC, &led_reg);
i = 21;
while ((led_reg & LD_MSG_IND_CPCAP_BLINK_ON) &&
(--i > 0)) {
cpcap_uc_stop(msg_ind_data->cpcap, CPCAP_BANK_PRIMARY,
CPCAP_MACRO_6);
msleep(10);
cpcap_regacc_read(msg_ind_data->cpcap, CPCAP_REG_REDC, &led_reg);
}
if (i == 0)
printk(KERN_ERR "%s: Unable to sync CPCAP blink off macro.\n", __func__);
printk_cpcap("%s: Blink macro stopped.\n", __func__);
/* If any LED's are on re-enable the regulator. */
if (msg_ind_data->regulator_state&(LD_LED_RED|LD_LED_GREEN|LD_LED_BLUE))
msg_ind_set_regulator(msg_ind_data, true, false);
}
msg_ind_data->regulator_state &= ~LD_LED_BLINK;
}
}
}
static int cpcap_regulator_get_voltage(struct regulator_dev *rdev)
{
struct cpcap_device *cpcap;
int regltr_id;
unsigned short volt_bits;
enum cpcap_reg regnr;
unsigned int shift;
cpcap = rdev_get_drvdata(rdev);
regltr_id = rdev_get_id(rdev);
if (regltr_id >= CPCAP_NUM_REGULATORS)
return -EINVAL;
regnr = cpcap_regltr_data[regltr_id].reg;
if (cpcap_regacc_read(cpcap, regnr, &volt_bits) < 0)
return -1;
if (!(volt_bits & cpcap_regltr_data[regltr_id].mode_mask))
return 0;
volt_bits &= cpcap_regltr_data[regltr_id].volt_mask;
volt_bits -= cpcap_regltr_data[regltr_id].bit_offset_from_cpcap_lowest_voltage;
shift = cpcap_regltr_data[regltr_id].volt_shft;
return cpcap_regltr_data[regltr_id].val_tbl[volt_bits >> shift];
}
static void logged_cpcap_write(struct cpcap_device *cpcap, unsigned int reg,
unsigned short int value, unsigned short int mask)
{
if (mask != 0) {
int ret_val = 0;
#ifdef CPCAP_AUDIO_SPI_LOG
printk(KERN_DEBUG
"CPCAP_AUDIO_SPI_WRITE: reg %u, value 0x%x,mask 0x%x\n",
CPCAP_REG_FOR_POWERIC_REG(reg), value, mask);
#endif
ret_val = cpcap_regacc_write(cpcap, reg, value, mask);
if (ret_val != 0)
CPCAP_AUDIO_ERROR_LOG(
"Write to register %u failed: error %d \n",
reg, ret_val);
#ifdef CPCAP_AUDIO_SPI_READBACK
ret_val = cpcap_regacc_read(cpcap, reg, &value);
if (ret_val == 0)
printk(KERN_DEBUG
"CPCAP_AUDIO_SPI_VERIFY reg %u: value 0x%x \n",
CPCAP_REG_FOR_POWERIC_REG(reg), value);
else
printk(KERN_ERR
"CPCAP_AUDIO_SPI_VERIFY reg %u FAILED\n",
CPCAP_REG_FOR_POWERIC_REG(reg));
#endif
}
}
enum cpcap_revision cpcap_get_revision(struct cpcap_device *cpcap)
{
unsigned short value;
/* Code taken from drivers/mfd/cpcap_core.c, since the revision value
is not initialized until after the registers are initialized, which
will happen after the trgra_cpcap_spi_init table is used. */
(void)cpcap_regacc_read(cpcap, CPCAP_REG_VERSC1, &value);
return (enum cpcap_revision)(((value >> 3) & 0x0007) |
((value << 3) & 0x0038));
}
static int cpcap_regulator_is_enabled(struct regulator_dev *rdev)
{
struct cpcap_device *cpcap = rdev_get_drvdata(rdev);
int regltr_id;
enum cpcap_reg regnr;
unsigned short value;
regltr_id = rdev_get_id(rdev);
if (regltr_id >= CPCAP_NUM_REGULATORS)
return -EINVAL;
regnr = cpcap_regltr_data[regltr_id].reg;
if (cpcap_regacc_read(cpcap, regnr, &value))
return -1;
return (value & cpcap_regltr_data[regltr_id].mode_mask) ? 1 : 0;
}
void force_to_detect_usb(void)
{
unsigned char sense = 0;
unsigned short value;
cpcap_regacc_read(temp_data->cpcap, CPCAP_REG_INTS2, &value);
/* Clear ASAP after read. */
cpcap_regacc_write(temp_data->cpcap, CPCAP_REG_INT2,
(CPCAP_BIT_CHRGCURR1_I |
CPCAP_BIT_VBUSVLD_I |
CPCAP_BIT_SESSVLD_I |
CPCAP_BIT_SE1_I),
(CPCAP_BIT_CHRGCURR1_I |
CPCAP_BIT_VBUSVLD_I |
CPCAP_BIT_SESSVLD_I |
CPCAP_BIT_SE1_I));
sense = ((value & CPCAP_BIT_VBUSVLD_S) ? 1 : 0);
if (!sense)
schedule_delayed_work(&temp_data->work, msecs_to_jiffies(0));
}
static void logged_cpcap_write(struct cpcap_device *cpcap, unsigned int reg,
unsigned short int value, unsigned short int mask)
{
if (mask != 0) {
int ret_val = 0;
pr_debug("%s: audio: reg %u, value 0x%x,mask 0x%x\n", __func__,
CPCAP_REG_FOR_POWERIC_REG(reg), value, mask);
ret_val = cpcap_regacc_write(cpcap, reg, value, mask);
if (ret_val != 0)
E("%s: w %04x m %04x -> r %u failed: %d\n", __func__,
value, mask, reg, ret_val);
#if CPCAP_AUDIO_SPI_READBACK
ret_val = cpcap_regacc_read(cpcap, reg, &value);
if (ret_val == 0)
pr_debug("%s: audio verify: reg %u: value 0x%x\n",
__func__,
CPCAP_REG_FOR_POWERIC_REG(reg), value);
else
E("%s: audio verify: reg %u FAILED\n", __func__,
CPCAP_REG_FOR_POWERIC_REG(reg));
#endif
}
}
static int get_sense(struct cpcap_usb_det_data *data)
{
int retval = -EFAULT;
unsigned short value;
struct cpcap_device *cpcap;
if (!data)
return -EFAULT;
cpcap = data->cpcap;
retval = cpcap_regacc_read(cpcap, CPCAP_REG_INTS1, &value);
if (retval)
return retval;
/* Clear ASAP after read. */
retval = cpcap_regacc_write(cpcap, CPCAP_REG_INT1,
(CPCAP_BIT_CHRG_DET_I |
CPCAP_BIT_ID_GROUND_I),
(CPCAP_BIT_CHRG_DET_I |
CPCAP_BIT_ID_GROUND_I));
if (retval)
return retval;
data->sense = value & (CPCAP_BIT_ID_FLOAT_S |
CPCAP_BIT_ID_GROUND_S);
retval = cpcap_regacc_read(cpcap, CPCAP_REG_INTS2, &value);
if (retval)
return retval;
/* Clear ASAP after read. */
retval = cpcap_regacc_write(cpcap, CPCAP_REG_INT2,
(CPCAP_BIT_CHRGCURR1_I |
CPCAP_BIT_VBUSVLD_I |
CPCAP_BIT_SESSVLD_I |
CPCAP_BIT_SE1_I),
(CPCAP_BIT_CHRGCURR1_I |
CPCAP_BIT_VBUSVLD_I |
CPCAP_BIT_SESSVLD_I |
CPCAP_BIT_SE1_I));
if (retval)
return retval;
data->sense |= value & (CPCAP_BIT_CHRGCURR1_S |
CPCAP_BIT_VBUSVLD_S |
CPCAP_BIT_SESSVLD_S |
CPCAP_BIT_SE1_S);
retval = cpcap_regacc_read(cpcap, CPCAP_REG_INTS4, &value);
if (retval)
return retval;
/* Clear ASAP after read. */
retval = cpcap_regacc_write(cpcap, CPCAP_REG_INT4,
(CPCAP_BIT_DP_I |
CPCAP_BIT_DM_I),
(CPCAP_BIT_DP_I |
CPCAP_BIT_DM_I));
if (retval)
return retval;
data->sense |= (value & (CPCAP_BIT_DP_S |
CPCAP_BIT_DM_S)) << CPCAP_SENSE4_LS;
#ifdef CONFIG_TTA_CHARGER
data->sense_tta.dplus = ((value & CPCAP_BIT_DP_S) ? 1 : 0);
data->sense_tta.dminus = ((value & CPCAP_BIT_DM_S) ? 1 : 0);
data->sense_tta.gpio_val = gpio_get_value(TTU_TTA_CHRG_DET_N_GPIO);
#endif
return 0;
}
static void cpcap_audio_register_dump(struct cpcap_audio_state *state)
{
#ifdef CPCAP_AUDIO_DEBUG
unsigned short reg_val[14] = {0};
int i = 0;
cpcap_regacc_read(state->cpcap, CPCAP_REG_VAUDIOC, ®_val[i++]);
cpcap_regacc_read(state->cpcap, CPCAP_REG_CC, ®_val[i++]);
cpcap_regacc_read(state->cpcap, CPCAP_REG_CDI, ®_val[i++]);
cpcap_regacc_read(state->cpcap, CPCAP_REG_SDAC, ®_val[i++]);
cpcap_regacc_read(state->cpcap, CPCAP_REG_SDACDI, ®_val[i++]);
cpcap_regacc_read(state->cpcap, CPCAP_REG_TXI, ®_val[i++]);
cpcap_regacc_read(state->cpcap, CPCAP_REG_TXMP, ®_val[i++]);
cpcap_regacc_read(state->cpcap, CPCAP_REG_RXOA, ®_val[i++]);
cpcap_regacc_read(state->cpcap, CPCAP_REG_RXVC, ®_val[i++]);
cpcap_regacc_read(state->cpcap, CPCAP_REG_RXCOA, ®_val[i++]);
cpcap_regacc_read(state->cpcap, CPCAP_REG_RXSDOA, ®_val[i++]);
cpcap_regacc_read(state->cpcap, CPCAP_REG_RXEPOA, ®_val[i++]);
cpcap_regacc_read(state->cpcap, CPCAP_REG_RXLL, ®_val[i++]);
cpcap_regacc_read(state->cpcap, CPCAP_REG_A2LA, ®_val[i++]);
printk(KERN_DEBUG " 0x200 = %x\n 0x201 = %x\n 0x202 = %x\n"
" 0x203 = %x\n 0x204 = %x\n 0x205 = %x\n 0x206 = %x\n"
" 0x207 = %x\n 0x208 = %x\n 0x209 = %x\n 0x20A = %x\n"
" 0x20B = %x\n 0x20C = %x\n 0x20D = %x\n", reg_val[0],
reg_val[1], reg_val[2], reg_val[3], reg_val[4],
reg_val[5], reg_val[6], reg_val[7], reg_val[8],
reg_val[9], reg_val[10], reg_val[11], reg_val[12],
reg_val[13]);
#else
return;
#endif /* CPCAP_AUDIO_DEBUG */
}
static void cpcap_audio_reguister_dump(struct cpcap_audio_state *state)
{
unsigned short reg_val = 0;
cpcap_regacc_read(state->cpcap, CPCAP_REG_VAUDIOC, ®_val);
printk(KERN_INFO "0x200 = %x\n", reg_val);
cpcap_regacc_read(state->cpcap, CPCAP_REG_CC, ®_val);
printk(KERN_INFO "0x201 = %x\n", reg_val);
cpcap_regacc_read(state->cpcap, CPCAP_REG_CDI, ®_val);
printk(KERN_INFO "0x202 = %x\n", reg_val);
cpcap_regacc_read(state->cpcap, CPCAP_REG_SDAC, ®_val);
printk(KERN_INFO "0x203 = %x\n", reg_val);
cpcap_regacc_read(state->cpcap, CPCAP_REG_SDACDI, ®_val);
printk(KERN_INFO "0x204 = %x\n", reg_val);
cpcap_regacc_read(state->cpcap, CPCAP_REG_TXI, ®_val);
printk(KERN_INFO "0x205 = %x\n", reg_val);
cpcap_regacc_read(state->cpcap, CPCAP_REG_TXMP, ®_val);
printk(KERN_INFO "0x206 = %x\n", reg_val);
cpcap_regacc_read(state->cpcap, CPCAP_REG_RXOA, ®_val);
printk(KERN_INFO "0x207 = %x\n", reg_val);
cpcap_regacc_read(state->cpcap, CPCAP_REG_RXVC, ®_val);
printk(KERN_INFO "0x208 = %x\n", reg_val);
cpcap_regacc_read(state->cpcap, CPCAP_REG_RXCOA, ®_val);
printk(KERN_INFO "0x209 = %x\n", reg_val);
cpcap_regacc_read(state->cpcap, CPCAP_REG_RXSDOA, ®_val);
printk(KERN_INFO "0x20A = %x\n", reg_val);
cpcap_regacc_read(state->cpcap, CPCAP_REG_RXEPOA, ®_val);
printk(KERN_INFO "0x20B = %x\n", reg_val);
}
