void __init cpm_reset(void) { sysconf8xx_t __iomem *siu_conf; mpc8xx_immr = ioremap(get_immrbase(), 0x4000); if (!mpc8xx_immr) { printk(KERN_CRIT "Could not map IMMR\n"); return; } cpmp = &mpc8xx_immr->im_cpm; #ifndef CONFIG_PPC_EARLY_DEBUG_CPM out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG); while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG); #endif #ifdef CONFIG_UCODE_PATCH cpm_load_patch(cpmp); #endif siu_conf = immr_map(im_siu_conf); out_be32(&siu_conf->sc_sdcr, 1); immr_unmap(siu_conf); cpm_muram_init(); }
void m8xx_cpm_reset(uint host_page_addr) { volatile immap_t *imp; volatile cpm8xx_t *commproc; pte_t *pte; imp = (immap_t *)IMAP_ADDR; commproc = (cpm8xx_t *)&imp->im_cpm; #ifdef CONFIG_UCODE_PATCH /* Perform a reset. */ commproc->cp_cpcr = (CPM_CR_RST | CPM_CR_FLG); /* Wait for it. */ while (commproc->cp_cpcr & CPM_CR_FLG); cpm_load_patch(imp); #endif /* Set SDMA Bus Request priority 5. * On 860T, this also enables FEC priority 6. I am not sure * this is what we realy want for some applications, but the * manual recommends it. * Bit 25, FAM can also be set to use FEC aggressive mode (860T). */ imp->im_siu_conf.sc_sdcr = 1; /* Reclaim the DP memory for our use. */ m8xx_cpm_dpinit(); /* Set the host page for allocation. */ host_buffer = host_page_addr; /* Host virtual page address */ host_end = host_page_addr + PAGE_SIZE; /* We need to get this page early, so I have to do it the * hard way. */ if (get_pteptr(&init_mm, host_page_addr, &pte)) { pte_val(*pte) |= _PAGE_NO_CACHE; flush_tlb_page(init_mm.mmap, host_buffer); } else { panic("Huh? No CPM host page?"); } /* Tell everyone where the comm processor resides. */ cpmp = (cpm8xx_t *)commproc; }
void __init cpm_reset(void) { sysconf8xx_t __iomem *siu_conf; mpc8xx_immr = ioremap(get_immrbase(), 0x4000); if (!mpc8xx_immr) { printk(KERN_CRIT "Could not map IMMR\n"); return; } cpmp = &mpc8xx_immr->im_cpm; #ifndef CONFIG_PPC_EARLY_DEBUG_CPM /* Perform a reset. */ out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG); /* Wait for it. */ while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG); #endif #ifdef CONFIG_UCODE_PATCH cpm_load_patch(cpmp); #endif /* Set SDMA Bus Request priority 5. * On 860T, this also enables FEC priority 6. I am not sure * this is what we really want for some applications, but the * manual recommends it. * Bit 25, FAM can also be set to use FEC aggressive mode (860T). */ siu_conf = immr_map(im_siu_conf); if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */ out_be32(&siu_conf->sc_sdcr, 0x40); else out_be32(&siu_conf->sc_sdcr, 1); immr_unmap(siu_conf); cpm_muram_init(); }
void m8xx_cpm_reset(void) { volatile immap_t *imp; volatile cpm8xx_t *commproc; imp = (immap_t *)IMAP_ADDR; commproc = (cpm8xx_t *)&imp->im_cpm; #ifdef CONFIG_UCODE_PATCH /* Perform a reset. */ commproc->cp_cpcr = (CPM_CR_RST | CPM_CR_FLG); /* Wait for it. */ while (commproc->cp_cpcr & CPM_CR_FLG); cpm_load_patch(imp); #endif /* Set SDMA Bus Request priority 5. * On 860T, this also enables FEC priority 6. I am not sure * this is what we really want for some applications, but the * manual recommends it. * Bit 25, FAM can also be set to use FEC aggressive mode (860T). */ out_be32(&imp->im_siu_conf.sc_sdcr, 1), /* Reclaim the DP memory for our use. */ m8xx_cpm_dpinit(); /* Tell everyone where the comm processor resides. */ cpmp = (cpm8xx_t *)commproc; }
void cpm_reset(void) { cpm8xx_t *commproc; sysconf8xx_t *siu_conf; commproc = (cpm8xx_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE); #ifdef CONFIG_UCODE_PATCH /* Perform a reset. */ out_be16(&commproc->cp_cpcr, CPM_CR_RST | CPM_CR_FLG); /* Wait for it. */ while (in_be16(&commproc->cp_cpcr) & CPM_CR_FLG); cpm_load_patch(commproc); #endif /* Set SDMA Bus Request priority 5. * On 860T, this also enables FEC priority 6. I am not sure * this is what we realy want for some applications, but the * manual recommends it. * Bit 25, FAM can also be set to use FEC aggressive mode (860T). */ siu_conf = (sysconf8xx_t*)immr_map(im_siu_conf); out_be32(&siu_conf->sc_sdcr, 1); immr_unmap(siu_conf); /* Reclaim the DP memory for our use. */ m8xx_cpm_dpinit(); /* Tell everyone where the comm processor resides. */ cpmp = commproc; }
/* * Breath some life into the CPU... * * Set up the memory map, * initialize a bunch of registers, * initialize the UPM's */ void cpu_init_f (volatile immap_t * immr) { volatile memctl8xx_t *memctl = &immr->im_memctl; # ifdef CONFIG_SYS_PLPRCR ulong mfmask; # endif ulong reg; /* SYPCR - contains watchdog control (11-9) */ immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR; #if defined(CONFIG_WATCHDOG) reset_8xx_watchdog (immr); #endif /* CONFIG_WATCHDOG */ /* SIUMCR - contains debug pin configuration (11-6) */ immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR; /* initialize timebase status and control register (11-26) */ /* unlock TBSCRK */ immr->im_sitk.sitk_tbscrk = KAPWR_KEY; immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR; /* initialize the PIT (11-31) */ immr->im_sitk.sitk_piscrk = KAPWR_KEY; immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; /* System integration timers. Don't change EBDF! (15-27) */ immr->im_clkrstk.cark_sccrk = KAPWR_KEY; reg = immr->im_clkrst.car_sccr; reg &= SCCR_MASK; reg |= CONFIG_SYS_SCCR; immr->im_clkrst.car_sccr = reg; /* PLL (CPU clock) settings (15-30) */ immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr, * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF * field value. * * For newer (starting MPC866) chips PLPRCR layout is different. */ #ifdef CONFIG_SYS_PLPRCR if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK) mfmask = PLPRCR_MFACT_MSK; else mfmask = PLPRCR_MF_MSK; if ((CONFIG_SYS_PLPRCR & mfmask) != 0) reg = CONFIG_SYS_PLPRCR; /* reset control bits */ else { reg = immr->im_clkrst.car_plprcr; reg &= mfmask; /* isolate MF-related fields */ reg |= CONFIG_SYS_PLPRCR; /* reset control bits */ } immr->im_clkrst.car_plprcr = reg; #endif /* * Memory Controller: */ /* perform BR0 reset that MPC850 Rev. A can't guarantee */ reg = memctl->memc_br0; reg &= BR_PS_MSK; /* Clear everything except Port Size bits */ reg |= BR_V; /* then add just the "Bank Valid" bit */ memctl->memc_br0 = reg; /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at * preliminary addresses - these have to be modified later * when FLASH size has been determined * * Depending on the size of the memory region defined by * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't * map CONFIG_SYS_MONITOR_BASE. * * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000. * * If BR0 wasn't loaded with address base 0xff000000, then BR0's * base address remains as 0x00000000. However, the address mask * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped * into the Bank0. * * This is why CONFIG_IVMS8 and similar boards must load BR0 with * CONFIG_SYS_BR0_PRELIM in advance. * * [Thanks to Michael Liao for this explanation. * I owe him a free beer. - wd] */ #if defined(CONFIG_HERMES) || \ defined(CONFIG_IP860) || \ defined(CONFIG_IVML24) || \ defined(CONFIG_IVMS8) || \ defined(CONFIG_LWMON) || \ defined(CONFIG_R360MPI) || \ defined(CONFIG_RMU) || \ defined(CONFIG_SPD823TS) memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; #endif #if defined(CONFIG_SYS_OR0_REMAP) memctl->memc_or0 = CONFIG_SYS_OR0_REMAP; #endif #if defined(CONFIG_SYS_OR1_REMAP) memctl->memc_or1 = CONFIG_SYS_OR1_REMAP; #endif #if defined(CONFIG_SYS_OR5_REMAP) memctl->memc_or5 = CONFIG_SYS_OR5_REMAP; #endif /* now restrict to preliminary range */ memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; #endif #if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */ memctl->memc_br0 = 0; #endif #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; #endif #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; #endif #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; #endif #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; #endif #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM; memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM; #endif #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM; memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; #endif /* * Reset CPM */ immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG; do { /* Spin until command processed */ __asm__ ("eieio"); } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); #ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */ /* write config value */ immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR; #endif #if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \ defined(CONFIG_SYS_SMC_UCODE_PATCH) cpm_load_patch (immr); /* load mpc8xx microcode patch */ #endif }