static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data,
int clk_id)
{
int sel_bit, set = 0;
u16 reg = OMAP2_CONTROL_DEVCONF0;
if (cpu_class_is_omap1())
return -EINVAL; /* TODO: Can this be implemented for OMAP1? */
if (mcbsp_data->bus_id != 0)
return -EINVAL;
switch (clk_id) {
case OMAP_MCBSP_CLKR_SRC_CLKX:
set = 1;
case OMAP_MCBSP_CLKR_SRC_CLKR:
sel_bit = 3;
break;
case OMAP_MCBSP_FSR_SRC_FSX:
set = 1;
case OMAP_MCBSP_FSR_SRC_FSR:
sel_bit = 4;
break;
default:
return -EINVAL;
}
if (set)
omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
else
omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
return 0;
}
static int __init omap1_pm_runtime_init(void)
{
const struct dev_pm_ops *pm;
struct dev_pm_ops *omap_pm;
if (!cpu_class_is_omap1())
return -ENODEV;
pm = platform_bus_get_pm_ops();
if (!pm) {
pr_err("%s: unable to get dev_pm_ops from platform_bus\n",
__func__);
return -ENODEV;
}
omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL);
if (!omap_pm) {
pr_err("%s: unable to alloc memory for new dev_pm_ops\n",
__func__);
return -ENOMEM;
}
omap_pm->runtime_suspend = omap1_pm_runtime_suspend;
omap_pm->runtime_resume = omap1_pm_runtime_resume;
platform_bus_set_pm_ops(omap_pm);
return 0;
}
void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
{
void *reg_cache;
if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
mcbsp->pdata->ops->free(mcbsp->id - 1);
if (mcbsp->pdata->has_wakeup)
MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
if (mcbsp->rx_irq)
free_irq(mcbsp->rx_irq, (void *)mcbsp);
free_irq(mcbsp->tx_irq, (void *)mcbsp);
reg_cache = mcbsp->reg_cache;
if (!cpu_class_is_omap1())
omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
spin_lock(&mcbsp->lock);
if (mcbsp->free)
dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
else
mcbsp->free = true;
mcbsp->reg_cache = NULL;
spin_unlock(&mcbsp->lock);
if (reg_cache)
kfree(reg_cache);
}
static int __init omap1_mcbsp_init(void)
{
if (!cpu_class_is_omap1())
return -ENODEV;
if (cpu_is_omap7xx())
omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0,
OMAP7XX_MCBSP_RES_SZ,
omap7xx_mcbsp_pdata,
OMAP7XX_MCBSP_COUNT);
if (cpu_is_omap15xx())
omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res_0,
OMAP15XX_MCBSP_RES_SZ,
omap15xx_mcbsp_pdata,
OMAP15XX_MCBSP_COUNT);
if (cpu_is_omap16xx())
omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res_0,
OMAP16XX_MCBSP_RES_SZ,
omap16xx_mcbsp_pdata,
OMAP16XX_MCBSP_COUNT);
return 0;
}
static int __init omap_init_lcd_dma(void)
{
int r;
if (!cpu_class_is_omap1())
return -ENODEV;
if (cpu_is_omap16xx()) {
u16 w;
/* this would prevent OMAP sleep */
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
spin_lock_init(&lcd_dma.lock);
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
"LCD DMA", NULL);
if (r != 0)
printk(KERN_ERR "unable to request IRQ for LCD DMA "
"(error %d)\n", r);
return r;
}
static int __init omap1_mcbsp_init(void)
{
if (!cpu_class_is_omap1())
return -ENODEV;
if (cpu_is_omap7xx()) {
omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ;
omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16);
} else if (cpu_is_omap15xx()) {
omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16);
} else if (cpu_is_omap16xx()) {
omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ;
omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16);
}
mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
GFP_KERNEL);
if (!mcbsp_ptr)
return -ENOMEM;
if (cpu_is_omap7xx())
omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata,
OMAP7XX_MCBSP_PDATA_SZ);
if (cpu_is_omap15xx())
omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
OMAP15XX_MCBSP_PDATA_SZ);
if (cpu_is_omap16xx())
omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata,
OMAP16XX_MCBSP_PDATA_SZ);
return omap_mcbsp_init();
}
/*
* Sets the Omap MUX and PULL_DWN registers based on the table
*/
int __init_or_module omap_cfg_reg(const unsigned long index)
{
struct pin_config *reg;
if (!cpu_class_is_omap1()) {
printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
index);
WARN_ON(1);
return -EINVAL;
}
if (mux_cfg == NULL) {
printk(KERN_ERR "Pin mux table not initialized\n");
return -ENODEV;
}
if (index >= mux_cfg->size) {
printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
index, mux_cfg->size);
dump_stack();
return -ENODEV;
}
reg = (struct pin_config *)&mux_cfg->pins[index];
if (!mux_cfg->cfg_reg)
return -ENODEV;
return mux_cfg->cfg_reg(reg);
}
static int omap_pcm_prepare(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct omap_runtime_data *prtd = runtime->private_data;
struct omap_pcm_dma_data *dma_data = prtd->dma_data;
struct omap_dma_channel_params dma_params;
int bytes;
/* return if this is a bufferless transfer e.g.
* codec <--> BT codec or GSM modem -- lg FIXME */
if (!prtd->dma_data)
return 0;
memset(&dma_params, 0, sizeof(dma_params));
dma_params.data_type = dma_data->data_type;
dma_params.trigger = dma_data->dma_req;
dma_params.sync_mode = dma_data->sync_mode;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
dma_params.src_amode = OMAP_DMA_AMODE_POST_INC;
dma_params.dst_amode = OMAP_DMA_AMODE_CONSTANT;
dma_params.src_or_dst_synch = OMAP_DMA_DST_SYNC;
dma_params.src_start = runtime->dma_addr;
dma_params.dst_start = dma_data->port_addr;
dma_params.dst_port = OMAP_DMA_PORT_MPUI;
dma_params.dst_fi = dma_data->packet_size;
} else {
dma_params.src_amode = OMAP_DMA_AMODE_CONSTANT;
dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC;
dma_params.src_or_dst_synch = OMAP_DMA_SRC_SYNC;
dma_params.src_start = dma_data->port_addr;
dma_params.dst_start = runtime->dma_addr;
dma_params.src_port = OMAP_DMA_PORT_MPUI;
dma_params.src_fi = dma_data->packet_size;
}
/*
* Set DMA transfer frame size equal to ALSA period size and frame
* count as no. of ALSA periods. Then with DMA frame interrupt enabled,
* we can transfer the whole ALSA buffer with single DMA transfer but
* still can get an interrupt at each period bounary
*/
bytes = snd_pcm_lib_period_bytes(substream);
dma_params.elem_count = bytes >> dma_data->data_type;
dma_params.frame_count = runtime->periods;
omap_set_dma_params(prtd->dma_ch, &dma_params);
if ((cpu_is_omap1510()))
omap_enable_dma_irq(prtd->dma_ch, OMAP_DMA_FRAME_IRQ |
OMAP_DMA_LAST_IRQ | OMAP_DMA_BLOCK_IRQ);
else
omap_enable_dma_irq(prtd->dma_ch, OMAP_DMA_FRAME_IRQ);
if (!(cpu_class_is_omap1())) {
omap_set_dma_src_burst_mode(prtd->dma_ch,
OMAP_DMA_DATA_BURST_16);
omap_set_dma_dest_burst_mode(prtd->dma_ch,
OMAP_DMA_DATA_BURST_16);
}
return 0;
}
void omap_writel(u32 v, u32 pa)
{
if (cpu_class_is_omap1())
__raw_writel(v, OMAP1_IO_ADDRESS(pa));
else
__raw_writel(v, OMAP2_IO_ADDRESS(pa));
}
/*
* Intercept ioremap() requests for addresses in our fixed mapping regions.
*/
void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
{
#ifdef CONFIG_ARCH_OMAP1
if (cpu_class_is_omap1()) {
if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT);
}
if (cpu_is_omap7xx()) {
if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE))
return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START);
if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE))
return XLATE(p, OMAP7XX_DSPREG_BASE,
OMAP7XX_DSPREG_START);
}
if (cpu_is_omap15xx()) {
if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
return XLATE(p, OMAP1510_DSP_BASE, OMAP1510_DSP_START);
if (BETWEEN(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_SIZE))
return XLATE(p, OMAP1510_DSPREG_BASE,
OMAP1510_DSPREG_START);
}
if (cpu_is_omap16xx()) {
if (BETWEEN(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_SIZE))
return XLATE(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_START);
if (BETWEEN(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_SIZE))
return XLATE(p, OMAP16XX_DSPREG_BASE,
OMAP16XX_DSPREG_START);
}
#endif
#ifdef CONFIG_ARCH_OMAP2
if (cpu_is_omap24xx()) {
if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE))
return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT);
if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE))
return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT);
}
if (cpu_is_omap2420()) {
if (BETWEEN(p, DSP_MEM_2420_PHYS, DSP_MEM_2420_SIZE))
return XLATE(p, DSP_MEM_2420_PHYS, DSP_MEM_2420_VIRT);
if (BETWEEN(p, DSP_IPI_2420_PHYS, DSP_IPI_2420_SIZE))
return XLATE(p, DSP_IPI_2420_PHYS, DSP_IPI_2420_SIZE);
if (BETWEEN(p, DSP_MMU_2420_PHYS, DSP_MMU_2420_SIZE))
return XLATE(p, DSP_MMU_2420_PHYS, DSP_MMU_2420_VIRT);
}
if (cpu_is_omap2430()) {
if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE))
return XLATE(p, L4_WK_243X_PHYS, L4_WK_243X_VIRT);
if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE))
return XLATE(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT);
if (BETWEEN(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_SIZE))
return XLATE(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_VIRT);
if (BETWEEN(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_SIZE))
return XLATE(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_VIRT);
}
#endif
#ifdef CONFIG_ARCH_OMAP3
<<<<<<< HEAD
void omap_stop_dma(int lch)
{
u32 l;
/* Disable all interrupts on the channel */
if (cpu_class_is_omap1())
dma_write(0, CICR(lch));
l = dma_read(CCR(lch));
l &= ~OMAP_DMA_CCR_EN;
dma_write(l, CCR(lch));
if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
int next_lch, cur_lch = lch;
char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
do {
/* The loop case: we've been here already */
if (dma_chan_link_map[cur_lch])
break;
/* Mark the current channel */
dma_chan_link_map[cur_lch] = 1;
disable_lnk(cur_lch);
next_lch = dma_chan[cur_lch].next_lch;
cur_lch = next_lch;
} while (next_lch != -1);
}
dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
}
static int __init omap_i2c_add_bus(int bus_id)
{
if (cpu_class_is_omap1())
return omap1_i2c_add_bus(bus_id);
else
return omap2_i2c_add_bus(bus_id);
}
static int __init omap_init(void)
{
if (!cpu_class_is_omap1())
return -ENODEV;
return platform_device_register(&serial_device);
}
/*
* Clears any DMA state so the DMA engine is ready to restart with new buffers
* through omap_start_dma(). Any buffers in flight are discarded.
*/
void omap_clear_dma(int lch)
{
unsigned long flags;
flags = splhigh();
if (cpu_class_is_omap1()) {
u32 l;
l = dma_read(CCR(lch));
l &= ~OMAP_DMA_CCR_EN;
dma_write(l, CCR(lch));
/* Clear pending interrupts */
l = dma_read(CSR(lch));
}
if (cpu_class_is_omap2()) {
int i;
void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
for (i = 0; i < 0x44; i += 4)
__raw_writel(0, lch_base + i);
}
splx(flags);
}
/* Note that dest_port is only for OMAP1 */
void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
unsigned long dest_start,
int dst_ei, int dst_fi)
{
u32 l;
if (cpu_class_is_omap1()) {
l = dma_read(CSDP(lch));
l &= ~(0x1f << 9);
l |= dest_port << 9;
dma_write(l, CSDP(lch));
}
l = dma_read(CCR(lch));
l &= ~(0x03 << 14);
l |= dest_amode << 14;
dma_write(l, CCR(lch));
if (cpu_class_is_omap1()) {
dma_write(dest_start >> 16, CDSA_U(lch));
dma_write(dest_start, CDSA_L(lch));
}
if (cpu_class_is_omap2())
dma_write(dest_start, CDSA(lch));
dma_write(dst_ei, CDEI(lch));
dma_write(dst_fi, CDFI(lch));
}
/* Note that src_port is only for omap1 */
void omap_set_dma_src_params(int lch, int src_port, int src_amode,
unsigned long src_start,
int src_ei, int src_fi)
{
u32 l;
if (cpu_class_is_omap1()) {
u16 w;
w = dma_read(CSDP(lch));
w &= ~(0x1f << 2);
w |= src_port << 2;
dma_write(w, CSDP(lch));
}
l = dma_read(CCR(lch));
l &= ~(0x03 << 12);
l |= src_amode << 12;
dma_write(l, CCR(lch));
if (cpu_class_is_omap1()) {
dma_write(src_start >> 16, CSSA_U(lch));
dma_write((u16)src_start, CSSA_L(lch));
}
if (cpu_class_is_omap2())
dma_write(src_start, CSSA(lch));
dma_write(src_ei, CSEI(lch));
dma_write(src_fi, CSFI(lch));
}
void omap_writew(u16 v, u32 pa)
{
if (cpu_class_is_omap1())
__raw_writew(v, OMAP1_IO_ADDRESS(pa));
else
__raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
}
u32 omap_readl(u32 pa)
{
if (cpu_class_is_omap1())
return __raw_readl(OMAP1_IO_ADDRESS(pa));
else
return __raw_readl(OMAP2_IO_ADDRESS(pa));
}
void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
int frame_count, int sync_mode,
int dma_trigger, int src_or_dst_synch)
{
u32 l;
l = dma_read(CSDP(lch));
l &= ~0x03;
l |= data_type;
dma_write(l, CSDP(lch));
if (cpu_class_is_omap1()) {
u16 ccr;
ccr = dma_read(CCR(lch));
ccr &= ~(1 << 5);
if (sync_mode == OMAP_DMA_SYNC_FRAME)
ccr |= 1 << 5;
dma_write(ccr, CCR(lch));
ccr = dma_read(CCR2(lch));
ccr &= ~(1 << 2);
if (sync_mode == OMAP_DMA_SYNC_BLOCK)
ccr |= 1 << 2;
dma_write(ccr, CCR2(lch));
}
if (cpu_class_is_omap2() && dma_trigger) {
u32 val;
val = dma_read(CCR(lch));
/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
val &= ~((3 << 19) | 0x1f);
val |= (dma_trigger & ~0x1f) << 14;
val |= dma_trigger & 0x1f;
if (sync_mode & OMAP_DMA_SYNC_FRAME)
val |= 1 << 5;
else
val &= ~(1 << 5);
if (sync_mode & OMAP_DMA_SYNC_BLOCK)
val |= 1 << 18;
else
val &= ~(1 << 18);
if (src_or_dst_synch)
val |= 1 << 24; /* source synch */
else
val &= ~(1 << 24); /* dest synch */
dma_write(val, CCR(lch));
}
dma_write(elem_count, CEN(lch));
dma_write(frame_count, CFN(lch));
}
static int __init omap1_pm_runtime_init(void)
{
if (!cpu_class_is_omap1())
return -ENODEV;
pm_clk_add_notifier(&platform_bus_type, &platform_bus_notifier);
return 0;
}
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len)
{
int ports, err;
struct platform_device *pdev;
struct resource *res;
resource_size_t base, irq;
if (cpu_class_is_omap1())
ports = 1;
else if (cpu_is_omap24xx())
ports = 2;
else if (cpu_is_omap34xx())
ports = 3;
BUG_ON(bus_id < 1 || bus_id > ports);
if (info) {
err = i2c_register_board_info(bus_id, info, len);
if (err)
return err;
}
pdev = &omap_i2c_devices[bus_id - 1];
*(u32 *)pdev->dev.platform_data = clkrate;
if (bus_id == 1) {
res = pdev->resource;
if (cpu_class_is_omap1()) {
base = OMAP1_I2C_BASE;
irq = INT_I2C;
} else {
base = OMAP2_I2C_BASE1;
irq = INT_24XX_I2C1_IRQ;
}
res[0].start = base;
res[0].end = base + OMAP_I2C_SIZE;
res[1].start = irq;
}
omap_i2c_mux_pins(bus_id - 1);
return platform_device_register(pdev);
}
void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
{
if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
u32 l;
l = dma_read(LCH_CTRL(lch));
l &= ~0x7;
l |= mode;
dma_write(l, LCH_CTRL(lch));
}
}
/**
* omap_plat_register_i2c_bus - register I2C bus with device descriptors
* @bus_id: bus id counting from number 1
* @clkrate: clock rate of the bus in kHz
* @info: pointer into I2C device descriptor table or NULL
* @len: number of descriptors in the table
*
* Returns 0 on success or an error code.
*/
int __init omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
struct omap_i2c_bus_board_data *pdata,
struct i2c_board_info const *info,
unsigned len)
{
int err;
int nr_ports = 0;
if (cpu_class_is_omap1())
nr_ports = omap1_i2c_nr_ports();
else if (cpu_class_is_omap2())
nr_ports = omap2_i2c_nr_ports();
BUG_ON(bus_id < 1 || bus_id > nr_ports);
if (info) {
err = i2c_register_board_info(bus_id, info, len);
if (err)
return err;
}
if (!omap_i2c_pdata[bus_id - 1].rate)
omap_i2c_pdata[bus_id - 1].rate = clkrate;
omap_i2c_pdata[bus_id - 1].rate &= ~OMAP_I2C_CMDLINE_SETUP;
if (pdata != NULL && pdata->handle != NULL) {
omap_i2c_pdata[bus_id - 1].handle = pdata->handle;
omap_i2c_pdata[bus_id - 1].hwspinlock_lock
= pdata->hwspinlock_lock;
omap_i2c_pdata[bus_id - 1].hwspinlock_unlock
= pdata->hwspinlock_unlock;
}
if (cpu_class_is_omap1())
return omap1_i2c_add_bus(bus_id);
else if (cpu_class_is_omap2())
return omap2_i2c_add_bus(bus_id);
return 0;
}
static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
int clk_id)
{
int sel_bit;
u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
if (cpu_class_is_omap1()) {
/* OMAP1's can use only external source clock */
if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
return -EINVAL;
else
return 0;
}
if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
return -EINVAL;
if (cpu_is_omap343x())
reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
switch (mcbsp_data->bus_id) {
case 0:
reg = OMAP2_CONTROL_DEVCONF0;
sel_bit = 2;
break;
case 1:
reg = OMAP2_CONTROL_DEVCONF0;
sel_bit = 6;
break;
case 2:
reg = reg_devconf1;
sel_bit = 0;
break;
case 3:
reg = reg_devconf1;
sel_bit = 2;
break;
case 4:
reg = reg_devconf1;
sel_bit = 4;
break;
default:
return -EINVAL;
}
if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
else
omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
return 0;
}
static inline void omap_enable_channel_irq(int lch)
{
u32 status;
/* Clear CSR */
if (cpu_class_is_omap1())
status = dma_read(CSR(lch));
else if (cpu_class_is_omap2())
dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
/* Enable some nice interrupts. */
dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
}
static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
{
if (cpu_class_is_omap1()) {
((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
__raw_writew((u16)val, mcbsp->io_base + reg);
} else if (cpu_is_omap2420()) {
((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
__raw_writew((u16)val, mcbsp->io_base + reg);
} else {
((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
__raw_writel(val, mcbsp->io_base + reg);
}
}
static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
{
if (cpu_class_is_omap1()) {
return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
} else if (cpu_is_omap2420()) {
return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
} else {
return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
}
}
static int __init omap_i2c_nr_ports(void)
{
int ports = 0;
if (cpu_class_is_omap1())
ports = 1;
else if (cpu_is_omap24xx())
ports = 2;
else if (cpu_is_omap34xx())
ports = 3;
return ports;
}
static int __init
omap_leds_init(void)
{
if (!cpu_class_is_omap1())
return -ENODEV;
if (machine_is_omap_innovator())
leds_event = innovator_leds_event;
else if (machine_is_omap_h2()
|| machine_is_omap_h3()
|| machine_is_omap_perseus2())
leds_event = h2p2_dbg_leds_event;
else if (machine_is_omap_osk())
leds_event = osk_leds_event;
else
return -1;
if (machine_is_omap_h2()
|| machine_is_omap_h3()
#ifdef CONFIG_OMAP_OSK_MISTRAL
|| machine_is_omap_osk()
#endif
) {
/* LED1/LED2 pins can be used as GPIO (as done here), or by
* the LPG (works even in deep sleep!), to drive a bicolor
* LED on the H2 sample board, and another on the H2/P2
* "surfer" expansion board.
*
* The same pins drive a LED on the OSK Mistral board, but
* that's a different kind of LED (just one color at a time).
*/
omap_cfg_reg(P18_1610_GPIO3);
if (gpio_request(3, "LED red") == 0)
gpio_direction_output(3, 1);
else
printk(KERN_WARNING "LED: can't get GPIO3/red?\n");
omap_cfg_reg(MPUIO4);
if (gpio_request(OMAP_MPUIO(4), "LED green") == 0)
gpio_direction_output(OMAP_MPUIO(4), 1);
else
printk(KERN_WARNING "LED: can't get MPUIO4/green?\n");
}
leds_event(led_start);
return 0;
}
int omap_dma_running(void)
{
int lch;
#if 0
if (cpu_class_is_omap1())
if (omap_lcd_dma_running())
return 1;
#endif
for (lch = 0; lch < dma_chan_count; lch++)
if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
return 1;
return 0;
}
