void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
{
unsigned int tmp;
while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
& 0x00000001) != 0x00000001)
;
__raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
tmp &= ~(phy_cfg->pgcr1_mask);
tmp |= phy_cfg->pgcr1_val;
__raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
__raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET);
__raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET);
__raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET);
__raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET);
tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
tmp &= ~(phy_cfg->dcr_mask);
tmp |= phy_cfg->dcr_val;
__raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
__raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
__raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
__raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
__raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
if (!cpu_is_k2g())
__raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
__raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
__raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
__raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
__raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
__raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
;
if (cpu_is_k2g()) {
setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1);
}
__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
;
}
int arch_cpu_init(void)
{
chip_configuration_unlock();
icache_enable();
if (cpu_is_k2g()) {
msmc_k2g_setup();
} else {
msmc_k2hkle_common_setup();
if (cpu_is_k2e())
msmc_k2e_setup();
else if (cpu_is_k2l())
msmc_k2l_setup();
else
msmc_k2hk_setup();
}
/* Initialize the PCIe-0 to work as Root Complex */
config_pcie_mode(0, ROOTCOMPLEX);
#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
/* Initialize the PCIe-1 to work as Root Complex */
config_pcie_mode(1, ROOTCOMPLEX);
#endif
#ifdef CONFIG_SOC_K2L
osr_init();
#endif
/*
* just initialise the COM2 port so that TI specific
* UART register PWREMU_MGMT is initialized. Linux UART
* driver doesn't handle this.
*/
#ifndef CONFIG_DM_SERIAL
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
#endif
return 0;
}
static void ddr3_reset_data(u32 base, u32 ddr3_size)
{
u32 mpax[2];
u32 seg_num;
u32 seg, blks, dst, edma_blks;
struct edma3_slot_config slot;
struct edma3_channel_config edma_channel;
u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };
/* Setup an edma to copy the 1k block to the entire DDR */
puts("\nClear entire DDR3 memory to enable ECC\n");
/* save the SES MPAX regs */
if (cpu_is_k2g())
msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
else
msmc_get_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
/* setup edma slot 1 configuration */
slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
EDMA3_SLOPT_COMP_CODE(0) |
EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
slot.bcnt = DDR3_EDMA_BCNT;
slot.acnt = DDR3_EDMA_BLK_SIZE;
slot.ccnt = DDR3_EDMA_CCNT;
slot.src_bidx = 0;
slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
slot.src_cidx = 0;
slot.dst_cidx = 0;
slot.link = EDMA3_PARSET_NULL_LINK;
slot.bcntrld = 0;
edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot);
/* configure quik edma channel */
edma_channel.slot = DDR3_EDMA_SLOT_NUM;
edma_channel.chnum = 0;
edma_channel.complete_code = 0;
/* event trigger after dst update */
edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
qedma3_start(KS2_EDMA0_BASE, &edma_channel);
/* DDR3 size in segments (4KB seg size) */
seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT);
for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
/* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
access slave interface so that edma driver can access */
if (cpu_is_k2g()) {
msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0,
base >> KS2_MSMC_SEG_SIZE_SHIFT,
KS2_MSMC_DST_SEG_BASE + seg,
MPAX_SEG_2G);
} else {
msmc_map_ses_segment(K2HKLE_MSMC_SEGMENT_ARM, 0,
base >> KS2_MSMC_SEG_SIZE_SHIFT,
KS2_MSMC_DST_SEG_BASE + seg,
MPAX_SEG_2G);
}
if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
edma_blks = KS2_MSMC_MAP_SEG_NUM <<
(KS2_MSMC_SEG_SIZE_SHIFT
- DDR3_EDMA_BLK_SIZE_SHIFT);
else
edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT
- DDR3_EDMA_BLK_SIZE_SHIFT);
/* Use edma driver to scrub 2GB DDR memory */
for (dst = base, blks = 0; blks < edma_blks;
blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) {
edma3_set_src_addr(KS2_EDMA0_BASE,
edma_channel.slot, (u32)edma_src);
edma3_set_dest_addr(KS2_EDMA0_BASE,
edma_channel.slot, (u32)dst);
while (edma3_check_for_transfer(KS2_EDMA0_BASE,
&edma_channel))
udelay(10);
}
}
static int ks2_eth_probe(struct udevice *dev)
{
struct ks2_eth_priv *priv = dev_get_priv(dev);
struct mii_dev *mdio_bus;
int ret;
priv->dev = dev;
/* These clock enables has to be moved to common location */
if (cpu_is_k2g())
writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
/* By default, select PA PLL clock as PA clock source */
#ifndef CONFIG_SOC_K2G
if (psc_enable_module(KS2_LPSC_PA))
return -EACCES;
#endif
if (psc_enable_module(KS2_LPSC_CPGMAC))
return -EACCES;
if (psc_enable_module(KS2_LPSC_CRYPTO))
return -EACCES;
if (cpu_is_k2e() || cpu_is_k2l())
pll_pa_clk_sel();
priv->net_rx_buffs.buff_ptr = rx_buffs;
priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS;
priv->net_rx_buffs.buff_len = RX_BUFF_LEN;
if (priv->slave_port == 1) {
/*
* Register MDIO bus for slave 0 only, other slave have
* to re-use the same
*/
mdio_bus = mdio_alloc();
if (!mdio_bus) {
error("MDIO alloc failed\n");
return -ENOMEM;
}
priv->mdio_bus = mdio_bus;
mdio_bus->read = keystone2_mdio_read;
mdio_bus->write = keystone2_mdio_write;
mdio_bus->reset = keystone2_mdio_reset;
mdio_bus->priv = priv->mdio_base;
sprintf(mdio_bus->name, "ethernet-mdio");
ret = mdio_register(mdio_bus);
if (ret) {
error("MDIO bus register failed\n");
return ret;
}
} else {
/* Get the MDIO bus from slave 0 device */
struct ks2_eth_priv *parent_priv;
parent_priv = dev_get_priv(dev->parent);
priv->mdio_bus = parent_priv->mdio_bus;
}
#ifndef CONFIG_SOC_K2G
keystone2_net_serdes_setup();
#endif
priv->netcp_pktdma = &netcp_pktdma;
if (priv->has_mdio) {
priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
dev, priv->phy_if);
phy_config(priv->phydev);
}
return 0;
}
