static int __init msm7x27x_cache_init(void) { int aux_ctrl = 0; int pctrl = 0; /* Way Size 010(0x2) 32KB */ aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | \ (0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | \ (0x1 << L2X0_AUX_CTRL_EVNT_MON_BUS_EN_SHIFT); if (cpu_is_msm8625()) { /* Way Size 011(0x3) 64KB */ aux_ctrl |= (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | \ (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | \ (0X1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | \ (0x1 << L2X0_AUX_CTRL_L2_FORCE_NWA_SHIFT); /* Write Prefetch Control settings */ pctrl = readl_relaxed(MSM_L2CC_BASE + L2X0_PREFETCH_CTRL); pctrl |= (0x3 << L2X0_PREFETCH_CTRL_OFFSET_SHIFT) | \ (0x1 << L2X0_PREFETCH_CTRL_WRAP8_INC_SHIFT) | \ (0x1 << L2X0_PREFETCH_CTRL_WRAP8_SHIFT); writel_relaxed(pctrl , MSM_L2CC_BASE + L2X0_PREFETCH_CTRL); } l2x0_init(MSM_L2CC_BASE, aux_ctrl, L2X0_AUX_CTRL_MASK); if (cpu_is_msm8625()) { pctrl = readl_relaxed(MSM_L2CC_BASE + L2X0_PREFETCH_CTRL); pr_info("Prfetch Ctrl: 0x%08x\n", pctrl); } return 0; }
int __init msm7x2x_misc_init(void) { if (machine_is_msm8625_rumi3()) { msm_clock_init(&msm8625_dummy_clock_init_data); msm_cpr_init(); return 0; } msm_clock_init(&msm7x27a_clock_init_data); if (cpu_is_msm7x27aa() || cpu_is_msm7x25ab()) platform_device_register(&msm7x27aa_device_acpuclk); else if (cpu_is_msm8625()) { if (msm8625_cpu_id() == MSM8625) platform_device_register(&msm7x27aa_device_acpuclk); else if (msm8625_cpu_id() == MSM8625A) platform_device_register(&msm8625_device_acpuclk); else if (msm8625_cpu_id() == MSM8625AB) platform_device_register(&msm8625ab_device_acpuclk); } else { platform_device_register(&msm7x27a_device_acpuclk); } if (cpu_is_msm8625() && (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2)) msm_cpr_init(); return 0; }
/* * Power collapse the Apps processor without involving Modem. * * Return value: * 0: success */ static int __ref msm_pm_power_collapse_standalone(bool from_idle) { int collapsed = 0; int ret; void *entry; MSM_PM_DPRINTK(MSM_PM_DEBUG_SUSPEND|MSM_PM_DEBUG_POWER_COLLAPSE, KERN_INFO, "%s()\n", __func__); ret = msm_spm_set_low_power_mode(MSM_SPM_MODE_POWER_COLLAPSE, false); WARN_ON(ret); entry = (!smp_processor_id() || from_idle) ? msm_pm_collapse_exit : msm_secondary_startup; msm_pm_boot_config_before_pc(smp_processor_id(), virt_to_phys(entry)); #ifdef CONFIG_VFP vfp_pm_suspend(); #endif #ifdef CONFIG_CACHE_L2X0 if (!cpu_is_msm8625()) l2cc_suspend(); #endif collapsed = msm_pm_collapse(); #ifdef CONFIG_CACHE_L2X0 if (!cpu_is_msm8625()) l2cc_resume(); #endif msm_pm_boot_config_after_pc(smp_processor_id()); if (collapsed) { #ifdef CONFIG_VFP vfp_pm_resume(); #endif cpu_init(); local_fiq_enable(); } MSM_PM_DPRINTK(MSM_PM_DEBUG_SUSPEND | MSM_PM_DEBUG_POWER_COLLAPSE, KERN_INFO, "%s(): msm_pm_collapse returned %d\n", __func__, collapsed); ret = msm_spm_set_low_power_mode(MSM_SPM_MODE_CLOCK_GATING, false); WARN_ON(ret); return !collapsed; }
static int __init msm_setup_fiq_handler(void) { int i, ret = 0; spin_lock_init(&msm_fiq_lock); claim_fiq(&msm7k_fh); set_fiq_handler(&msm7k_fiq_start, msm7k_fiq_length); for_each_possible_cpu(i) { msm7k_fiq_stack[i] = (void *)__get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER); if (msm7k_fiq_stack[i] == NULL) break; } if (i != nr_cpumask_bits) { pr_err("FIQ STACK SETUP IS NOT SUCCESSFUL\n"); for (i = 0; i < nr_cpumask_bits && msm7k_fiq_stack[i] != NULL; i++) free_pages((unsigned long)msm7k_fiq_stack[i], THREAD_SIZE_ORDER); return -ENOMEM; } fiq_set_type(msm_fiq_no, IRQF_TRIGGER_RISING); if (cpu_is_msm8625() || cpu_is_msm8625q()) gic_set_irq_secure(msm_fiq_no); else msm_fiq_select(msm_fiq_no); enable_irq(msm_fiq_no); pr_info("%s : MSM FIQ handler setup--done\n", __func__); return ret; }
void msm7k_fiq_handler(void) { struct pt_regs ctx_regs; static cpumask_t fiq_cpu_mask; int this_cpu; unsigned long msm_fiq_flags; spin_lock_irqsave(&msm_fiq_lock, msm_fiq_flags); this_cpu = smp_processor_id(); pr_info("%s: Fiq is received on CPU%d\n", __func__, this_cpu); fiq_counter += 1; ctx_regs.ARM_pc = msm_dump_cpu_ctx[this_cpu].fiq_r14; ctx_regs.ARM_lr = msm_dump_cpu_ctx[this_cpu].svc_r14; ctx_regs.ARM_sp = msm_dump_cpu_ctx[this_cpu].svc_r13; ctx_regs.ARM_fp = msm_dump_cpu_ctx[this_cpu].usr_r11; unwind_backtrace(&ctx_regs, current); if (fiq_counter == 1 && (cpu_is_msm8625() || cpu_is_msm8625q())) { cpumask_copy(&fiq_cpu_mask, cpu_online_mask); cpu_clear(this_cpu, fiq_cpu_mask); gic_raise_secure_softirq(&fiq_cpu_mask, GIC_SECURE_SOFT_IRQ); } flush_cache_all(); outer_flush_all(); spin_unlock_irqrestore(&msm_fiq_lock, msm_fiq_flags); return; }
void __init msm_pm_register_cpr_ops(void) { /* CPR presents on revision >= v2.0 chipsets */ if (cpu_is_msm8625() && SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) msm_pm_set_cpr_ops(&msm8625_pm_cpr_ops); }
static void __init msm7x2x_init(void) { msm7x2x_misc_init(); /* Initialize regulators first so that other devices can use them */ msm7x27a_init_regulators(); msm_adsp_add_pdev(); if (cpu_is_msm8625()) msm8625_device_i2c_init(); else msm7x27a_device_i2c_init(); msm7x27a_init_ebi2(); msm7x27a_uartdm_config(); msm7x27a_otg_gadget(); msm7x27a_cfg_smsc911x(); msm7x27a_add_footswitch_devices(); msm7x27a_add_platform_devices(); /* Ensure ar6000pm device is registered before MMC/SDC */ msm7x27a_init_ar6000pm(); msm7627a_init_mmc(); msm_fb_add_devices(); msm7x2x_init_host(); msm7x27a_pm_init(); register_i2c_devices(); msm7627a_bt_power_init(); msm7627a_camera_init(); msm7627a_add_io_devices(); /*7x25a kgsl initializations*/ msm7x25a_kgsl_3d0_init(); /*8x25 kgsl initializations*/ msm8x25_kgsl_3d0_init(); }
static void __init ft5x06_touchpad_setup(void) { int rc; if (machine_is_msm8625q_skud()) { if (cpu_is_msm8625()) { ft5x06_platformdata.irq_gpio = FT5X06_IRQ_GPIO_QPR_SKUD_PRIM; ft5x06_platformdata.reset_gpio = FT5X06_RESET_GPIO_QPR_SKUD_PRIM; ft5x06_platformdata.x_max = 480; ft5x06_platformdata.y_max = 854; ft5x06_device_info[0].irq = MSM_GPIO_TO_INT(FT5X06_IRQ_GPIO_QPR_SKUD_PRIM); } else { ft5x06_platformdata.irq_gpio = FT5X06_IRQ_GPIO_QPR_SKUD; ft5x06_platformdata.reset_gpio = FT5X06_RESET_GPIO_QPR_SKUD; ft5x06_platformdata.x_max = 480; ft5x06_platformdata.y_max = 854; ft5x06_device_info[0].irq = MSM_GPIO_TO_INT(FT5X06_IRQ_GPIO_QPR_SKUD); } } else if(machine_is_msm8625q_evbd()) { ft5x06_platformdata.irq_gpio = FT5X16_IRQ_GPIO_EVBD; ft5x06_platformdata.reset_gpio = FT5X06_RESET_GPIO; ft5x06_platformdata.x_max = 540; ft5x06_platformdata.y_max = 960; ft5x06_device_info[0].irq = MSM_GPIO_TO_INT(FT5X16_IRQ_GPIO_EVBD); } else if (machine_is_msm8625q_skue()) { ft5x06_platformdata.irq_gpio = FT5X06_IRQ_GPIO_QPR_SKUE; ft5x06_platformdata.reset_gpio = FT5X06_RESET_GPIO_QPR_SKUE; ft5x06_platformdata.x_max = 540; ft5x06_platformdata.y_max = 960; ft5x06_device_info[0].irq = MSM_GPIO_TO_INT(FT5X06_IRQ_GPIO_QPR_SKUE); } rc = gpio_tlmm_config(GPIO_CFG(ft5x06_platformdata.irq_gpio, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), GPIO_CFG_ENABLE); if (rc) pr_err("%s: gpio_tlmm_config for %d failed\n", __func__, ft5x06_platformdata.irq_gpio); rc = gpio_tlmm_config(GPIO_CFG(ft5x06_platformdata.reset_gpio, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_8MA), GPIO_CFG_ENABLE); if (rc) pr_err("%s: gpio_tlmm_config for %d failed\n", __func__, ft5x06_platformdata.reset_gpio); ft5x06_virtual_key_properties_kobj = kobject_create_and_add("board_properties", NULL); if (ft5x06_virtual_key_properties_kobj) rc = sysfs_create_group(ft5x06_virtual_key_properties_kobj, &ft5x06_virtual_key_properties_attr_group); if (!ft5x06_virtual_key_properties_kobj || rc) pr_err("%s: failed to create board_properties\n", __func__); i2c_register_board_info(MSM_GSBI1_QUP_I2C_BUS_ID, ft5x06_device_info, ARRAY_SIZE(ft5x06_device_info)); }
/* * Bring the Apps processor to SWFI. * * Return value: * -EIO: could not ramp Apps processor clock * 0: success */ static int msm_pm_swfi(bool ramp_acpu) { unsigned long saved_acpuclk_rate = 0; if (ramp_acpu) { saved_acpuclk_rate = acpuclk_wait_for_irq(); MSM_PM_DPRINTK(MSM_PM_DEBUG_CLOCK, KERN_INFO, "%s(): change clock rate (old rate = %lu)\n", __func__, saved_acpuclk_rate); if (!saved_acpuclk_rate) return -EIO; } if (!cpu_is_msm8625()) msm_pm_config_hw_before_swfi(); msm_arch_idle(); if (ramp_acpu) { MSM_PM_DPRINTK(MSM_PM_DEBUG_CLOCK, KERN_INFO, "%s(): restore clock rate to %lu\n", __func__, saved_acpuclk_rate); if (acpuclk_set_rate(smp_processor_id(), saved_acpuclk_rate, SETRATE_SWFI) < 0) printk(KERN_ERR "%s(): failed to restore clock rate(%lu)\n", __func__, saved_acpuclk_rate); } return 0; }
static void __init msm7x2x_init(void) { msm7x2x_misc_init(); /* Initialize regulators first so that other devices can use them */ msm7x27a_init_regulators(); msm_adsp_add_pdev(); if (cpu_is_msm8625()) msm8625_device_i2c_init(); else msm7x27a_device_i2c_init(); msm7x27a_init_ebi2(); msm7x27a_uartdm_config(); msm7x27a_otg_gadget(); /* LGE_CHANGE_: 2012/11/2 [email protected] U0 Flash Porting */ #ifndef CONFIG_MACH_LGE msm7x27a_cfg_smsc911x(); #endif /* LGE_CHANGE_E: 2012/11/2 [email protected] U0 Flash Porting */ msm7x27a_add_footswitch_devices(); msm7x27a_add_platform_devices(); /* Ensure ar6000pm device is registered before MMC/SDC */ msm7x27a_init_ar6000pm(); msm7627a_init_mmc(); msm_fb_add_devices(); msm7x2x_init_host(); msm7x27a_pm_init(); #if defined(CONFIG_I2C) && defined(CONFIG_GPIO_SX150X) register_i2c_devices(); #endif #if defined(CONFIG_BT) && defined(CONFIG_MARIMBA_CORE) msm7627a_bt_power_init(); #endif #ifdef CONFIG_MSM7X27A_AUDIO lge_add_sound_devices(); #endif /* LGE_CHANGE_S: 2012/11/2 [email protected] U0 Flash Porting */ msm7627a_camera_init(); /* LGE_CHANGE_E: 2012/11/2 [email protected] U0 Flash Porting */ msm7627a_add_io_devices(); /*7x25a kgsl initializations*/ msm7x25a_kgsl_3d0_init(); /*8x25 kgsl initializations*/ msm8x25_kgsl_3d0_init(); lge_add_gpio_i2c_devices(); /* 2012-10-25 [email protected] Boot Mode Check [START] */ #ifdef CONFIG_LGE_POWER_ON_STATUS_PATCH lge_board_pwr_on_status(); #endif #ifdef CONFIG_LGE_BOOT_MODE lge_add_boot_mode_devices(); #endif /* 2012-10-25 [email protected] Boot Mode Check [END] */ #if defined(CONFIG_ANDROID_RAM_CONSOLE) && defined(CONFIG_LGE_HANDLE_PANIC) lge_add_panic_handler_devices(); #endif lge_add_pm_devices(); }
/* * Clear hardware registers after Apps powers up. */ static void msm_pm_config_hw_after_power_up(void) { if (cpu_is_msm7x30() || cpu_is_msm8x55()) { __raw_writel(0, APPS_SECOP); mb(); __raw_writel(0, APPS_PWRDOWN); mb(); msm_spm_reinit(); } else if (cpu_is_msm8625()) { __raw_writel(0, APPS_PWRDOWN); mb(); if (power_collapsed) { /* * enable the SCU while coming out of power * collapse. */ scu_enable(MSM_SCU_BASE); /* * Program the top csr to put the core1 into GDFS. */ configure_top_csr(); } } else { __raw_writel(0, APPS_PWRDOWN); mb(); __raw_writel(0, APPS_CLK_SLEEP_EN); mb(); } }
static int msm7627a_init_gpio(void) { if (cpu_is_msm8625()) platform_device_register(&msm8625_device_gpio); else platform_device_register(&msm_device_gpio); return 0; }
void __init msm_pm_register_irqs(void) { if (cpu_is_msm8625()) msm_pm_set_irq_extns(&msm8625_pm_irq_calls); else msm_pm_set_irq_extns(&msm7x27a_pm_irq_calls); }
void __init msm_fb_register_device(char *name, void *data) { if (!strncmp(name, "mdp", 3)) { if (cpu_is_msm8625()) msm_register_device(&msm8625_mdp_device, data); else msm_register_device(&msm_mdp_device, data); } else if (!strncmp(name, "mipi_dsi", 8)) { if (cpu_is_msm8625()) msm_register_device(&msm8625_mipi_dsi_device, data); else msm_register_device(&msm_mipi_dsi_device, data); } else if (!strncmp(name, "lcdc", 4)) { msm_register_device(&msm_lcdc_device, data); } else { printk(KERN_ERR "%s: unknown device! %s\n", __func__, name); } }
static void __init qrd7627a_uart1dm_config(void) { msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(UART1DM_RX_GPIO); if (cpu_is_msm8625()) msm8625_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata; else msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata; }
static void __init msm7x27a_uartdm_config(void) { msm7x27a_cfg_uart2dm_serial(); msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(UART1DM_RX_GPIO); if (cpu_is_msm8625() || cpu_is_msm8625q()) msm8625_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata; else msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata; }
static int __init init7k_fiq(void) { if (!cpu_is_msm8625() && !cpu_is_msm8625q()) return 0; if (msm_setup_fiq_handler()) pr_err("MSM7K FIQ INIT FAILED\n"); return 0; }
void __init msm8x25_kgsl_3d0_init(void) { if (cpu_is_msm8625()) { kgsl_3d0_pdata.idle_timeout = HZ/5; kgsl_3d0_pdata.strtstp_sleepwake = false; /* 8x25 supports a higher GPU frequency */ kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 320000000; kgsl_3d0_pdata.pwrlevel[0].bus_freq = 200000000; } }
static int __init init7k_fiq(void) { if (cpu_is_msm8625() || cpu_is_msm8625q()) msm_fiq_no = MSM8625_INT_A9_M2A_2; else msm_fiq_no = INT_A9_M2A_2; if (msm_setup_fiq_handler()) pr_err("MSM FIQ INIT FAILED\n"); return 0; }
int msm_add_host(unsigned int host, struct msm_usb_host_platform_data *plat) { struct platform_device *pdev; if (cpu_is_msm8625()) pdev = msm8625_host_devices[host]; else pdev = msm_host_devices[host]; if (!pdev) return -ENODEV; pdev->dev.platform_data = plat; return platform_device_register(pdev); }
static void __init msm_pm_init(void) { if (!cpu_is_msm8625()) { msm_pm_set_platform_data(msm7627a_pm_data, ARRAY_SIZE(msm7627a_pm_data)); BUG_ON(msm_pm_boot_init(&msm_pm_boot_pdata)); } else { msm_pm_set_platform_data(msm8625_pm_data, ARRAY_SIZE(msm8625_pm_data)); BUG_ON(msm_pm_boot_init(&msm_pm_8625_boot_pdata)); msm8x25_spm_device_init(); } }
static void __init msm7x27a_uartdm_config(void) { msm7x27a_cfg_uart2dm_serial(); /* set RX intterupt for WCN2243 */ if(BT_WCN2243 == get_hw_bt_device_model()) { msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(UART1DM_RX_GPIO); if (cpu_is_msm8625()) msm8625_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata; else msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata; } }
void __init msm8x25_kgsl_3d0_init(void) { if (cpu_is_msm8625()) { kgsl_3d0_pdata.idle_timeout = HZ/5; kgsl_3d0_pdata.strtstp_sleepwake = false; if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) /* 8x25 v2.0 & above supports a higher GPU frequency */ kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 320000000; else kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 300000000; kgsl_3d0_pdata.pwrlevel[0].bus_freq = 200000000; } }
int __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat) { struct platform_device *pdev; if (controller < 1 || controller > 4) return -EINVAL; if (cpu_is_msm8625()) pdev = msm8625_sdcc_devices[controller-1]; else pdev = msm_sdcc_devices[controller-1]; pdev->dev.platform_data = plat; return platform_device_register(pdev); }
static void __init msm_qrd_init(void) { msm7x2x_misc_init(); msm7627a_init_regulators(); msmqrd_adsp_add_pdev(); if (cpu_is_msm8625() || cpu_is_msm8625q()) msm8625_device_i2c_init(); else msm7627a_device_i2c_init(); /* uart1dm*/ qrd7627a_uart1dm_config(); /*OTG gadget*/ qrd7627a_otg_gadget(); msm_add_footswitch_devices(); add_platform_devices(); /* Ensure ar6000pm device is registered before MMC/SDC */ #if defined(CONFIG_BT) && defined(CONFIG_MARIMBA_CORE) msm_qrd_init_ar6000pm(); #endif msm7627a_init_mmc(); #ifdef CONFIG_USB_EHCI_MSM_72K msm7627a_init_host(); #endif msm_pm_init(); msm_pm_register_irqs(); msm_fb_add_devices(); if (machine_is_msm8625q_evbd() || machine_is_msm8625q_skud() || machine_is_msm8625q_skue()) i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info)); #if defined(CONFIG_BT) && defined(CONFIG_MARIMBA_CORE) msm7627a_bt_power_init(); #endif msm7627a_sensor_init(); msm7627a_camera_init(); qrd7627a_add_io_devices(); msm7x25a_kgsl_3d0_init(); msm8x25_kgsl_3d0_init(); }
static void __init qrd7627a_otg_gadget(void) { if (cpu_is_msm8625()) { msm_otg_pdata.swfi_latency = msm8625_pm_data [MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT].latency; msm8625_device_otg.dev.platform_data = &msm_otg_pdata; msm8625_device_gadget_peripheral.dev.platform_data = &msm_gadget_pdata; } else { msm_otg_pdata.swfi_latency = msm7627a_pm_data [MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT].latency; msm_device_otg.dev.platform_data = &msm_otg_pdata; msm_device_gadget_peripheral.dev.platform_data = &msm_gadget_pdata; } }
static int __init msm_pmu_init(void) { #if defined(CONFIG_ARCH_MSM_KRAITMP) || defined(CONFIG_ARCH_MSM_SCORPIONMP) \ || (defined(CONFIG_ARCH_MSM_CORTEX_A5) && !defined(CONFIG_MSM_VIC)) cpu_pmu_device.dev.platform_data = &multicore_data; #endif #ifdef CONFIG_ARCH_MSM8625 if (cpu_is_msm8625() || cpu_is_msm8625q()) { pmu_devices[0] = &msm8625_cpu_pmu_device; pmu_devices[1] = &msm8625_l2_pmu_device; msm8625_cpu_pmu_device.dev.platform_data = &multicore_data; } #endif return platform_add_devices(pmu_devices, ARRAY_SIZE(pmu_devices)); }
static void __init msm7x27a_add_platform_devices(void) { #ifdef CONFIG_HUAWEI_KERNEL if (machine_is_msm8625_surf() || machine_is_msm8625_ffa() || cpu_is_msm8625()) #else if (machine_is_msm8625_surf() || machine_is_msm8625_ffa()) #endif { platform_add_devices(msm8625_surf_devices, ARRAY_SIZE(msm8625_surf_devices)); } else { platform_add_devices(msm7627a_surf_ffa_devices, ARRAY_SIZE(msm7627a_surf_ffa_devices)); } platform_add_devices(common_devices, ARRAY_SIZE(common_devices)); }
static void __init msm_qrd_init(void) { msm7x2x_misc_init(); msm7627a_init_regulators(); msmqrd_adsp_add_pdev(); if (cpu_is_msm8625()) msm8625_device_i2c_init(); else msm7627a_device_i2c_init(); /* uart1dm*/ qrd7627a_uart1dm_config(); /*OTG gadget*/ qrd7627a_otg_gadget(); msm_add_footswitch_devices(); add_platform_devices(); /* Ensure ar6000pm device is registered before MMC/SDC */ msm_qrd_init_ar6000pm(); msm7627a_init_mmc(); #ifdef CONFIG_USB_EHCI_MSM_72K msm7627a_init_host(); #endif msm_pm_init(); msm_pm_register_irqs(); msm_fb_add_devices(); #if defined(CONFIG_BT) && defined(CONFIG_MARIMBA_CORE) /* qcomm QRD phone concerned not need by hw product*/ //msm7627a_bt_power_init(); #endif msm7627a_camera_init(); qrd7627a_add_io_devices(); msm7x25a_kgsl_3d0_init(); msm8x25_kgsl_3d0_init(); }
int __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat) { struct platform_device *pdev; if (controller < 1 || controller > 4) return -EINVAL; if (machine_is_msm8625_skua() || machine_is_msm8625_evb() || machine_is_msm8625_qrd5() || machine_is_msm8625_skub()) { msm8625_device_sdc3.resource[2].start = DMOV_NAND_CHAN; msm8625_device_sdc3.resource[2].end = DMOV_NAND_CHAN; } if (cpu_is_msm8625()) pdev = msm8625_sdcc_devices[controller-1]; else pdev = msm_sdcc_devices[controller-1]; pdev->dev.platform_data = plat; return platform_device_register(pdev); }