unsigned int has_emac()
{
return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36();
}
unsigned int has_gmac()
{
return !cpu_is_sama5d31();
}
void at91_add_device_eth(int id, struct macb_platform_data *data)
{
if (!data)
return;
switch (id) {
case 0:
if (cpu_is_sama5d31()) {
pr_warn("AT91: no gmac on sama5d31\n");
return;
}
at91_set_A_periph(AT91_PIN_PB16, 0); /* GMDC */
at91_set_A_periph(AT91_PIN_PB17, 0); /* GMDIO */
at91_set_A_periph(AT91_PIN_PB9, 0); /* GTXEN */
at91_set_A_periph(AT91_PIN_PB11, 0); /* GRXCK */
at91_set_A_periph(AT91_PIN_PB13, 0); /* GRXER */
switch (data->phy_interface) {
case PHY_INTERFACE_MODE_GMII:
at91_set_B_periph(AT91_PIN_PB19, 0); /* GTX4 */
at91_set_B_periph(AT91_PIN_PB20, 0); /* GTX5 */
at91_set_B_periph(AT91_PIN_PB21, 0); /* GTX6 */
at91_set_B_periph(AT91_PIN_PB22, 0); /* GTX7 */
at91_set_B_periph(AT91_PIN_PB23, 0); /* GRX4 */
at91_set_B_periph(AT91_PIN_PB24, 0); /* GRX5 */
at91_set_B_periph(AT91_PIN_PB25, 0); /* GRX6 */
at91_set_B_periph(AT91_PIN_PB26, 0); /* GRX7 */
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_RGMII:
at91_set_A_periph(AT91_PIN_PB0, 0); /* GTX0 */
at91_set_A_periph(AT91_PIN_PB1, 0); /* GTX1 */
at91_set_A_periph(AT91_PIN_PB2, 0); /* GTX2 */
at91_set_A_periph(AT91_PIN_PB3, 0); /* GTX3 */
at91_set_A_periph(AT91_PIN_PB4, 0); /* GRX0 */
at91_set_A_periph(AT91_PIN_PB5, 0); /* GRX1 */
at91_set_A_periph(AT91_PIN_PB6, 0); /* GRX2 */
at91_set_A_periph(AT91_PIN_PB7, 0); /* GRX3 */
break;
default:
return;
}
switch (data->phy_interface) {
case PHY_INTERFACE_MODE_MII:
at91_set_A_periph(AT91_PIN_PB8, 0); /* GTXCK */
at91_set_A_periph(AT91_PIN_PB10, 0); /* GTXER */
at91_set_A_periph(AT91_PIN_PB12, 0); /* GRXDV */
at91_set_A_periph(AT91_PIN_PB14, 0); /* GCRS */
at91_set_A_periph(AT91_PIN_PB15, 0); /* GCOL */
break;
case PHY_INTERFACE_MODE_RGMII:
at91_set_A_periph(AT91_PIN_PB8, 0); /* GTXCK */
at91_set_A_periph(AT91_PIN_PB18, 0); /* G125CK */
break;
case PHY_INTERFACE_MODE_GMII:
at91_set_A_periph(AT91_PIN_PB10, 0); /* GTXER */
at91_set_A_periph(AT91_PIN_PB12, 0); /* GRXDV */
at91_set_A_periph(AT91_PIN_PB14, 0); /* GCRS */
at91_set_A_periph(AT91_PIN_PB15, 0); /* GCOL */
at91_set_A_periph(AT91_PIN_PB27, 0); /* G125CK0 */
break;
default:
return;
}
add_generic_device("macb", id, NULL, SAMA5D3_BASE_GMAC, SZ_16K,
IORESOURCE_MEM, data);
break;
case 1:
if (cpu_is_sama5d33() || cpu_is_sama5d34()) {
pr_warn("AT91: no macb on sama5d33/d34\n");
return;
}
if (data->phy_interface != PHY_INTERFACE_MODE_RMII) {
pr_warn("AT91: Only RMII available on interfacr macb%d.\n", id);
return;
}
at91_set_A_periph(AT91_PIN_PC7, 0); /* ETXCK_EREFCK */
at91_set_A_periph(AT91_PIN_PC5, 0); /* ERXDV */
at91_set_A_periph(AT91_PIN_PC2, 0); /* ERX0 */
at91_set_A_periph(AT91_PIN_PC3, 0); /* ERX1 */
at91_set_A_periph(AT91_PIN_PC6, 0); /* ERXER */
at91_set_A_periph(AT91_PIN_PC4, 0); /* ETXEN */
at91_set_A_periph(AT91_PIN_PC0, 0); /* ETX0 */
at91_set_A_periph(AT91_PIN_PC1, 0); /* ETX1 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PC8, 0); /* EMDC */
add_generic_device("macb", id, NULL, SAMA5D3_BASE_EMAC, SZ_16K,
IORESOURCE_MEM, data);
break;
default:
return;
}
}
