static INLINE void mips_advance_pc( void )
{
THISPC = NEXTPC;
THISOP = mcc.nextop;
NEXTPC += 4;
mcc.nextop = cpu_readop32( NEXTPC );
}
int mips_execute( int cycles )
{
mips_ICount = cycles;
do
{
THISOP = cpu_readop32(THISPC);
THISPC += 4;
switch( INS_OP( THISOP ) )
{
case OP_SPECIAL:
switch( INS_FUNCT( THISOP ) )
{
case FUNCT_SLL:
if( INS_RD( THISOP ) != 0 )
{
RD = RT << SHAMT;
}
mips_advance_pc();
break;
case FUNCT_SRL:
if( INS_RD( THISOP ) != 0 )
{
RD = RT >> SHAMT;
}
mips_advance_pc();
break;
case FUNCT_SRA:
if( INS_RD( THISOP ) != 0 )
{
RD = (INT32) RT >> SHAMT;
}
mips_advance_pc();
break;
case FUNCT_SLLV:
if( INS_RD( THISOP ) != 0 )
{
RD = RT << ( RS & 31 );
}
mips_advance_pc();
break;
case FUNCT_SRLV:
if( INS_RD( THISOP ) != 0 )
{
RD = RT >> ( RS & 31 );
}
mips_advance_pc();
break;
case FUNCT_SRAV:
if( INS_RD( THISOP ) != 0 )
{
RD = (INT32) RT >> ( RS & 31 );
}
static INLINE void mips_set_nextpc( UINT32 adr )
{
THISPC = NEXTPC;
THISOP = mcc.nextop;
if( ( adr & ( ( ( CP0R( CP0_SR ) & 0x02 ) << 31 ) | 3 ) ) != 0 )
{
CP0R( CP0_BADVADDR ) = adr;
mips_exception( EXC_ADEL );
}
else
{
change_pc32( adr );
NEXTPC = adr;
mcc.nextop = cpu_readop32( NEXTPC );
}
}
static int arm_execute( int cycles )
{
UINT32 pc;
UINT32 insn;
arm_icount = cycles;
do
{
CALL_DEBUGGER(R15);
/* load instruction */
pc = R15;
insn = cpu_readop32( pc & ADDRESS_MASK );
switch (insn >> INSN_COND_SHIFT)
{
case COND_EQ:
if (Z_IS_CLEAR(pc)) goto L_Next;
break;
case COND_NE:
if (Z_IS_SET(pc)) goto L_Next;
break;
case COND_CS:
if (C_IS_CLEAR(pc)) goto L_Next;
break;
case COND_CC:
if (C_IS_SET(pc)) goto L_Next;
break;
case COND_MI:
if (N_IS_CLEAR(pc)) goto L_Next;
break;
case COND_PL:
if (N_IS_SET(pc)) goto L_Next;
break;
case COND_VS:
if (V_IS_CLEAR(pc)) goto L_Next;
break;
case COND_VC:
if (V_IS_SET(pc)) goto L_Next;
break;
case COND_HI:
if (C_IS_CLEAR(pc) || Z_IS_SET(pc)) goto L_Next;
break;
case COND_LS:
if (C_IS_SET(pc) && Z_IS_CLEAR(pc)) goto L_Next;
break;
case COND_GE:
if (!(pc & N_MASK) != !(pc & V_MASK)) goto L_Next; /* Use x ^ (x >> ...) method */
break;
case COND_LT:
if (!(pc & N_MASK) == !(pc & V_MASK)) goto L_Next;
break;
case COND_GT:
if (Z_IS_SET(pc) || (!(pc & N_MASK) != !(pc & V_MASK))) goto L_Next;
break;
case COND_LE:
if (Z_IS_CLEAR(pc) && (!(pc & N_MASK) == !(pc & V_MASK))) goto L_Next;
break;
case COND_NV:
goto L_Next;
}
/* Condition satisfied, so decode the instruction */
if ((insn & 0x0fc000f0u) == 0x00000090u) /* Multiplication */
{
HandleMul(insn);
R15 += 4;
}
else if (!(insn & 0x0c000000u)) /* Data processing */
{
HandleALU(insn);
}
else if ((insn & 0x0c000000u) == 0x04000000u) /* Single data access */
{
HandleMemSingle(insn);
R15 += 4;
}
else if ((insn & 0x0e000000u) == 0x08000000u ) /* Block data access */
{
HandleMemBlock(insn);
R15 += 4;
}
else if ((insn & 0x0e000000u) == 0x0a000000u) /* Branch */
{
HandleBranch(insn);
}
else if ((insn & 0x0f000000u) == 0x0e000000u) /* Coprocessor */
{
HandleCoPro(insn);
R15 += 4;
}
else if ((insn & 0x0f000000u) == 0x0f000000u) /* Software interrupt */
{
pc=R15+4;
R15 = eARM_MODE_SVC; /* Set SVC mode so PC is saved to correct R14 bank */
SetRegister( 14, pc ); /* save PC */
R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK);
change_pc(pc&ADDRESS_MASK);
arm_icount -= 2 * S_CYCLE + N_CYCLE;
}
else /* Undefined */
{
logerror("%08x: Undefined instruction\n",R15);
L_Next:
arm_icount -= S_CYCLE;
R15 += 4;
}
arm_check_irq_state();
} while( arm_icount > 0 );
return cycles - arm_icount;
} /* arm_execute */
unsigned DasmMIPS( char *buffer, UINT32 oldpc )
{
UINT32 pc, op;
pc = oldpc;
op = cpu_readop32( pc );
pc += 4;
sprintf( buffer, "dw $%08x", op );
switch( INS_OP( op ) )
{
case OP_SPECIAL:
switch( INS_FUNCT( op ) )
{
case FUNCT_SLL:
if( op == 0 )
{
/* the standard nop is "sll zero,zero,$0000" */
sprintf( buffer, "nop" );
}
else
{
sprintf( buffer, "sll %s,%s,$%02x", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], INS_SHAMT( op ) );
}
break;
case FUNCT_SRL:
sprintf( buffer, "srl %s,%s,$%02x", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], INS_SHAMT( op ) );
break;
case FUNCT_SRA:
sprintf( buffer, "sra %s,%s,$%02x", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], INS_SHAMT( op ) );
break;
case FUNCT_SLLV:
sprintf( buffer, "sllv %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ] );
break;
case FUNCT_SRLV:
sprintf( buffer, "srlv %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ] );
break;
case FUNCT_SRAV:
sprintf( buffer, "srav %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ] );
break;
case FUNCT_JR:
if( INS_RD( op ) == 0 )
{
sprintf( buffer, "jr %s", s_cpugenreg[ INS_RS( op ) ] );
}
break;
case FUNCT_JALR:
sprintf( buffer, "jalr %s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ] );
break;
case FUNCT_SYSCALL:
sprintf( buffer, "syscall $%05x", INS_CODE( op ) );
break;
case FUNCT_BREAK:
sprintf( buffer, "break $%05x", INS_CODE( op ) );
break;
case FUNCT_MFHI:
sprintf( buffer, "mfhi %s", s_cpugenreg[ INS_RD( op ) ] );
break;
case FUNCT_MTHI:
if( INS_RD( op ) == 0 )
{
sprintf( buffer, "mthi %s", s_cpugenreg[ INS_RS( op ) ] );
}
break;
case FUNCT_MFLO:
sprintf( buffer, "mflo %s", s_cpugenreg[ INS_RD( op ) ] );
break;
case FUNCT_MTLO:
if( INS_RD( op ) == 0 )
{
sprintf( buffer, "mtlo %s", s_cpugenreg[ INS_RS( op ) ] );
}
break;
case FUNCT_MULT:
if( INS_RD( op ) == 0 )
{
sprintf( buffer, "mult %s,%s", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
}
break;
case FUNCT_MULTU:
if( INS_RD( op ) == 0 )
{
sprintf( buffer, "multu %s,%s", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
}
break;
case FUNCT_DIV:
if( INS_RD( op ) == 0 )
{
sprintf( buffer, "div %s,%s", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
}
break;
case FUNCT_DIVU:
if( INS_RD( op ) == 0 )
{
sprintf( buffer, "divu %s,%s", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
}
break;
case FUNCT_ADD:
sprintf( buffer, "add %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_ADDU:
sprintf( buffer, "addu %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_SUB:
sprintf( buffer, "sub %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_SUBU:
sprintf( buffer, "subu %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_AND:
sprintf( buffer, "and %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_OR:
sprintf( buffer, "or %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_XOR:
sprintf( buffer, "xor %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_NOR:
sprintf( buffer, "nor %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_SLT:
sprintf( buffer, "slt %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_SLTU:
sprintf( buffer, "sltu %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
}
break;
case OP_REGIMM:
switch( INS_RT( op ) )
{
case RT_BLTZ:
sprintf( buffer, "bltz %s,$%08x", s_cpugenreg[ INS_RS( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
break;
case RT_BGEZ:
sprintf( buffer, "bgez %s,$%08x", s_cpugenreg[ INS_RS( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
break;
case RT_BLTZAL:
sprintf( buffer, "bltzal %s,$%08x", s_cpugenreg[ INS_RS( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
break;
case RT_BGEZAL:
sprintf( buffer, "bgezal %s,$%08x", s_cpugenreg[ INS_RS( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
break;
}
break;
case OP_J:
sprintf( buffer, "j $%08x", ( pc & 0xF0000000 ) + ( INS_TARGET( op ) << 2 ) );
break;
case OP_JAL:
sprintf( buffer, "jal $%08x", ( pc & 0xF0000000 ) + ( INS_TARGET( op ) << 2 ) );
break;
case OP_BEQ:
sprintf( buffer, "beq %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
break;
case OP_BNE:
sprintf( buffer, "bne %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
break;
case OP_BLEZ:
if( INS_RT( op ) == 0 )
{
sprintf( buffer, "blez %s,$%08x", s_cpugenreg[ INS_RS( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
}
break;
case OP_BGTZ:
if( INS_RT( op ) == 0 )
{
sprintf( buffer, "bgtz %s,$%08x", s_cpugenreg[ INS_RS( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
}
break;
case OP_ADDI:
sprintf( buffer, "addi %s,%s,%s", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ) );
break;
case OP_ADDIU:
sprintf( buffer, "addiu %s,%s,%s", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ) );
break;
case OP_SLTI:
sprintf( buffer, "slti %s,%s,%s", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ) );
break;
case OP_SLTIU:
sprintf( buffer, "sltiu %s,%s,%s", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ) );
break;
case OP_ANDI:
sprintf( buffer, "andi %s,%s,$%04x", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], INS_IMMEDIATE( op ) );
break;
case OP_ORI:
sprintf( buffer, "ori %s,%s,$%04x", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], INS_IMMEDIATE( op ) );
break;
case OP_XORI:
sprintf( buffer, "xori %s,%s,$%04x", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], INS_IMMEDIATE( op ) );
break;
case OP_LUI:
sprintf( buffer, "lui %s,$%04x", s_cpugenreg[ INS_RT( op ) ], INS_IMMEDIATE( op ) );
break;
case OP_COP0:
switch( INS_RS( op ) )
{
case RS_MFC:
sprintf( buffer, "mfc0 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp0genreg[ INS_RD( op ) ] );
break;
case RS_MTC:
sprintf( buffer, "mtc0 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp0genreg[ INS_RD( op ) ] );
break;
case RS_BC:
switch( INS_RT( op ) )
{
case RT_BCF:
sprintf( buffer, "bc0f $%08x", pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
break;
case RT_BCT:
sprintf( buffer, "bc0t $%08x", pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
break;
}
break;
default:
switch( INS_CO( op ) )
{
case 1:
sprintf( buffer, "cop0 $%07x", INS_COFUN( op ) );
switch( INS_CF( op ) )
{
case 1:
sprintf( buffer, "tlbr" );
break;
case 4:
sprintf( buffer, "tlbwi" );
break;
case 6:
sprintf( buffer, "tlbwr" );
break;
case 8:
sprintf( buffer, "tlbp" );
break;
case 16:
sprintf( buffer, "rfe" );
break;
}
break;
}
break;
}
break;
case OP_COP1:
switch( INS_RS( op ) )
{
case RS_MFC:
sprintf( buffer, "mfc1 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp1genreg[ INS_RD( op ) ] );
break;
case RS_CFC:
sprintf( buffer, "cfc1 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp1ctlreg[ INS_RD( op ) ] );
break;
case RS_MTC:
sprintf( buffer, "mtc1 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp1genreg[ INS_RD( op ) ] );
break;
case RS_CTC:
sprintf( buffer, "ctc1 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp1ctlreg[ INS_RD( op ) ] );
break;
case RS_BC:
switch( INS_RT( op ) )
{
case RT_BCF:
sprintf( buffer, "bc1f $%08x", pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
break;
case RT_BCT:
sprintf( buffer, "bc1t $%08x", pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
break;
}
break;
default:
switch( INS_CO( op ) )
{
case 1:
sprintf( buffer, "cop1 $%07x", INS_COFUN( op ) );
break;
}
break;
}
break;
case OP_COP2:
switch( INS_RS( op ) )
{
case RS_MFC:
sprintf( buffer, "mfc2 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp2genreg[ INS_RD( op ) ] );
break;
case RS_CFC:
sprintf( buffer, "cfc2 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp2ctlreg[ INS_RD( op ) ] );
break;
case RS_MTC:
sprintf( buffer, "mtc2 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp2genreg[ INS_RD( op ) ] );
break;
case RS_CTC:
sprintf( buffer, "ctc2 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp2ctlreg[ INS_RD( op ) ] );
break;
case RS_BC:
switch( INS_RT( op ) )
{
case RT_BCF:
sprintf( buffer, "bc2f $%08x", pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
break;
case RT_BCT:
sprintf( buffer, "bc2t $%08x", pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
break;
}
break;
default:
switch( INS_CO( op ) )
{
case 1:
sprintf( buffer, "cop2 $%07x", INS_COFUN( op ) );
switch( GTE_FUNCT( op ) )
{
case 0x01:
if( INS_CO( op ) == 0x0180001 )
{
sprintf( buffer, "rtps" );
}
break;
case 0x06:
if( INS_CO( op ) == 0x0400006 ||
INS_CO( op ) == 0x1400006 ||
INS_CO( op ) == 0x0155cc6 )
{
sprintf( buffer, "nclip" );
}
break;
case 0x0c:
if( GTE_OP( op ) == 0x17 )
{
sprintf( buffer, "op%s", s_gtesf[ GTE_SF( op ) ] );
}
break;
case 0x10:
if( INS_CO( op ) == 0x0780010 )
{
sprintf( buffer, "dpcs" );
}
break;
case 0x11:
if( INS_CO( op ) == 0x0980011 )
{
sprintf( buffer, "intpl" );
}
break;
case 0x12:
if( GTE_OP( op ) == 0x04 )
{
sprintf( buffer, "mvmva%s %s + %s * %s (lm=%s)",
s_gtesf[ GTE_SF( op ) ], s_gtecv[ GTE_CV( op ) ], s_gtemx[ GTE_MX( op ) ],
s_gtev[ GTE_V( op ) ], s_gtelm[ GTE_LM( op ) ] );
}
break;
case 0x13:
if( INS_CO( op ) == 0x0e80413 )
{
sprintf( buffer, "ncds" );
}
break;
case 0x14:
if( INS_CO( op ) == 0x1280414 )
{
sprintf( buffer, "cdp" );
}
break;
case 0x16:
if( INS_CO( op ) == 0x0f80416 )
{
sprintf( buffer, "ncdt" );
}
break;
case 0x1b:
if( INS_CO( op ) == 0x108041b )
{
sprintf( buffer, "nccs" );
}
break;
case 0x1c:
if( INS_CO( op ) == 0x138041c )
{
sprintf( buffer, "cc" );
}
break;
case 0x1e:
if( INS_CO( op ) == 0x0c8041e )
{
sprintf( buffer, "ncs" );
}
break;
case 0x20:
if( INS_CO( op ) == 0x0d80420 )
{
sprintf( buffer, "nct" );
}
break;
case 0x28:
if( GTE_OP( op ) == 0x0a && GTE_LM( op ) == 1 )
{
sprintf( buffer, "sqr%s", s_gtesf[ GTE_SF( op ) ] );
}
break;
case 0x29:
if( INS_CO( op ) == 0x0680029 )
{
sprintf( buffer, "dcpl" );
}
break;
case 0x2a:
if( INS_CO( op ) == 0x0f8002a )
{
sprintf( buffer, "dpct" );
}
break;
case 0x2d:
if( INS_CO( op ) == 0x158002d )
{
sprintf( buffer, "avsz3" );
}
break;
case 0x2e:
if( INS_CO( op ) == 0x168002e )
{
sprintf( buffer, "avsz4" );
}
break;
case 0x30:
if( INS_CO( op ) == 0x0280030 )
{
sprintf( buffer, "rtpt" );
}
break;
case 0x3d:
if( GTE_OP( op ) == 0x09 ||
GTE_OP( op ) == 0x19 )
{
sprintf( buffer, "gpf%s", s_gtesf[ GTE_SF( op ) ] );
}
break;
case 0x3e:
if( GTE_OP( op ) == 0x1a )
{
sprintf( buffer, "gpl%s", s_gtesf[ GTE_SF( op ) ] );
}
break;
case 0x3f:
if( INS_CO( op ) == 0x108043f ||
INS_CO( op ) == 0x118043f )
{
sprintf( buffer, "ncct" );
}
break;
}
}
break;
}
break;
case OP_LB:
sprintf( buffer, "lb %s,%s", s_cpugenreg[ INS_RT( op ) ], make_address( op ) );
break;
case OP_LH:
sprintf( buffer, "lh %s,%s", s_cpugenreg[ INS_RT( op ) ], make_address( op ) );
break;
case OP_LWL:
sprintf( buffer, "lwl %s,%s", s_cpugenreg[ INS_RT( op ) ], make_address( op ) );
break;
case OP_LW:
sprintf( buffer, "lw %s,%s", s_cpugenreg[ INS_RT( op ) ], make_address( op ) );
break;
case OP_LBU:
sprintf( buffer, "lbu %s,%s", s_cpugenreg[ INS_RT( op ) ], make_address( op ) );
break;
case OP_LHU:
sprintf( buffer, "lhu %s,%s", s_cpugenreg[ INS_RT( op ) ], make_address( op ) );
break;
case OP_LWR:
sprintf( buffer, "lwr %s,%s", s_cpugenreg[ INS_RT( op ) ], make_address( op ) );
break;
case OP_SB:
sprintf( buffer, "sb %s,%s", s_cpugenreg[ INS_RT( op ) ], make_address( op ) );
break;
case OP_SH:
sprintf( buffer, "sh %s,%s", s_cpugenreg[ INS_RT( op ) ], make_address( op ) );
break;
case OP_SWL:
sprintf( buffer, "swl %s,%s", s_cpugenreg[ INS_RT( op ) ], make_address( op ) );
break;
case OP_SW:
sprintf( buffer, "sw %s,%s", s_cpugenreg[ INS_RT( op ) ], make_address( op ) );
break;
case OP_SWR:
sprintf( buffer, "swr %s,%s", s_cpugenreg[ INS_RT( op ) ], make_address( op ) );
break;
case OP_LWC1:
sprintf( buffer, "lwc1 %s,%s", s_cp1genreg[ INS_RT( op ) ], make_address( op ) );
break;
case OP_LWC2:
sprintf( buffer, "lwc2 %s,%s", s_cp2genreg[ INS_RT( op ) ], make_address( op ) );
break;
case OP_SWC1:
sprintf( buffer, "swc1 %s,%s", s_cp1genreg[ INS_RT( op ) ], make_address( op ) );
break;
case OP_SWC2:
sprintf( buffer, "swc2 %s,%s", s_cp2genreg[ INS_RT( op ) ], make_address( op ) );
break;
}
return pc - oldpc;
}
