int sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length) { uint16 val; sim_cpu *cpu; cpu = STATE_CPU (sd, 0); val = *memory++; if (length == 2) val = (val << 8) | *memory; switch (rn) { case D_REGNUM: cpu_set_d (cpu, val); break; case A_REGNUM: cpu_set_a (cpu, val); return 1; case B_REGNUM: cpu_set_b (cpu, val); return 1; case X_REGNUM: cpu_set_x (cpu, val); break; case Y_REGNUM: cpu_set_y (cpu, val); break; case SP_REGNUM: cpu_set_sp (cpu, val); break; case PC_REGNUM: cpu_set_pc (cpu, val); break; case PSW_REGNUM: cpu_set_ccr (cpu, val); return 1; case PAGE_REGNUM: cpu_set_page (cpu, val); return 1; default: break; } return 2; }
static int m68hc11_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) { uint16 val; val = *memory++; if (length == 2) val = (val << 8) | *memory; switch (rn) { case D_REGNUM: cpu_set_d (cpu, val); break; case A_REGNUM: cpu_set_a (cpu, val); return 1; case B_REGNUM: cpu_set_b (cpu, val); return 1; case X_REGNUM: cpu_set_x (cpu, val); break; case Y_REGNUM: cpu_set_y (cpu, val); break; case SP_REGNUM: cpu_set_sp (cpu, val); break; case PC_REGNUM: cpu_set_pc (cpu, val); break; case PSW_REGNUM: cpu_set_ccr (cpu, val); return 1; case PAGE_REGNUM: cpu_set_page (cpu, val); return 1; default: break; } return 2; }