u8 csi_event_enable(u32 mask, u8 err_reg_no)
{
switch (err_reg_no) {
case 1:
return csi_core_write(MASK1, (~mask) & csi_core_read(MASK1));
case 2:
return csi_core_write(MASK2, (~mask) & csi_core_read(MASK2));
default:
return ERR_OUT_OF_BOUND;
}
}
static unsigned char csi_event_disable(unsigned int mask, unsigned char err_reg_no)
{
switch (err_reg_no)
{
case 1:
csi_core_write(MASK1, mask | csi_core_read(MASK1));
break;
case 2:
csi_core_write(MASK2, mask | csi_core_read(MASK2));
break;
default:
return ERR_OUT_OF_BOUND;
}
return 0;
}
u8 csi_core_write_part(csi_registers_t address, u32 data, u8 shift, u8 width)
{
u32 mask = (1 << width) - 1;
u32 temp = csi_core_read(address);
temp &= ~(mask << shift);
temp |= (data & mask) << shift;
return csi_core_write(address, temp);
}
static unsigned char csi_core_write_part(unsigned int address, unsigned int data, unsigned char shift, unsigned char width)
{
unsigned int mask = (1 << width) - 1;
unsigned int temp = csi_core_read(address);
temp &= ~(mask << shift);
temp |= (data & mask) << shift;
csi_core_write(address, temp);
return 0;
}
static void mipi_csih_dphy_test_data_in(unsigned char test_data)
{
csi_core_write(PHY_TST_CTRL1, test_data);
}
