/*
* General outline: remap really low stuff [eventually] to SuperIO,
* stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
* is mapped through the PCI IO window. Stuff with high bits (PXSEG)
* should be way beyond the window, and is used w/o translation for
* compatibility.
*/
u8 landisk_inb(unsigned long port)
{
if (PXSEG(port))
return ctrl_inb(port);
else if (is_pci_ioaddr(port))
return ctrl_inb(pci_ioaddr(port));
return ctrl_inw(port2adr(port)) & 0xff;
}
void __init ec3104_kbd_init_hw(void)
{
ec3104_keyb.last_msr = ctrl_inb(EC3104_SER4_MSR);
ec3104_keyb.cached_mcr = ctrl_inb(EC3104_SER4_MCR);
ec3104_keyb_clear_state();
/* Ok, finally allocate the IRQ, and off we go.. */
request_irq(EC3104_IRQ_SER4, ec3104_keyb_interrupt, 0, "keyboard", NULL);
}
/*
* General outline: remap really low stuff [eventually] to SuperIO,
* stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
* is mapped through the PCI IO window. Stuff with high bits (PXSEG)
* should be way beyond the window, and is used w/o translation for
* compatibility.
*/
unsigned char hs7751rvoip_inb(unsigned long port)
{
if (PXSEG(port))
return ctrl_inb(port);
else if (codec_port(port))
return ctrl_inb(CODEC_IOMAP(port));
else if (is_pci_ioaddr(port) || shifted_port(port))
return ctrl_inb(pci_ioaddr(port));
else
return ctrl_inw(port2adr(port)) & 0xff;
}
int platform_timer_setup(irqreturn_t (*timer_int)(int, void *, struct pt_regs *))
{
*(unsigned short *)GRA= H8300_TIMER_FREQ / HZ; /* set interval */
*(unsigned short *)TCNT=0; /* clear counter */
ctrl_outb(0x80|CCLR_CMGRA|CLK_DIV8, TCR); /* set ITU0 clock */
ctrl_outb(0x88, TIOR); /* no output */
request_irq(26, timer_int, 0, "timer", 0);
ctrl_outb(0xf9, TIER); /* compare match GRA interrupt */
ctrl_outb(ctrl_inb(TSNC) & ~0x01, TSNC); /* ITU0 async */
ctrl_outb(ctrl_inb(TMDR) & ~0x01, TMDR); /* ITU0 normal mode */
ctrl_outb(ctrl_inb(TSTR) | 0x01, TSTR); /* ITU0 Start */
return 0;
}
u8 titan_inb_p(unsigned long port)
{
u8 v;
if (PXSEG(port))
v = ctrl_inb(port);
else if (is_pci_ioaddr(port))
v = ctrl_inb(pci_ioaddr(port));
else
v = ctrl_inw(port2adr(port)) & 0xff;
ctrl_delay();
return v;
}
static int hp6x0_pm_enter(suspend_state_t state)
{
u8 stbcr, stbcr2;
#ifdef CONFIG_HD64461_ENABLER
u8 scr;
u16 hd64461_stbcr;
#endif
if (state != PM_SUSPEND_MEM)
return -EINVAL;
#ifdef CONFIG_HD64461_ENABLER
outb(0, HD64461_PCC1CSCIER);
scr = inb(HD64461_PCC1SCR);
scr |= HD64461_PCCSCR_VCC1;
outb(scr, HD64461_PCC1SCR);
hd64461_stbcr = inw(HD64461_STBCR);
hd64461_stbcr |= HD64461_STBCR_SPC1ST;
outw(hd64461_stbcr, HD64461_STBCR);
#endif
ctrl_outb(0x1f, DACR);
stbcr = ctrl_inb(STBCR);
ctrl_outb(0x01, STBCR);
stbcr2 = ctrl_inb(STBCR2);
ctrl_outb(0x7f , STBCR2);
outw(0xf07f, HD64461_SCPUCR);
pm_enter();
outw(0, HD64461_SCPUCR);
ctrl_outb(stbcr, STBCR);
ctrl_outb(stbcr2, STBCR2);
#ifdef CONFIG_HD64461_ENABLER
hd64461_stbcr = inw(HD64461_STBCR);
hd64461_stbcr &= ~HD64461_STBCR_SPC1ST;
outw(hd64461_stbcr, HD64461_STBCR);
outb(0x4c, HD64461_PCC1CSCIER);
outb(0x00, HD64461_PCC1CSCR);
#endif
return 0;
}
unsigned char hs7751rvoip_inb_p(unsigned long port)
{
unsigned char v;
if (PXSEG(port))
v = ctrl_inb(port);
else if (codec_port(port))
v = ctrl_inb(CODEC_IOMAP(port));
else if (is_pci_ioaddr(port) || shifted_port(port))
v = ctrl_inb(pci_ioaddr(port));
else
v = ctrl_inw(port2adr(port)) & 0xff;
ctrl_delay();
return v;
}
/* For SH7707, SH7709, SH7709A, SH7729, SH7300*/
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
{
unsigned int fcr_val = 0;
#if !defined(CONFIG_CPU_SUBTYPE_SH7300) /* SH7300 doesn't use RTS/CTS */
{
unsigned short data;
/* We need to set SCPCR to enable RTS/CTS */
data = ctrl_inw(SCPCR);
/* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
ctrl_outw(data&0x0fcf, SCPCR);
}
if (cflag & CRTSCTS)
fcr_val |= SCFCR_MCE;
else {
unsigned short data;
/* We need to set SCPCR to enable RTS/CTS */
data = ctrl_inw(SCPCR);
/* Clear out SCP7MD1,0, SCP4MD1,0,
Set SCP6MD1,0 = {01} (output) */
ctrl_outw((data&0x0fcf)|0x1000, SCPCR);
data = ctrl_inb(SCPDR);
/* Set /RTS2 (bit6) = 0 */
ctrl_outb(data&0xbf, SCPDR);
}
#endif
sci_out(port, SCFCR, fcr_val);
}
/* For SH7707, SH7709, SH7709A, SH7729 */
static void sci_init_pins_scif(struct sci_port* port, unsigned int cflag)
{
unsigned int fcr_val = 0;
{
unsigned short data;
/* We need to set SCPCR to enable RTS/CTS */
data = ctrl_inw(SCPCR);
/* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
ctrl_outw(data&0x0fcf, SCPCR);
}
if (cflag & CRTSCTS)
fcr_val |= SCFCR_MCE;
else {
unsigned short data;
/* We need to set SCPCR to enable RTS/CTS */
data = ctrl_inw(SCPCR);
/* Clear out SCP7MD1,0, SCP4MD1,0,
Set SCP6MD1,0 = {01} (output) */
ctrl_outw((data&0x0fcf)|0x1000, SCPCR);
data = ctrl_inb(SCPDR);
/* Set /RTS2 (bit6) = 0 */
ctrl_outb(data&0xbf, SCPDR);
}
sci_out(port, SCFCR, fcr_val);
}
static void __init landisk_setup(char **cmdline_p)
{
/* LED ON */
ctrl_outb(ctrl_inb(PA_LED) | 0x03, PA_LED);
printk(KERN_INFO "I-O DATA DEVICE, INC. \"LANDISK Series\" support.\n");
pm_power_off = landisk_power_off;
}
static void e5_send_byte(u8 byte, struct e5_struct *k)
{
u8 status;
do {
status = ctrl_inb(EC3104_SER4_LSR);
} while ((status & LSR_BOTH_EMPTY) != LSR_BOTH_EMPTY);
printk("<%02x>", byte);
ctrl_outb(byte, EC3104_SER4_DATA);
do {
status = ctrl_inb(EC3104_SER4_LSR);
} while ((status & LSR_BOTH_EMPTY) != LSR_BOTH_EMPTY);
}
static void dac_audio_stop_timer(void)
{
u8 tstr;
tstr = ctrl_inb(TMU_TSTR);
tstr &= ~TMU1_TSTR_INIT;
ctrl_outb(tstr, TMU_TSTR);
}
void generic_outsl(unsigned long port, const void *buffer, unsigned long count)
{
const unsigned long *buf=buffer;
while(count--) outl(*buf++, port);
#ifdef SH3_PCMCIA_BUG_WORKAROUND
ctrl_inb (DUMMY_READ_AREA6);
#endif
}
static unsigned long pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct pll_clock *pll_clock = to_pll_clock(hw);
int mul = 1 << (ctrl_inb((unsigned long)pll_clock->pllcr) & 3);
return parent_rate * mul;
}
static void e5_wait_for_cts(struct e5_struct *k)
{
u8 msr;
do {
msr = ctrl_inb(EC3104_SER4_MSR);
} while (!(msr & MSR_CTS));
}
void generic_insl(unsigned long port, void *buffer, unsigned long count)
{
unsigned long *buf=buffer;
while(count--) *buf++=inl(port);
#ifdef SH3_PCMCIA_BUG_WORKAROUND
ctrl_inb (DUMMY_READ_AREA6);
#endif
}
static void hp690_japanese_scan_kbd(unsigned char *s)
{
int i;
unsigned const char *t=hp690_switch;
for(i=0; i<9; i++) {
ctrl_outb(*t++, PDDR);
ctrl_outb(*t++, PEDR);
*s++=ctrl_inb(PCDR);
*s++=ctrl_inb(PFDR);
}
ctrl_outb(0xff, PDDR);
ctrl_outb(0xff, PEDR);
*s++=ctrl_inb(PGDR);
*s++=ctrl_inb(PHDR);
}
u8 rts7751r2d_readb(void __iomem *addr)
{
unsigned long tmp = (unsigned long __force)addr;
if (is_ide_ioaddr(tmp))
return ctrl_inw(tmp) & 0xff;
else
return ctrl_inb(tmp);
}
static void ec3104_keyb_clear_state(void)
{
struct e5_struct *k = &ec3104_keyb;
u8 msr, lsr;
/* we want CTS to be low */
k->last_msr = 0;
for (;;) {
msleep(100);
msr = ctrl_inb(EC3104_SER4_MSR);
lsr = ctrl_inb(EC3104_SER4_LSR);
if (lsr & LSR_DR) {
e5_receive(k);
continue;
}
if ((msr & MSR_CTS) && !(k->last_msr & MSR_CTS)) {
if (k->cached_mcr & MCR_RTS)
printk("confused: RTS already high\n");
/* CTS went high. Send RTS. */
k->cached_mcr |= MCR_RTS;
ctrl_outb(k->cached_mcr, EC3104_SER4_MCR);
} else if ((!(msr & MSR_CTS)) && (k->last_msr & MSR_CTS)) {
/* CTS went low. */
if (!(k->cached_mcr & MCR_RTS))
printk("confused: RTS already low\n");
k->cached_mcr &= ~MCR_RTS;
ctrl_outb(k->cached_mcr, EC3104_SER4_MCR);
} else
break;
k->last_msr = msr;
continue;
}
}
/**
* sh_wdt_ping - Ping the Watchdog
*
* @data: Unused
*
* Clears overflow bit, resets timer counter.
*/
static void sh_wdt_ping(unsigned long data)
{
if (time_before(jiffies, next_heartbeat)) {
sh_wdt_write_csr((ctrl_inb(WTCSR) & ~WTCSR_IOVF));
sh_wdt_write_cnt(0);
timer.expires = next_ping_period(clock_division_ratio);
add_timer(&timer);
}
}
void __init platform_timer_setup(irqreturn_t (*timer_int)(int, void *, struct pt_regs *))
{
/* 8bit timer module enabled */
ctrl_outb(ctrl_inb(MSTPCRL) & ~0x01, MSTPCRL);
/* setup 8bit timer ch1 */
ctrl_outb(H8300_TIMER_FREQ / HZ, _8TCORA1); /* set interval */
ctrl_outb(0x00, _8TCSR1); /* no output */
request_irq(76, timer_int, 0, "timer" ,0);
ctrl_outb(CMIEA|CCLR_CMA|CLK_DIV8192, _8TCR1); /* start count */
}
/**
* sh_wdt_start - Start the Watchdog
*
* Starts the watchdog.
*/
static void sh_wdt_start(void)
{
timer.expires = next_ping_period(clock_division_ratio);
next_heartbeat = jiffies + (sh_heartbeat * HZ);
add_timer(&timer);
sh_wdt_write_csr(WTCSR_WT | WTCSR_CKS_4096);
sh_wdt_write_cnt(0);
sh_wdt_write_csr((ctrl_inb(WTCSR) | WTCSR_TME));
}
static void do_softint(struct work_struct *work)
{
int absx = 0, absy = 0;
u8 scpdr;
int touched = 0;
if (ctrl_inb(PHDR) & PHDR_TS_PEN_DOWN) {
scpdr = ctrl_inb(SCPDR);
scpdr |= SCPDR_TS_SCAN_ENABLE;
scpdr &= ~SCPDR_TS_SCAN_Y;
ctrl_outb(scpdr, SCPDR);
udelay(30);
absy = adc_single(ADC_CHANNEL_TS_Y);
scpdr = ctrl_inb(SCPDR);
scpdr |= SCPDR_TS_SCAN_Y;
scpdr &= ~SCPDR_TS_SCAN_X;
ctrl_outb(scpdr, SCPDR);
udelay(30);
absx = adc_single(ADC_CHANNEL_TS_X);
scpdr = ctrl_inb(SCPDR);
scpdr |= SCPDR_TS_SCAN_X;
scpdr &= ~SCPDR_TS_SCAN_ENABLE;
ctrl_outb(scpdr, SCPDR);
udelay(100);
touched = ctrl_inb(PHDR) & PHDR_TS_PEN_DOWN;
}
if (touched) {
input_report_key(hp680_ts_dev, BTN_TOUCH, 1);
input_report_abs(hp680_ts_dev, ABS_X, absx);
input_report_abs(hp680_ts_dev, ABS_Y, absy);
} else {
input_report_key(hp680_ts_dev, BTN_TOUCH, 0);
}
input_sync(hp680_ts_dev);
enable_irq(HP680_TS_IRQ);
}
static int pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
int pll;
unsigned char val;
unsigned long flags;
struct pll_clock *pll_clock = to_pll_clock(hw);
pll = ((rate / parent_rate) / 2) & 0x03;
spin_lock_irqsave(&clklock, flags);
val = ctrl_inb((unsigned long)pll_clock->sckcr);
val |= 0x08;
ctrl_outb(val, (unsigned long)pll_clock->sckcr);
val = ctrl_inb((unsigned long)pll_clock->pllcr);
val &= ~0x03;
val |= pll;
ctrl_outb(val, (unsigned long)pll_clock->pllcr);
spin_unlock_irqrestore(&clklock, flags);
return 0;
}
static void __init hp6xx_setup(char **cmdline_p)
{
u8 v8;
u16 v;
v = inw(HD64461_STBCR);
v |= HD64461_STBCR_SURTST | HD64461_STBCR_SIRST |
HD64461_STBCR_STM1ST | HD64461_STBCR_STM0ST |
HD64461_STBCR_SAFEST | HD64461_STBCR_SPC0ST |
HD64461_STBCR_SMIAST | HD64461_STBCR_SAFECKE_OST|
HD64461_STBCR_SAFECKE_IST;
#ifndef CONFIG_HD64461_ENABLER
v |= HD64461_STBCR_SPC1ST;
#endif
outw(v, HD64461_STBCR);
v = inw(HD64461_GPADR);
v |= HD64461_GPADR_SPEAKER | HD64461_GPADR_PCMCIA0;
outw(v, HD64461_GPADR);
outw(HD64461_PCCGCR_VCC0 | HD64461_PCCSCR_VCC1, HD64461_PCC0GCR);
#ifndef CONFIG_HD64461_ENABLER
outw(HD64461_PCCGCR_VCC0 | HD64461_PCCSCR_VCC1, HD64461_PCC1GCR);
#endif
sh_dac_output(0, DAC_SPEAKER_VOLUME);
sh_dac_disable(DAC_SPEAKER_VOLUME);
v8 = ctrl_inb(DACR);
v8 &= ~DACR_DAE;
ctrl_outb(v8,DACR);
v8 = ctrl_inb(SCPDR);
v8 |= SCPDR_TS_SCAN_X | SCPDR_TS_SCAN_Y;
v8 &= ~SCPDR_TS_SCAN_ENABLE;
ctrl_outb(v8, SCPDR);
v = ctrl_inw(SCPCR);
v &= ~SCPCR_TS_MASK;
v |= SCPCR_TS_ENABLE;
ctrl_outw(v, SCPCR);
}
void hs7751rvoip_insb(unsigned long port, void *addr, unsigned long count)
{
u8 *buf = addr;
if (PXSEG(port))
while (count--)
*buf++ = ctrl_inb(port);
else if (codec_port(port))
while (count--)
*buf++ = ctrl_inb(CODEC_IOMAP(port));
else if (is_pci_ioaddr(port) || shifted_port(port)) {
volatile u8 *bp = (volatile u8 *)pci_ioaddr(port);
while (count--)
*buf++ = *bp;
} else {
volatile u16 *p = (volatile u16 *)port2adr(port);
while (count--)
*buf++ = *p & 0xff;
}
}
void generic_insw(unsigned long port, void *buffer, unsigned long count)
{
volatile unsigned short *port_addr;
unsigned short *buf=buffer;
port_addr = (volatile unsigned short *)PORT2ADDR(port);
while(count--)
*buf++ = *port_addr;
#ifdef SH3_PCMCIA_BUG_WORKAROUND
ctrl_inb (DUMMY_READ_AREA6);
#endif
}
void generic_outsl(unsigned long port, const void *buffer, unsigned long count)
{
volatile unsigned long *port_addr;
const unsigned long *buf=buffer;
port_addr = (volatile unsigned long *)PORT2ADDR(port);
while(count--)
*port_addr = *buf++;
#ifdef SH3_PCMCIA_BUG_WORKAROUND
ctrl_inb (DUMMY_READ_AREA6);
#endif
}
void rts7751r2d_outsb(unsigned long port, const void *addr, unsigned long count)
{
unsigned long a = (unsigned long)addr;
volatile __u8 *bp;
volatile __u16 *p;
if (CHECK_AX88796L_PORT(port)) {
p = (volatile unsigned short *)port88796l(port, 0);
while (count--)
*p = ctrl_inb(a++);
} else if (PXSEG(port))
while (count--)
ctrl_outb(a++, port);
else if (is_pci_ioaddr(port) || shifted_port(port)) {
bp = (__u8 *)pci_ioaddr(port);
while (count--)
*bp = ctrl_inb(a++);
} else {
p = (volatile unsigned short *)port2adr(port);
while (count--)
*p = ctrl_inb(a++);
}
}
static void e5_receive(struct e5_struct *k)
{
k->packet[k->pos++] = ctrl_inb(EC3104_SER4_DATA);
if (k->pos == 1) {
switch(k->packet[0]) {
case 0x80:
k->length = 3;
break;
case 0x87: /* PS2 ext */
k->length = 6;
break;
case 0x88: /* keyboard */
k->length = 3;
break;
default:
k->length = 1;
printk(KERN_WARNING "unknown E5 packet %02x\n",
k->packet[0]);
}
}
if (k->pos == k->length) {
int i;
if (e5_checksum(k->packet, k->length) != 0)
printk(KERN_WARNING "E5: wrong checksum\n");
#if 0
printk("E5 packet [");
for(i=0; i<k->length; i++) {
printk("%02x ", k->packet[i]);
}
printk("(%02x)]\n", e5_checksum(k->packet, k->length-1));
#endif
switch(k->packet[0]) {
case 0x80:
case 0x88:
handle_keyboard_event(k->packet[1]);
break;
}
k->pos = k->length = 0;
}
}
