void cx25840_audio_set_path(struct i2c_client *client) { struct cx25840_state *state = i2c_get_clientdata(client); /* stop microcontroller */ cx25840_and_or(client, 0x803, ~0x10, 0); /* Mute everything to prevent the PFFT! */ cx25840_write(client, 0x8d3, 0x1f); if (state->aud_input == CX25840_AUDIO_SERIAL) { /* Set Path1 to Serial Audio Input */ cx25840_write4(client, 0x8d0, 0x12100101); /* The microcontroller should not be started for the * non-tuner inputs: autodetection is specific for * TV audio. */ } else { /* Set Path1 to Analog Demod Main Channel */ cx25840_write4(client, 0x8d0, 0x7038061f); /* When the microcontroller detects the * audio format, it will unmute the lines */ cx25840_and_or(client, 0x803, ~0x10, 0x10); } set_audclk_freq(client, state->audclk_freq); }
static unsigned int rxclk_rx_s_carrier(struct i2c_client *c, unsigned int freq, u16 *divider) { *divider = carrier_freq_to_clock_divider(freq); cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider); return clock_divider_to_carrier_freq(*divider); }
void cx25840_audio_set_path(struct i2c_client *client) { struct cx25840_state *state = to_state(i2c_get_clientdata(client)); if (!is_cx2583x(state)) { /* assert soft reset */ cx25840_and_or(client, 0x810, ~0x1, 0x01); /* stop microcontroller */ cx25840_and_or(client, 0x803, ~0x10, 0); /* Mute everything to prevent the PFFT! */ cx25840_write(client, 0x8d3, 0x1f); if (state->aud_input == CX25840_AUDIO_SERIAL) { /* Set Path1 to Serial Audio Input */ cx25840_write4(client, 0x8d0, 0x01011012); /* The microcontroller should not be started for the * non-tuner inputs: autodetection is specific for * TV audio. */ } else { /* Set Path1 to Analog Demod Main Channel */ cx25840_write4(client, 0x8d0, 0x1f063870); } } set_audclk_freq(client, state->audclk_freq); if (!is_cx2583x(state)) { if (state->aud_input != CX25840_AUDIO_SERIAL) { /* When the microcontroller detects the * audio format, it will unmute the lines */ cx25840_and_or(client, 0x803, ~0x10, 0x10); } /* deassert soft reset */ cx25840_and_or(client, 0x810, ~0x1, 0x00); /* Ensure the controller is running when we exit */ if (is_cx2388x(state) || is_cx231xx(state)) cx25840_and_or(client, 0x803, ~0x10, 0x10); } }
int cx25840_ir_probe(struct v4l2_subdev *sd) { struct cx25840_state *state = to_state(sd); struct cx25840_ir_state *ir_state; struct v4l2_subdev_ir_parameters default_params; /* Only init the IR controller for the CX2388[57] AV Core for now */ if (!(is_cx23885(state) || is_cx23887(state))) return 0; ir_state = kzalloc(sizeof(struct cx25840_ir_state), GFP_KERNEL); if (ir_state == NULL) return -ENOMEM; spin_lock_init(&ir_state->rx_kfifo_lock); ir_state->rx_kfifo = kfifo_alloc(CX25840_IR_RX_KFIFO_SIZE, GFP_KERNEL, &ir_state->rx_kfifo_lock); if (IS_ERR(ir_state->rx_kfifo)) { kfree(ir_state); return -ENOMEM; } ir_state->c = state->c; state->ir_state = ir_state; /* Ensure no interrupts arrive yet */ if (is_cx23885(state) || is_cx23887(state)) cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, IRQEN_MSK); else cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, 0); mutex_init(&ir_state->rx_params_lock); memcpy(&default_params, &default_rx_params, sizeof(struct v4l2_subdev_ir_parameters)); v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params); mutex_init(&ir_state->tx_params_lock); memcpy(&default_params, &default_tx_params, sizeof(struct v4l2_subdev_ir_parameters)); v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params); return 0; }
static int cx23885_set_audclk_freq(struct i2c_client *client, u32 freq) { struct cx25840_state *state = to_state(i2c_get_clientdata(client)); if (state->aud_input != CX25840_AUDIO_SERIAL) { switch (freq) { case 32000: case 44100: case 48000: /* We don't have register values * so avoid destroying registers. */ /* FIXME return -EINVAL; */ break; } } else { switch (freq) { case 32000: case 44100: /* We don't have register values * so avoid destroying registers. */ /* FIXME return -EINVAL; */ break; case 48000: /* src1_ctl */ /* 0x1.867c = 48000 / (2 * 28636360/8 * 2/455) */ cx25840_write4(client, 0x8f8, 0x0801867c); /* src3/4/6_ctl */ /* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */ cx25840_write4(client, 0x900, 0x08014faa); cx25840_write4(client, 0x904, 0x08014faa); cx25840_write4(client, 0x90c, 0x08014faa); break; } } state->audclk_freq = freq; return 0; }
/* * IR Tx Carrier Duty Cycle register helpers */ static unsigned int cduty_tx_s_duty_cycle(struct i2c_client *c, unsigned int duty_cycle) { u32 n; n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */ if (n != 0) n--; if (n > 15) n = 15; cx25840_write4(c, CX25840_IR_CDUTY_REG, n); return DIV_ROUND_CLOSEST((n + 1) * 100, 16); }
static u32 rxclk_rx_s_max_pulse_width(struct i2c_client *c, u32 ns, u16 *divider) { u64 pulse_clocks; if (ns > IR_MAX_DURATION) ns = IR_MAX_DURATION; pulse_clocks = ns_to_pulse_clocks(ns); *divider = pulse_clocks_to_clock_divider(pulse_clocks); cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider); return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider); }
static int cx25840_ir_tx_shutdown(struct v4l2_subdev *sd) { struct cx25840_ir_state *ir_state = to_ir_state(sd); struct i2c_client *c; if (ir_state == NULL) return -ENODEV; c = ir_state->c; mutex_lock(&ir_state->tx_params_lock); /* Disable or slow down all IR Tx circuits and counters */ irqenable_tx(sd, 0); control_tx_enable(c, false); control_tx_modulation_enable(c, false); cx25840_write4(c, CX25840_IR_TXCLK_REG, TXCLK_TCD); ir_state->tx_params.shutdown = true; mutex_unlock(&ir_state->tx_params_lock); return 0; }
static int cx25840_ir_rx_shutdown(struct v4l2_subdev *sd) { struct cx25840_ir_state *ir_state = to_ir_state(sd); struct i2c_client *c; if (ir_state == NULL) return -ENODEV; c = ir_state->c; mutex_lock(&ir_state->rx_params_lock); /* Disable or slow down all IR Rx circuits and counters */ irqenable_rx(sd, 0); control_rx_enable(c, false); control_rx_demodulation_enable(c, false); control_rx_s_edge_detection(c, CNTRL_EDG_NONE); filter_rx_s_min_width(c, 0); cx25840_write4(c, CX25840_IR_RXCLK_REG, RXCLK_RCD); ir_state->rx_params.shutdown = true; mutex_unlock(&ir_state->rx_params_lock); return 0; }
/* * V4L2 Subdevice IR Ops */ int cx25840_ir_irq_handler(struct v4l2_subdev *sd, u32 status, bool *handled) { struct cx25840_state *state = to_state(sd); struct cx25840_ir_state *ir_state = to_ir_state(sd); struct i2c_client *c = NULL; unsigned long flags; union cx25840_ir_fifo_rec rx_data[FIFO_RX_DEPTH]; unsigned int i, j, k; u32 events, v; int tsr, rsr, rto, ror, tse, rse, rte, roe, kror; u32 cntrl, irqen, stats; *handled = false; if (ir_state == NULL) return -ENODEV; c = ir_state->c; /* Only support the IR controller for the CX2388[57] AV Core for now */ if (!(is_cx23885(state) || is_cx23887(state))) return -ENODEV; cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG); irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG); if (is_cx23885(state) || is_cx23887(state)) irqen ^= IRQEN_MSK; stats = cx25840_read4(c, CX25840_IR_STATS_REG); tsr = stats & STATS_TSR; /* Tx FIFO Service Request */ rsr = stats & STATS_RSR; /* Rx FIFO Service Request */ rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */ ror = stats & STATS_ROR; /* Rx FIFO Over Run */ tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */ rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */ rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */ roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */ v4l2_dbg(2, ir_debug, sd, "IR IRQ Status: %s %s %s %s %s %s\n", tsr ? "tsr" : " ", rsr ? "rsr" : " ", rto ? "rto" : " ", ror ? "ror" : " ", stats & STATS_TBY ? "tby" : " ", stats & STATS_RBY ? "rby" : " "); v4l2_dbg(2, ir_debug, sd, "IR IRQ Enables: %s %s %s %s\n", tse ? "tse" : " ", rse ? "rse" : " ", rte ? "rte" : " ", roe ? "roe" : " "); /* * Transmitter interrupt service */ if (tse && tsr) { /* * TODO: * Check the watermark threshold setting * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo * Push the data to the hardware FIFO. * If there was nothing more to send in the tx_kfifo, disable * the TSR IRQ and notify the v4l2_device. * If there was something in the tx_kfifo, check the tx_kfifo * level and notify the v4l2_device, if it is low. */ /* For now, inhibit TSR interrupt until Tx is implemented */ irqenable_tx(sd, 0); events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ; v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events); *handled = true; } /* * Receiver interrupt service */ kror = 0; if ((rse && rsr) || (rte && rto)) { /* * Receive data on RSR to clear the STATS_RSR. * Receive data on RTO, since we may not have yet hit the RSR * watermark when we receive the RTO. */ for (i = 0, v = FIFO_RX_NDV; (v & FIFO_RX_NDV) && !kror; i = 0) { for (j = 0; (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) { v = cx25840_read4(c, CX25840_IR_FIFO_REG); rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV; i++; } if (i == 0) break; j = i * sizeof(union cx25840_ir_fifo_rec); k = kfifo_in_locked(&ir_state->rx_kfifo, (unsigned char *) rx_data, j, &ir_state->rx_kfifo_lock); if (k != j) kror++; /* rx_kfifo over run */ } *handled = true; } events = 0; v = 0; if (kror) { events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN; v4l2_err(sd, "IR receiver software FIFO overrun\n"); } if (roe && ror) { /* * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear * the Rx FIFO Over Run status (STATS_ROR) */ v |= CNTRL_RFE; events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN; v4l2_err(sd, "IR receiver hardware FIFO overrun\n"); } if (rte && rto) { /* * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear * the Rx Pulse Width Timer Time Out (STATS_RTO) */ v |= CNTRL_RXE; events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED; } if (v) { /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */ cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl & ~v); cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl); *handled = true; } spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags); if (kfifo_len(&ir_state->rx_kfifo) >= CX25840_IR_RX_KFIFO_SIZE / 2) events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ; spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags); if (events) v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events); return 0; }
/* * IR Filter Register helpers */ static u32 filter_rx_s_min_width(struct i2c_client *c, u32 min_width_ns) { u32 count = ns_to_lpf_count(min_width_ns); cx25840_write4(c, CX25840_IR_FILTR_REG, count); return lpf_count_to_ns(count); }
static int set_audclk_freq(struct i2c_client *client, u32 freq) { struct cx25840_state *state = i2c_get_clientdata(client); if (freq != 32000 && freq != 44100 && freq != 48000) return -EINVAL; /* common for all inputs and rates */ /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x10 */ cx25840_write(client, 0x127, 0x50); if (state->aud_input != CX25840_AUDIO_SERIAL) { switch (freq) { case 32000: /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x0f040610); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0xee39bb01); if (state->is_cx25836) break; /* src3/4/6_ctl = 0x0801f77f */ cx25840_write4(client, 0x900, 0x7ff70108); cx25840_write4(client, 0x904, 0x7ff70108); cx25840_write4(client, 0x90c, 0x7ff70108); break; case 44100: /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x0f040910); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0xd66bec00); if (state->is_cx25836) break; /* src3/4/6_ctl = 0x08016d59 */ cx25840_write4(client, 0x900, 0x596d0108); cx25840_write4(client, 0x904, 0x596d0108); cx25840_write4(client, 0x90c, 0x596d0108); break; case 48000: /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x0f040a10); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0xe5d69800); if (state->is_cx25836) break; /* src3/4/6_ctl = 0x08014faa */ cx25840_write4(client, 0x900, 0xaa4f0108); cx25840_write4(client, 0x904, 0xaa4f0108); cx25840_write4(client, 0x90c, 0xaa4f0108); break; } } else { switch (freq) { case 32000: /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x0f04081e); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0x69082a01); if (state->is_cx25836) break; /* src1_ctl = 0x08010000 */ cx25840_write4(client, 0x8f8, 0x00000108); /* src3/4/6_ctl = 0x08020000 */ cx25840_write4(client, 0x900, 0x00000208); cx25840_write4(client, 0x904, 0x00000208); cx25840_write4(client, 0x90c, 0x00000208); /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x14 */ cx25840_write(client, 0x127, 0x54); break; case 44100: /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x0f040918); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0xd66bec00); if (state->is_cx25836) break; /* src1_ctl = 0x08010000 */ cx25840_write4(client, 0x8f8, 0xcd600108); /* src3/4/6_ctl = 0x08020000 */ cx25840_write4(client, 0x900, 0x85730108); cx25840_write4(client, 0x904, 0x85730108); cx25840_write4(client, 0x90c, 0x85730108); break; case 48000: /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x0f040a18); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0xe5d69800); if (state->is_cx25836) break; /* src1_ctl = 0x08010000 */ cx25840_write4(client, 0x8f8, 0x00800108); /* src3/4/6_ctl = 0x08020000 */ cx25840_write4(client, 0x900, 0x55550108); cx25840_write4(client, 0x904, 0x55550108); cx25840_write4(client, 0x90c, 0x55550108); break; } } state->audclk_freq = freq; return 0; }
static int set_audclk_freq(struct i2c_client *client, u32 freq) { struct cx25840_state *state = to_state(i2c_get_clientdata(client)); if (freq != 32000 && freq != 44100 && freq != 48000) return -EINVAL; /* common for all inputs and rates */ /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x10 */ if (!state->is_cx23885 && !state->is_cx231xx) cx25840_write(client, 0x127, 0x50); if (state->aud_input != CX25840_AUDIO_SERIAL) { switch (freq) { case 32000: if (state->is_cx23885) { /* We don't have register values * so avoid destroying registers. */ break; } if (!state->is_cx231xx) { /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x1006040f); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0x01bb39ee); } if (state->is_cx25836) break; /* src3/4/6_ctl = 0x0801f77f */ cx25840_write4(client, 0x900, 0x0801f77f); cx25840_write4(client, 0x904, 0x0801f77f); cx25840_write4(client, 0x90c, 0x0801f77f); break; case 44100: if (state->is_cx23885) { /* We don't have register values * so avoid destroying registers. */ break; } if (!state->is_cx231xx) { /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x1009040f); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0x00ec6bd6); } if (state->is_cx25836) break; /* src3/4/6_ctl = 0x08016d59 */ cx25840_write4(client, 0x900, 0x08016d59); cx25840_write4(client, 0x904, 0x08016d59); cx25840_write4(client, 0x90c, 0x08016d59); break; case 48000: if (state->is_cx23885) { /* We don't have register values * so avoid destroying registers. */ break; } if (!state->is_cx231xx) { /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x100a040f); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0x0098d6e5); } if (state->is_cx25836) break; /* src3/4/6_ctl = 0x08014faa */ cx25840_write4(client, 0x900, 0x08014faa); cx25840_write4(client, 0x904, 0x08014faa); cx25840_write4(client, 0x90c, 0x08014faa); break; } } else { switch (freq) { case 32000: if (state->is_cx23885) { /* We don't have register values * so avoid destroying registers. */ break; } if (!state->is_cx231xx) { /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x1e08040f); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0x012a0869); } if (state->is_cx25836) break; /* src1_ctl = 0x08010000 */ cx25840_write4(client, 0x8f8, 0x08010000); /* src3/4/6_ctl = 0x08020000 */ cx25840_write4(client, 0x900, 0x08020000); cx25840_write4(client, 0x904, 0x08020000); cx25840_write4(client, 0x90c, 0x08020000); /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x14 */ cx25840_write(client, 0x127, 0x54); break; case 44100: if (state->is_cx23885) { /* We don't have register values * so avoid destroying registers. */ break; } if (!state->is_cx231xx) { /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x1809040f); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0x00ec6bd6); } if (state->is_cx25836) break; /* src1_ctl = 0x08010000 */ cx25840_write4(client, 0x8f8, 0x080160cd); /* src3/4/6_ctl = 0x08020000 */ cx25840_write4(client, 0x900, 0x08017385); cx25840_write4(client, 0x904, 0x08017385); cx25840_write4(client, 0x90c, 0x08017385); break; case 48000: if (!state->is_cx23885 && !state->is_cx231xx) { /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x180a040f); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0x0098d6e5); } if (state->is_cx25836) break; if (!state->is_cx23885 && !state->is_cx231xx) { /* src1_ctl */ cx25840_write4(client, 0x8f8, 0x08018000); /* src3/4/6_ctl */ cx25840_write4(client, 0x900, 0x08015555); cx25840_write4(client, 0x904, 0x08015555); cx25840_write4(client, 0x90c, 0x08015555); } else { cx25840_write4(client, 0x8f8, 0x0801867c); cx25840_write4(client, 0x900, 0x08014faa); cx25840_write4(client, 0x904, 0x08014faa); cx25840_write4(client, 0x90c, 0x08014faa); } break; } } state->audclk_freq = freq; return 0; }
static int cx25840_set_audclk_freq(struct i2c_client *client, u32 freq) { struct cx25840_state *state = to_state(i2c_get_clientdata(client)); if (state->aud_input != CX25840_AUDIO_SERIAL) { switch (freq) { case 32000: /* * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10 */ cx25840_write4(client, 0x108, 0x1006040f); /* * VID_PLL Fraction (register 0x10c) = 0x2be2fe * 28636360 * 0xf.15f17f0/4 = 108 MHz * 432 MHz pre-postdivide */ /* * AUX_PLL Fraction = 0x1bb39ee * 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384 * 196.6 MHz pre-postdivide * FIXME < 200 MHz is out of specified valid range * FIXME 28636363 ref_freq doesn't match VID PLL ref */ cx25840_write4(client, 0x110, 0x01bb39ee); /* * SA_MCLK_SEL = 1 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider */ cx25840_write(client, 0x127, 0x50); if (is_cx2583x(state)) break; /* src3/4/6_ctl */ /* 0x1.f77f = (4 * 28636360/8 * 2/455) / 32000 */ cx25840_write4(client, 0x900, 0x0801f77f); cx25840_write4(client, 0x904, 0x0801f77f); cx25840_write4(client, 0x90c, 0x0801f77f); break; case 44100: /* * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 * AUX_PLL Integer = 0x09, AUX PLL Post Divider = 0x10 */ cx25840_write4(client, 0x108, 0x1009040f); /* * VID_PLL Fraction (register 0x10c) = 0x2be2fe * 28636360 * 0xf.15f17f0/4 = 108 MHz * 432 MHz pre-postdivide */ /* * AUX_PLL Fraction = 0x0ec6bd6 * 28636363 * 0x9.7635eb0/0x10 = 44100 * 384 * 271 MHz pre-postdivide * FIXME 28636363 ref_freq doesn't match VID PLL ref */ cx25840_write4(client, 0x110, 0x00ec6bd6); /* * SA_MCLK_SEL = 1 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider */ cx25840_write(client, 0x127, 0x50); if (is_cx2583x(state)) break; /* src3/4/6_ctl */ /* 0x1.6d59 = (4 * 28636360/8 * 2/455) / 44100 */ cx25840_write4(client, 0x900, 0x08016d59); cx25840_write4(client, 0x904, 0x08016d59); cx25840_write4(client, 0x90c, 0x08016d59); break; case 48000: /* * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 * AUX_PLL Integer = 0x0a, AUX PLL Post Divider = 0x10 */ cx25840_write4(client, 0x108, 0x100a040f); /* * VID_PLL Fraction (register 0x10c) = 0x2be2fe * 28636360 * 0xf.15f17f0/4 = 108 MHz * 432 MHz pre-postdivide */ /* * AUX_PLL Fraction = 0x098d6e5 * 28636363 * 0xa.4c6b728/0x10 = 48000 * 384 * 295 MHz pre-postdivide * FIXME 28636363 ref_freq doesn't match VID PLL ref */ cx25840_write4(client, 0x110, 0x0098d6e5); /* * SA_MCLK_SEL = 1 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider */ cx25840_write(client, 0x127, 0x50); if (is_cx2583x(state)) break; /* src3/4/6_ctl */ /* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */ cx25840_write4(client, 0x900, 0x08014faa); cx25840_write4(client, 0x904, 0x08014faa); cx25840_write4(client, 0x90c, 0x08014faa); break; } } else { switch (freq) { case 32000: /* * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 * AUX_PLL Integer = 0x08, AUX PLL Post Divider = 0x1e */ cx25840_write4(client, 0x108, 0x1e08040f); /* * VID_PLL Fraction (register 0x10c) = 0x2be2fe * 28636360 * 0xf.15f17f0/4 = 108 MHz * 432 MHz pre-postdivide */ /* * AUX_PLL Fraction = 0x12a0869 * 28636363 * 0x8.9504348/0x1e = 32000 * 256 * 246 MHz pre-postdivide * FIXME 28636363 ref_freq doesn't match VID PLL ref */ cx25840_write4(client, 0x110, 0x012a0869); /* * SA_MCLK_SEL = 1 * SA_MCLK_DIV = 0x14 = 256/384 * AUX_PLL post dvivider */ cx25840_write(client, 0x127, 0x54); if (is_cx2583x(state)) break; /* src1_ctl */ /* 0x1.0000 = 32000/32000 */ cx25840_write4(client, 0x8f8, 0x08010000); /* src3/4/6_ctl */ /* 0x2.0000 = 2 * (32000/32000) */ cx25840_write4(client, 0x900, 0x08020000); cx25840_write4(client, 0x904, 0x08020000); cx25840_write4(client, 0x90c, 0x08020000); break; case 44100: /* * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 * AUX_PLL Integer = 0x09, AUX PLL Post Divider = 0x18 */ cx25840_write4(client, 0x108, 0x1809040f); /* * VID_PLL Fraction (register 0x10c) = 0x2be2fe * 28636360 * 0xf.15f17f0/4 = 108 MHz * 432 MHz pre-postdivide */ /* * AUX_PLL Fraction = 0x0ec6bd6 * 28636363 * 0x9.7635eb0/0x18 = 44100 * 256 * 271 MHz pre-postdivide * FIXME 28636363 ref_freq doesn't match VID PLL ref */ cx25840_write4(client, 0x110, 0x00ec6bd6); /* * SA_MCLK_SEL = 1 * SA_MCLK_DIV = 0x10 = 256/384 * AUX_PLL post dvivider */ cx25840_write(client, 0x127, 0x50); if (is_cx2583x(state)) break; /* src1_ctl */ /* 0x1.60cd = 44100/32000 */ cx25840_write4(client, 0x8f8, 0x080160cd); /* src3/4/6_ctl */ /* 0x1.7385 = 2 * (32000/44100) */ cx25840_write4(client, 0x900, 0x08017385); cx25840_write4(client, 0x904, 0x08017385); cx25840_write4(client, 0x90c, 0x08017385); break; case 48000: /* * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 * AUX_PLL Integer = 0x0a, AUX PLL Post Divider = 0x18 */ cx25840_write4(client, 0x108, 0x180a040f); /* * VID_PLL Fraction (register 0x10c) = 0x2be2fe * 28636360 * 0xf.15f17f0/4 = 108 MHz * 432 MHz pre-postdivide */ /* * AUX_PLL Fraction = 0x098d6e5 * 28636363 * 0xa.4c6b728/0x18 = 48000 * 256 * 295 MHz pre-postdivide * FIXME 28636363 ref_freq doesn't match VID PLL ref */ cx25840_write4(client, 0x110, 0x0098d6e5); /* * SA_MCLK_SEL = 1 * SA_MCLK_DIV = 0x10 = 256/384 * AUX_PLL post dvivider */ cx25840_write(client, 0x127, 0x50); if (is_cx2583x(state)) break; /* src1_ctl */ /* 0x1.8000 = 48000/32000 */ cx25840_write4(client, 0x8f8, 0x08018000); /* src3/4/6_ctl */ /* 0x1.5555 = 2 * (32000/48000) */ cx25840_write4(client, 0x900, 0x08015555); cx25840_write4(client, 0x904, 0x08015555); cx25840_write4(client, 0x90c, 0x08015555); break; } } state->audclk_freq = freq; return 0; }
static int cx231xx_set_audclk_freq(struct i2c_client *client, u32 freq) { struct cx25840_state *state = to_state(i2c_get_clientdata(client)); if (state->aud_input != CX25840_AUDIO_SERIAL) { switch (freq) { case 32000: /* src3/4/6_ctl */ /* 0x1.f77f = (4 * 28636360/8 * 2/455) / 32000 */ cx25840_write4(client, 0x900, 0x0801f77f); cx25840_write4(client, 0x904, 0x0801f77f); cx25840_write4(client, 0x90c, 0x0801f77f); break; case 44100: /* src3/4/6_ctl */ /* 0x1.6d59 = (4 * 28636360/8 * 2/455) / 44100 */ cx25840_write4(client, 0x900, 0x08016d59); cx25840_write4(client, 0x904, 0x08016d59); cx25840_write4(client, 0x90c, 0x08016d59); break; case 48000: /* src3/4/6_ctl */ /* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */ cx25840_write4(client, 0x900, 0x08014faa); cx25840_write4(client, 0x904, 0x08014faa); cx25840_write4(client, 0x90c, 0x08014faa); break; } } else { switch (freq) { /* FIXME These cases make different assumptions about audclk */ case 32000: /* src1_ctl */ /* 0x1.0000 = 32000/32000 */ cx25840_write4(client, 0x8f8, 0x08010000); /* src3/4/6_ctl */ /* 0x2.0000 = 2 * (32000/32000) */ cx25840_write4(client, 0x900, 0x08020000); cx25840_write4(client, 0x904, 0x08020000); cx25840_write4(client, 0x90c, 0x08020000); break; case 44100: /* src1_ctl */ /* 0x1.60cd = 44100/32000 */ cx25840_write4(client, 0x8f8, 0x080160cd); /* src3/4/6_ctl */ /* 0x1.7385 = 2 * (32000/44100) */ cx25840_write4(client, 0x900, 0x08017385); cx25840_write4(client, 0x904, 0x08017385); cx25840_write4(client, 0x90c, 0x08017385); break; case 48000: /* src1_ctl */ /* 0x1.867c = 48000 / (2 * 28636360/8 * 2/455) */ cx25840_write4(client, 0x8f8, 0x0801867c); /* src3/4/6_ctl */ /* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */ cx25840_write4(client, 0x900, 0x08014faa); cx25840_write4(client, 0x904, 0x08014faa); cx25840_write4(client, 0x90c, 0x08014faa); break; } } state->audclk_freq = freq; return 0; }