void SMP::op_write(uint16 addr, uint8 data) { debugger.op_write(addr, data); add_clocks(24); op_buswrite(addr, data); cycle_edge(); }
void sCPU::dma_transfer(bool direction, uint8 bbus, uint32 abus) { if(direction == 0) { //a->b transfer (to $21xx) if(bbus == 0x80 && ((abus & 0xfe0000) == 0x7e0000 || (abus & 0x40e000) == 0x0000)) { //illegal WRAM->WRAM transfer (bus conflict) //read most likely occurs; no write occurs //read is irrelevent, as it cannot be observed by software dma_add_clocks(8); } else { dma_add_clocks(4); uint8 data = dma_read(abus); dma_add_clocks(4); bus.write(0x2100 | bbus, data); } } else { //b->a transfer (from $21xx) if(bbus == 0x80 && ((abus & 0xfe0000) == 0x7e0000 || (abus & 0x40e000) == 0x0000)) { //illegal WRAM->WRAM transfer (bus conflict) //no read occurs; write does occur dma_add_clocks(8); bus.write(abus, 0x00); //does not write S-CPU MDR } else { dma_add_clocks(4); uint8 data = bus.read(0x2100 | bbus); dma_add_clocks(4); if(dma_addr_valid(abus) == true) { bus.write(abus, data); } } } cycle_edge(); }
uint8 SMP::op_read(uint16 addr) { add_clocks(12); uint8 r = op_busread(addr); add_clocks(12); cycle_edge(); return r; }
uint8 SMP::op_read(uint16 addr, eCDLog_Flags flags) { debugger.op_read(addr); add_clocks(12); cdlInfo.currFlags = flags; uint8 r = op_busread(addr); add_clocks(12); cycle_edge(); return r; }
void sCPU::dma_run() { dma_add_clocks(8); cycle_edge(); for(unsigned i = 0; i < 8; i++) { if(channel[i].dma_enabled == false) continue; dma_add_clocks(8); cycle_edge(); unsigned index = 0; do { dma_transfer(channel[i].direction, dma_bbus(i, index++), dma_addr(i)); } while(channel[i].dma_enabled && --channel[i].xfersize); channel[i].dma_enabled = false; } status.irq_lock = true; event.enqueue(2, EventIrqLockRelease); }
void SMP::op_io() { add_clocks(24); cycle_edge(); }