void
cyg_hal_am33_serial_init(int first_chan)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
int i;
for (i = 0; i < AM33_NUM_UARTS; i++) {
// Disable interrupts.
HAL_INTERRUPT_MASK(channels[0].isr_vector);
// Init channel
cyg_hal_plf_serial_init_channel((void*)&channels[i]);
cyg_hal_plf_serial_set_baud(channels[i].base, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD);
// Setup procs in the vector table
CYGACC_CALL_IF_SET_CONSOLE_COMM(i + first_chan);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
}
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
cyg_uint8* port;
cyg_uint8 _lcr;
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
port = ((channel_data_t*)__ch_data)->base;
// Disable port interrupts while changing hardware
HAL_WRITE_UINT8(port+SER_16550_IER, 0);
// Set databits, stopbits and parity.
_lcr = LCR_WL8 | LCR_SB1 | LCR_PN;
HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);
// Set baud rate.
cyg_hal_plf_serial_set_baud(port, CYG_DEV_SERIAL_BAUD_DIVISOR);
// Enable and clear FIFO
HAL_WRITE_UINT8(port+SER_16550_FCR, (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT));
// enable RTS to keep host side happy
HAL_WRITE_UINT8( port+SER_16550_MCR, MCR_RTS );
// Don't allow interrupts.
HAL_WRITE_UINT8(port+SER_16550_IER, 0);
}
void
cyg_hal_plf_serial_setbaud(void *__ch_data, cyg_uint32 baud_rate)
{
cyg_uint8* port;
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
port = ((channel_data_t*)__ch_data)->base;
cyg_hal_plf_serial_set_baud(port, baud_rate);
}
void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
CYG_ADDRWORD port;
cyg_uint8 _lcr;
cyg_uint32 freq;
hal_ar7240_sys_frequency();
freq = ar7240_ahb_freq;
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
port = ((channel_data_t*)__ch_data)->base;
/*
* undocumented. confirm, why write to GPIO for uart?
*/
ar7240_reg_wr(AR7240_GPIO_OE, 0xcff);
ar7240_reg_wr(AR7240_GPIO_OUT, 0x3b);
ar7240_reg_wr(AR7240_GPIO_FUNCTIONS, (ar7240_reg_rd(AR7240_GPIO_FUNCTIONS) | 0x48002));
ar7240_reg_wr(AR7240_GPIO_OUT, 0x2f);
// Disable port interrupts while changing hardware
HAL_WRITE_UINT32(port+SER_16550_IER, 0);
// Set databits, stopbits and parity.
_lcr = LCR_WL8 | LCR_SB1 | LCR_PN;
HAL_WRITE_UINT32(port+SER_16550_LCR, _lcr);
// Set baud rate.
cyg_hal_plf_serial_set_baud(port, freq / (16 *
CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD));
// Enable and clear FIFO
HAL_WRITE_UINT32(port+SER_16550_FCR, (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT));
#ifdef NOTANYMORE
// enable RTS to keep host side happy. Also allow interrupts
HAL_WRITE_UINT32( port+SER_16550_MCR, MCR_DTR | MCR_RTS | MCR_INT);
#endif
// Don't allow interrupts.
HAL_WRITE_UINT32(port+SER_16550_IER, 0);
}
void cyg_hal_plf_serial_init_channel(void* __ch_data)
{
cyg_uint32 port;
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
port = ((channel_data_t*)__ch_data)->base;
/* Reset UART controller by generating an one to zero transition */
if (port == HAL_RA305X_UART_BASE) {
HAL_SYSCTL_REG(RA305X_SYSCTL_RESET) = RA305X_SYSCTL_UART_RST;
} else if (port == HAL_RA305X_UARTLITE_BASE) {
HAL_SYSCTL_REG(RA305X_SYSCTL_RESET) = RA305X_SYSCTL_UARTL_RST;
}
#ifdef CONFIG_MT7628_ASIC
else if (port == HAL_RA305X_UART_LITE3_BASE)
HAL_SYSCTL_REG(RA305X_SYSCTL_RESET) = RA305X_SYSCTL_UARTL3_RST;
#endif
HAL_SYSCTL_REG(RA305X_SYSCTL_RESET) = 0;
// Disable port interrupts while changing hardware
RA_UART_REG(port, UART_IER) = 0;
// Set databits, stopbits and parity.
RA_UART_REG(port, UART_LCR) = UART_LCR_WLS_8BIT;
// Set default baud rate.
cyg_hal_plf_serial_set_baud(port, CYG_DEV_SERIAL_BAUD_DIVISOR);
// Enable and clear FIFO
RA_UART_REG(port, UART_FCR) = UART_FCR_FIFOEN | UART_FCR_RXRST | UART_FCR_TXRST | 0x80;
// RA_UART_REG(port, UART_FCR) = 0;
// enable RTS to keep host side happy.
RA_UART_REG(port, UART_MCR) = UART_MCR_RTS | UART_MCR_DTS;
cyg_hal_plf_serial_write(__ch_data,"diag init\n\r",strlen("diag init\n\r"));
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan;
cyg_uint8 icr;
int ret = 0;
CYGARC_HAL_SAVE_GP();
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
chan = (channel_data_t*)__ch_data;
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_READ_UINT8(chan->base + _SERIAL_ICR, icr);
icr |= SIO_INT_ENABLE;
HAL_WRITE_UINT8(chan->base + _SERIAL_ICR, icr);
HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_READ_UINT8(chan->base + _SERIAL_ICR, icr);
icr &= ~SIO_INT_ENABLE;
HAL_WRITE_UINT8(chan->base + _SERIAL_ICR, icr);
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
break;
case __COMMCTL_SETBAUD:
{
cyg_uint32 baud_rate;
cyg_uint8* port = chan->base;
va_list ap;
va_start(ap, __func);
baud_rate = va_arg(ap, cyg_uint32);
va_end(ap);
// Disable port interrupts while changing hardware
HAL_READ_UINT8(port + _SERIAL_ICR, icr);
HAL_WRITE_UINT8(port + _SERIAL_ICR, 0);
// Set baud rate.
ret = cyg_hal_plf_serial_set_baud(port, baud_rate);
// Reenable interrupts if necessary
HAL_WRITE_UINT8(port + _SERIAL_ICR, icr);
}
break;
case __COMMCTL_GETBAUD:
break;
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan;
cyg_uint8 ier;
int ret = 0;
CYGARC_HAL_SAVE_GP();
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
chan = (channel_data_t*)__ch_data;
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_READ_UINT8(chan->base + SER_16550_IER, ier);
ier |= SIO_IER_ERDAI;
HAL_WRITE_UINT8(chan->base + SER_16550_IER, ier);
HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_READ_UINT8(chan->base + SER_16550_IER, ier);
ier &= ~SIO_IER_ERDAI;
HAL_WRITE_UINT8(chan->base + SER_16550_IER, ier);
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
break;
case __COMMCTL_SETBAUD:
{
cyg_uint32 baud_rate;
cyg_uint16 baud_divisor;
cyg_uint8* port = chan->base;
va_list ap;
va_start(ap, __func);
baud_rate = va_arg(ap, cyg_uint32);
va_end(ap);
switch (baud_rate)
{
case 110: baud_divisor = DIVISOR(110); break;
case 150: baud_divisor = DIVISOR(150); break;
case 300: baud_divisor = DIVISOR(300); break;
case 600: baud_divisor = DIVISOR(600); break;
case 1200: baud_divisor = DIVISOR(1200); break;
case 2400: baud_divisor = DIVISOR(2400); break;
case 4800: baud_divisor = DIVISOR(4800); break;
case 7200: baud_divisor = DIVISOR(7200); break;
case 9600: baud_divisor = DIVISOR(9600); break;
case 14400: baud_divisor = DIVISOR(14400); break;
case 19200: baud_divisor = DIVISOR(19200); break;
case 38400: baud_divisor = DIVISOR(38400); break;
case 57600: baud_divisor = DIVISOR(57600); break;
case 115200: baud_divisor = DIVISOR(115200); break;
case 230400: baud_divisor = DIVISOR(230400); break;
default: return -1; break; // Invalid baud rate selected
}
// Disable port interrupts while changing hardware
HAL_READ_UINT8(port+SER_16550_IER, ier);
HAL_WRITE_UINT8(port+SER_16550_IER, 0);
// Set baud rate.
cyg_hal_plf_serial_set_baud(port, baud_divisor);
// Reenable interrupts if necessary
HAL_WRITE_UINT8(port+SER_16550_IER, ier);
}
break;
case __COMMCTL_GETBAUD:
break;
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan;
cyg_uint8 ier;
int ret = 0;
CYGARC_HAL_SAVE_GP();
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
chan = (channel_data_t*)__ch_data;
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_READ_UINT8(chan->base + SER_16550_IER, ier);
ier |= SIO_IER_ERDAI;
HAL_WRITE_UINT8(chan->base + SER_16550_IER, ier);
HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_READ_UINT8(chan->base + SER_16550_IER, ier);
ier &= ~SIO_IER_ERDAI;
HAL_WRITE_UINT8(chan->base + SER_16550_IER, ier);
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
break;
case __COMMCTL_SETBAUD:
{
cyg_uint32 baud_rate;
cyg_uint16 baud_divisor;
cyg_uint8* port = chan->base;
va_list ap;
va_start(ap, __func);
baud_rate = va_arg(ap, cyg_uint32);
va_end(ap);
switch (baud_rate)
{
case 110:
baud_divisor = BAUD_110;
break;
case 150:
baud_divisor = BAUD_150;
break;
case 300:
baud_divisor = BAUD_300;
break;
case 600:
baud_divisor = BAUD_600;
break;
case 1200:
baud_divisor = BAUD_1200;
break;
case 2400:
baud_divisor = BAUD_2400;
break;
case 4800:
baud_divisor = BAUD_4800;
break;
case 7200:
baud_divisor = BAUD_7200;
break;
case 9600:
baud_divisor = BAUD_9600;
break;
case 14400:
baud_divisor = BAUD_14400;
break;
case 19200:
baud_divisor = BAUD_19200;
break;
case 38400:
baud_divisor = BAUD_38400;
break;
case 57600:
baud_divisor = BAUD_57600;
break;
case 115200:
baud_divisor = BAUD_115200;
break;
case 230400:
baud_divisor = BAUD_230400;
break;
default:
return -1;
break; // Invalid baud rate selected
}
//
// We may need to increase the timeout before causing a break reset.
// According to the Atlas Users Manual (Document MD00005) The BRKRES
// register will need to be programmed with a value larger that 0xA (the default)
// if we are going to use a baud rate lower than 2400.
//
if (baud_rate <= 2400)
{
// For now, just disable the break reset entirely.
HAL_WRITE_UINT32(HAL_ATLAS_BRKRES, 0);
} else {
// Put the break reset state back to the default
HAL_WRITE_UINT32(HAL_ATLAS_BRKRES, HAL_ATLAS_BRKRES_DEFAULT_VALUE);
}
// Disable port interrupts while changing hardware
HAL_READ_UINT8(port+SER_16550_IER, ier);
HAL_WRITE_UINT8(port+SER_16550_IER, 0);
// Set baud rate.
cyg_hal_plf_serial_set_baud(port, baud_divisor);
// Reenable interrupts if necessary
HAL_WRITE_UINT8(port+SER_16550_IER, ier);
}
break;
case __COMMCTL_GETBAUD:
break;
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan;
cyg_uint32 intmask;
int ret = 0;
CYGARC_HAL_SAVE_GP();
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
chan = (channel_data_t*)__ch_data;
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
RA_UART_REG(chan->base, UART_IER) |= UART_IER_ERBFI;
HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
RA_UART_REG(chan->base, UART_IER) &= ~UART_IER_ERBFI;
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
break;
case __COMMCTL_SETBAUD:
{
cyg_uint32 baud_rate;
cyg_uint16 baud_divisor;
cyg_uint32 port = chan->base;
va_list ap;
va_start(ap, __func);
baud_rate = va_arg(ap, cyg_uint32);
va_end(ap);
baud_divisor = RA_SERIAL_BAUD_DIVISOR(baud_rate);
// Disable port interrupts while changing hardware
intmask = RA_UART_REG(port, UART_IER);
RA_UART_REG(port, UART_IER) = 0;
// Set baud rate.
cyg_hal_plf_serial_set_baud(port, baud_divisor);
// Reenable interrupts if necessary
RA_UART_REG(port, UART_IER) = intmask;
}
break;
case __COMMCTL_GETBAUD:
break;
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
