static void
do_lspci(int argc, char *argv[])
{
cyg_uint8 devfn;
cyg_pci_device_id devid = CYG_PCI_NULL_DEVID;
cyg_pci_device dev_info;
int i;
while (cyg_pci_find_next(devid, &devid)) {
devfn = CYG_PCI_DEV_GET_DEVFN(devid);
// Get the device info
cyg_pci_get_device_info(devid, &dev_info);
diag_printf("%d:%d:%d ",
CYG_PCI_DEV_GET_BUS(devid),
CYG_PCI_DEV_GET_DEV(devfn),
CYG_PCI_DEV_GET_FN(devfn));
diag_printf("Vendor[%04x] Device[%04x] Type[%02x] Class[%06x]\n",
dev_info.vendor,
dev_info.device,
dev_info.header_type,
(dev_info.class_rev >> 8) & 0xffffff);
if (dev_info.command & CYG_PCI_CFG_COMMAND_ACTIVE) {
// dump bars
for (i = 0; i < CYG_PCI_MAX_BAR; i++)
if (dev_info.base_address[i])
diag_printf(" BAR%d: %08x\n", i, dev_info.base_address[i]);
}
}
}
externC void
hal_ppc405_pci_init(void)
{
static int _init = 0;
cyg_uint8 next_bus;
cyg_uint32 cmd_state, bridge_state;
if (_init) return;
_init = 1;
// Configure PCI bridge
HAL_WRITE_UINT32LE(PCIL0_PMM0PCILA, 0);
HAL_WRITE_UINT32LE(PCIL0_PMM0PCIHA, 0);
HAL_WRITE_UINT32LE(PCIL0_PMM0LA, HAL_PCI_PHYSICAL_MEMORY_BASE);
HAL_WRITE_UINT32LE(PCIL0_PMM0MA, ~(0x10000000-1) | 0x00000001);
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_1, 0);
HAL_WRITE_UINT32LE(PCIL0_PTM1LA, 0);
HAL_WRITE_UINT32LE(PCIL0_PTM1MS, ~(0x10000000-1) | 0x00000001);
// Indicate that the bridge has been configured
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state);
bridge_state |= 0x0001;
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state);
// Setup for bus mastering
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND, cmd_state);
cyg_pci_init();
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
#if defined(CYGPKG_IO_PCI_DEBUG)
diag_printf("Configure PCI bus\n");
#endif
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
// Setup latency timer field
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
#if defined(CYGSEM_HAL_POWERPC_PPC405_PCI_SHOW_BUS)
if (1) {
cyg_uint8 req;
cyg_uint8 devfn;
cyg_pci_device_id devid;
cyg_pci_device dev_info;
int i;
devid = CYG_PCI_DEV_MAKE_ID(next_bus-1, 0) | CYG_PCI_NULL_DEVFN;
while (cyg_pci_find_next(devid, &devid)) {
devfn = CYG_PCI_DEV_GET_DEVFN(devid);
cyg_pci_get_device_info(devid, &dev_info);
HAL_PCI_CFG_READ_UINT8(0, devfn, CYG_PCI_CFG_INT_PIN, req);
diag_printf("\n");
diag_printf("Bus: %d", CYG_PCI_DEV_GET_BUS(devid));
diag_printf(", PCI Device: %d", CYG_PCI_DEV_GET_DEV(devfn));
diag_printf(", PCI Func: %d\n", CYG_PCI_DEV_GET_FN(devfn));
diag_printf(" Vendor Id: 0x%04X", dev_info.vendor);
diag_printf(", Device Id: 0x%04X", dev_info.device);
diag_printf(", Command: 0x%04X", dev_info.command);
diag_printf(", IRQ: %d\n", req);
for (i = 0; i < dev_info.num_bars; i++) {
diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
dev_info.base_size[i], dev_info.base_map[i]);
}
}
}
#endif
}
externC void
_csb281_pci_init(void)
{
static int _init = 0;
cyg_uint8 next_bus;
cyg_uint32 cmd_state;
if (_init) return;
_init = 1;
// Initialize PCI support
cyg_pci_init();
// Setup for bus mastering
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND, cmd_state);
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
// Force PCI-side window to 0
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0, 0x01);
// Enable bus mastering from host
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
// Setup latency timer field
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
if (0){
cyg_uint8 devfn;
cyg_pci_device_id devid;
cyg_pci_device dev_info;
int i;
devid = CYG_PCI_DEV_MAKE_ID(next_bus-1, 0) | CYG_PCI_NULL_DEVFN;
while (cyg_pci_find_next(devid, &devid)) {
devfn = CYG_PCI_DEV_GET_DEVFN(devid);
cyg_pci_get_device_info(devid, &dev_info);
diag_printf("\n");
diag_printf("Bus: %d\n", CYG_PCI_DEV_GET_BUS(devid));
diag_printf("PCI Device: %d\n", CYG_PCI_DEV_GET_DEV(devfn));
diag_printf("PCI Func : %d\n", CYG_PCI_DEV_GET_FN(devfn));
diag_printf("Vendor Id : 0x%08X\n", dev_info.vendor);
diag_printf("Device Id : 0x%08X\n", dev_info.device);
for (i = 0; i < dev_info.num_bars; i++) {
diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
dev_info.base_size[i], dev_info.base_map[i]);
}
}
}
// Configure interrupts (high level)?
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI0, 1, 1);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI1, 1, 1);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 1);
}
void slowPoll( void )
{
RANDOM_STATE randomState;
BYTE buffer[ RANDOM_BUFSIZE ];
cyg_handle_t hThread = 0;
cyg_uint16 threadID = 0;
#ifdef CYGPKG_IO_PCI
cyg_pci_device_id pciDeviceID;
#endif /* CYGPKG_IO_PCI */
#ifdef CYGPKG_POWER
PowerController *powerControllerInfo;
#endif /* CYGPKG_POWER */
int itemsAdded = 0, iterationCount;
initRandomData( randomState, buffer, RANDOM_BUFSIZE );
/* Get the thread handle, ID, state, priority, and stack usage for
every thread in the system */
for( iterationCount = 0;
cyg_thread_get_next( &hThread, &threadID ) && \
iterationCount < FAILSAFE_ITERATIONS_MED;
iterationCount++ )
{
cyg_thread_info threadInfo;
if( !cyg_thread_get_info( hThread, threadID, &threadInfo ) )
continue;
addRandomData( randomState, &threadInfo, sizeof( cyg_thread_info ) );
itemsAdded++;
}
/* Walk the power-management info getting the power-management state for
each device. This works a bit strangely, the power controller
information is a static table created at system build time so all that
we're doing is walking down an array getting one entry after another */
#ifdef CYGPKG_POWER
for( powerControllerInfo = &( __POWER__[ 0 ] ), iterationCount = 0;
powerControllerInfo != &( __POWER_END__ ) && \
iterationCount < FAILSAFE_ITERATIONS_MED;
powerControllerInfo++, iterationCount++ )
{
const PowerMode power_get_controller_mode( powerControllerInfo );
addRandomValue( randomState, PowerMode );
}
#endif /* CYGPKG_POWER */
/* Add PCI device information if there's PCI support present */
#ifdef CYGPKG_IO_PCI
if( cyg_pci_find_next( CYG_PCI_NULL_DEVID, &pciDeviceID ) )
{
iterationCount = 0;
do
{
cyg_pci_device pciDeviceInfo;
cyg_pci_get_device_info( pciDeviceID, &pciDeviceInfo );
addRandomValue( randomState, PowerMode );
addRandomData( randomState, &pciDeviceInfo,
sizeof( cyg_pci_device ) );
itemsAdded++;
}
while( cyg_pci_find_next( pciDeviceID, &pciDeviceID ) && \
iterationCount++ < FAILSAFE_ITERATIONS_MED );
}
#endif /* CYGPKG_IO_PCI */
/* eCOS also has a CPU load-monitoring facility that we could in theory
use as a source of entropy but this is really meant for performance-
monitoring and isn't very suitable for use as an entropy source. The
way this works is that your first call a calibration function
cyg_cpuload_calibrate() and then when it you want to get load
statistics call cyg_cpuload_create()/cyg_cpuload_get()/
cyg_cpuload_delete(), with get() returning the load over a 0.1s, 1s,
and 10s interval. The only one of these capabilities that's even
potentially usable is cyg_cpuload_calibrate() and even that's rather
dubious for general use since it runs a thread at the highest priority
level for 0.1s for calibration purposes and measures the elapsed tick
count, which will hardly endear us to other threads in the system.
It's really meant for development-mode load measurements and can't
safely be used as an entropy source */
/* Flush any remaining data through and produce an estimate of its
value. Unlike its use in standard OSes this isn't really a true
estimate since virtually all of the entropy is coming from the seed
file, all this does is complete the seed-file quality estimate to
make sure that we don't fail the entropy test */
endRandomData( randomState, ( itemsAdded > 5 ) ? 20 : 0 );
}