void dc_set_loopback(struct channel *sc, u32 mode)
{
u32 val;
switch (mode) {
case SBE_2T3E3_21143_VAL_LOOPBACK_OFF:
case SBE_2T3E3_21143_VAL_LOOPBACK_INTERNAL:
break;
default:
return;
}
/* select loopback mode */
val = dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
~SBE_2T3E3_21143_VAL_OPERATING_MODE;
val |= mode;
dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, val);
if (mode == SBE_2T3E3_21143_VAL_LOOPBACK_OFF)
dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
else
dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
}
void dc_set_loopback(struct channel *sc, u32 mode)
{
u32 val;
switch (mode) {
case SBE_2T3E3_21143_VAL_LOOPBACK_OFF:
case SBE_2T3E3_21143_VAL_LOOPBACK_INTERNAL:
break;
default:
return;
}
#if 0
/* restart SIA */
dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY,
SBE_2T3E3_21143_VAL_SIA_RESET);
udelay(1000);
dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY,
SBE_2T3E3_21143_VAL_SIA_RESET);
#endif
/* select loopback mode */
val = dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
~SBE_2T3E3_21143_VAL_OPERATING_MODE;
val |= mode;
dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, val);
if (mode == SBE_2T3E3_21143_VAL_LOOPBACK_OFF)
dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
else
dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
}
void dc_receiver_onoff(struct channel *sc, u32 mode)
{
u32 i, state = 0;
if (sc->p.receiver_on == mode)
return;
switch (mode) {
case SBE_2T3E3_OFF:
if (dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
SBE_2T3E3_21143_VAL_RECEIVE_START) {
dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
SBE_2T3E3_21143_VAL_RECEIVE_START);
for (i = 0; i < 16; i++) {
state = dc_read(sc->addr, SBE_2T3E3_21143_REG_STATUS) &
SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STATE;
if (state == SBE_2T3E3_21143_VAL_RX_STOPPED)
break;
udelay(5);
}
if (state != SBE_2T3E3_21143_VAL_RX_STOPPED)
dev_warn(&sc->pdev->dev, "SBE 2T3E3: Rx failed to stop\n");
else
dev_info(&sc->pdev->dev, "SBE 2T3E3: Rx off\n");
}
break;
case SBE_2T3E3_ON:
dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
SBE_2T3E3_21143_VAL_RECEIVE_START);
udelay(100);
dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_POLL_DEMAND, 0xFFFFFFFF);
break;
default:
return;
}
sc->p.receiver_on = mode;
}
static u32 serialrom_read_bit(struct channel *channel)
{
unsigned long addr = channel->card->bootrom_addr;
u32 bit;
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_READ_OPERATION |
SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CLOCK |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock high */
bit = (dc_read(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT) &
SBE_2T3E3_21143_VAL_SERIAL_ROM_DATA_OUT) > 0 ? 1 : 0;
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_READ_OPERATION |
SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
return bit;
}
u32 bootrom_read(struct channel *channel, u32 reg)
{
unsigned long addr = channel->card->bootrom_addr;
u32 result;
/* select BootROM address */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_PROGRAMMING_ADDRESS, reg & 0x3FFFF);
/* select reading from BootROM */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_READ_OPERATION |
SBE_2T3E3_21143_VAL_BOOT_ROM_SELECT);
udelay(2); /* 20 PCI cycles */
/* read from BootROM */
result = dc_read(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT) & 0xff;
/* reset CSR9 */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
return result;
}
void t3e3_reg_read(struct channel *sc, u32 *reg, u32 *val)
{
u32 i;
*val = 0;
switch (reg[0]) {
case SBE_2T3E3_CHIP_21143:
if (!(reg[1] & 7))
*val = dc_read(sc->addr, reg[1] / 8);
break;
case SBE_2T3E3_CHIP_CPLD:
for (i = 0; i < SBE_2T3E3_CPLD_REG_MAX; i++)
if (cpld_reg_map[i][sc->h.slot] == reg[1]) {
*val = cpld_read(sc, i);
break;
}
break;
case SBE_2T3E3_CHIP_FRAMER:
for (i = 0; i < SBE_2T3E3_FRAMER_REG_MAX; i++)
if (t3e3_framer_reg_map[i] == reg[1]) {
*val = exar7250_read(sc, i);
break;
}
break;
case SBE_2T3E3_CHIP_LIU:
for (i = 0; i < SBE_2T3E3_LIU_REG_MAX; i++)
if (t3e3_liu_reg_map[i] == reg[1]) {
*val = exar7300_read(sc, i);
break;
}
break;
default:
break;
}
}
int copyfile(int src, int dest, size_t bufsize, off64_t *size, off64_t total_size)
{
ssize_t n, m ;
char * cpbuf;
size_t count;
off64_t total_bytes = 0;
size_t off;
if ( ( cpbuf = malloc(bufsize) ) == NULL ) {
perror("malloc");
return -1;
}
if( is_feedback_enabled) {
hash_printing_accept_byte_count(progress_set, 0, total_size);
}
do{
off = 0;
do{
n = dc_read(src, cpbuf + off, bufsize - off);
if( n <=0 ) break;
off += n;
} while (off != bufsize );
/* do not continue if read fails*/
if (n < 0) {
/* Read failed. */
free(cpbuf);
return -1;
}
if (off > 0) {
count = 0;
while ((count != off) && ((m = dc_write(dest, cpbuf+count, off-count)) > 0)) {
total_bytes += (off64_t)m;
count += m;
if( is_feedback_enabled) {
hash_printing_accept_byte_count(progress_set, total_bytes, total_size);
}
}
if (m < 0) {
/* Write failed. */
free(cpbuf);
return -1;
}
}
} while (n != 0);
if(size != NULL) {
*size = total_bytes;
}
if( is_feedback_enabled) {
hash_printing_accept_byte_count( progress_finished, 0, 0);
}
free(cpbuf);
return 0;
}
