/* Initialize and fire up non-boot processors */
void
cpu_mp_start(void)
{
int error, i;
mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
/* Reserve memory for application processors */
for(i = 0; i < (mp_ncpus - 1); i++)
dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
M_WAITOK | M_ZERO);
dcache_wbinv_poc_all();
/* Initialize boot code and start up processors */
platform_mp_start_ap();
/* Check if ap's started properly */
error = check_ap();
if (error)
printf("WARNING: Some AP's failed to start\n");
else
for (i = 1; i < mp_ncpus; i++)
CPU_SET(i, &all_cpus);
}
void
aw_mp_start_ap(platform_t plat)
{
bus_space_handle_t cpucfg;
bus_space_handle_t prcm;
int i, j, soc_family;
uint32_t val;
soc_family = allwinner_soc_family();
if (soc_family == ALLWINNERSOC_SUN7I) {
if (bus_space_map(fdtbus_bs_tag, A20_CPUCFG_BASE, CPUCFG_SIZE,
0, &cpucfg) != 0)
panic("Couldn't map the CPUCFG\n");
} else {
if (bus_space_map(fdtbus_bs_tag, CPUCFG_BASE, CPUCFG_SIZE,
0, &cpucfg) != 0)
panic("Couldn't map the CPUCFG\n");
if (bus_space_map(fdtbus_bs_tag, PRCM_BASE, PRCM_SIZE, 0,
&prcm) != 0)
panic("Couldn't map the PRCM\n");
}
dcache_wbinv_poc_all();
bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_P_REG0,
pmap_kextract((vm_offset_t)mpentry));
/*
* Assert nCOREPORESET low and set L1RSTDISABLE low.
* Ensure DBGPWRDUP is set to LOW to prevent any external
* debug access to the processor.
*/
for (i = 1; i < mp_ncpus; i++)
bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU_RST_CTL(i), 0);
/* Set L1RSTDISABLE low */
val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_GENCTL);
for (i = 1; i < mp_ncpus; i++)
val &= ~(1 << i);
bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_GENCTL, val);
/* Set DBGPWRDUP low */
val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1);
for (i = 1; i < mp_ncpus; i++)
val &= ~(1 << i);
bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1, val);
/* Release power clamp */
for (i = 1; i < mp_ncpus; i++)
for (j = 0; j <= CPU_PWR_CLAMP_STEPS; j++) {
if (soc_family != ALLWINNERSOC_SUN7I) {
bus_space_write_4(fdtbus_bs_tag, prcm,
CPU_PWR_CLAMP(i), 0xff >> j);
} else {
void
exynos5_mp_start_ap(platform_t plat)
{
bus_addr_t sysram, pmu;
int err, i, j;
int status;
int reg;
err = bus_space_map(fdtbus_bs_tag, EXYNOS_PMU_BASE, 0x20000, 0, &pmu);
if (err != 0)
panic("Couldn't map pmu\n");
if (exynos_get_soc_id() == EXYNOS5420_SOC_ID)
reg = EXYNOS5420_SYSRAM_NS;
else
reg = EXYNOS_SYSRAM;
err = bus_space_map(fdtbus_bs_tag, reg, 0x100, 0, &sysram);
if (err != 0)
panic("Couldn't map sysram\n");
/* Give power to CPUs */
for (i = 1; i < mp_ncpus; i++) {
bus_space_write_4(fdtbus_bs_tag, pmu, CORE_CONFIG(i),
CORE_PWR_EN);
for (j = 10; j >= 0; j--) {
status = bus_space_read_4(fdtbus_bs_tag, pmu,
CORE_STATUS(i));
if ((status & CORE_PWR_EN) == CORE_PWR_EN)
break;
DELAY(10);
if (j == 0)
printf("Can't power on CPU%d\n", i);
}
}
bus_space_write_4(fdtbus_bs_tag, sysram, 0x0,
pmap_kextract((vm_offset_t)mpentry));
dcache_wbinv_poc_all();
dsb();
sev();
bus_space_unmap(fdtbus_bs_tag, sysram, 0x100);
bus_space_unmap(fdtbus_bs_tag, pmu, 0x20000);
}
void
zynq7_mp_start_ap(platform_t plat)
{
bus_space_handle_t scu_handle;
bus_space_handle_t ocm_handle;
uint32_t scu_ctrl;
/* Map in SCU control register. */
if (bus_space_map(fdtbus_bs_tag, SCU_CONTROL_REG, 4,
0, &scu_handle) != 0)
panic("platform_mp_start_ap: Couldn't map SCU config reg\n");
/* Set SCU enable bit. */
scu_ctrl = bus_space_read_4(fdtbus_bs_tag, scu_handle, 0);
scu_ctrl |= SCU_CONTROL_ENABLE;
bus_space_write_4(fdtbus_bs_tag, scu_handle, 0, scu_ctrl);
bus_space_unmap(fdtbus_bs_tag, scu_handle, 4);
/* Map in magic location to give entry address to CPU1. */
if (bus_space_map(fdtbus_bs_tag, ZYNQ7_CPU1_ENTRY, 4,
0, &ocm_handle) != 0)
panic("platform_mp_start_ap: Couldn't map OCM\n");
/* Write start address for CPU1. */
bus_space_write_4(fdtbus_bs_tag, ocm_handle, 0,
pmap_kextract((vm_offset_t)mpentry));
bus_space_unmap(fdtbus_bs_tag, ocm_handle, 4);
/*
* The SCU is enabled above but I think the second CPU doesn't
* turn on filtering until after the wake-up below. I think that's why
* things don't work if I don't put these cache ops here. Also, the
* magic location, 0xfffffff0, isn't in the SCU's filtering range so it
* needs a write-back too.
*/
dcache_wbinv_poc_all();
/* Wake up CPU1. */
dsb();
sev();
}
int
pmsu_boot_secondary_cpu(void)
{
bus_space_handle_t vaddr;
int rv;
rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_PMSU_BASE, MV_PMSU_REGS_LEN,
0, &vaddr);
if (rv != 0)
return (rv);
/* Boot cpu1 */
bus_space_write_4(fdtbus_bs_tag, vaddr, PMSU_BOOT_ADDR_REDIRECT_OFFSET(1),
pmap_kextract((vm_offset_t)mpentry));
dcache_wbinv_poc_all();
armv7_sev();
bus_space_unmap(fdtbus_bs_tag, vaddr, MV_PMSU_REGS_LEN);
return (0);
}
void
platform_mp_start_ap(void)
{
bus_space_handle_t scu;
bus_space_handle_t src;
uint32_t val;
int i;
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
panic("Couldn't map the SCU\n");
if (bus_space_map(fdtbus_bs_tag, SRC_PHYSBASE, SRC_SIZE, 0, &src) != 0)
panic("Couldn't map the system reset controller (SRC)\n");
/*
* Invalidate SCU cache tags. The 0x0000ffff constant invalidates all
* ways on all cores 0-3. Per the ARM docs, it's harmless to write to
* the bits for cores that are not present.
*/
bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff);
/*
* Erratum ARM/MP: 764369 (problems with cache maintenance).
* Setting the "disable-migratory bit" in the undocumented SCU
* Diagnostic Control Register helps work around the problem.
*/
val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL,
val | SCU_DIAG_DISABLE_MIGBIT);
/*
* Enable the SCU, then clean the cache on this core. After these two
* operations the cache tag ram in the SCU is coherent with the contents
* of the cache on this core. The other cores aren't running yet so
* their caches can't contain valid data yet, but we've initialized
* their SCU tag ram above, so they will be coherent from startup.
*/
val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG,
val | SCU_CONTROL_ENABLE);
dcache_wbinv_poc_all();
/*
* For each AP core, set the entry point address and argument registers,
* and set the core-enable and core-reset bits in the control register.
*/
val = bus_space_read_4(fdtbus_bs_tag, src, SRC_CONTROL_REG);
for (i=1; i < mp_ncpus; i++) {
bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR0_C1FUNC + 8*i,
pmap_kextract((vm_offset_t)mpentry));
bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR1_C1ARG + 8*i, 0);
val |= ((1 << (SRC_CONTROL_C1ENA_SHIFT - 1 + i )) |
( 1 << (SRC_CONTROL_C1RST_SHIFT - 1 + i)));
}
bus_space_write_4(fdtbus_bs_tag, src, SRC_CONTROL_REG, val);
dsb();
sev();
bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
bus_space_unmap(fdtbus_bs_tag, src, SRC_SIZE);
}
void
platform_mp_start_ap(void)
{
bus_space_handle_t scu;
bus_space_handle_t imem;
bus_space_handle_t pmu;
uint32_t val;
int i;
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
panic("Could not map the SCU");
if (bus_space_map(fdtbus_bs_tag, IMEM_PHYSBASE,
IMEM_SIZE, 0, &imem) != 0)
panic("Could not map the IMEM");
if (bus_space_map(fdtbus_bs_tag, PMU_PHYSBASE, PMU_SIZE, 0, &pmu) != 0)
panic("Could not map the PMU");
/*
* Invalidate SCU cache tags. The 0x0000ffff constant invalidates all
* ways on all cores 0-3. Per the ARM docs, it's harmless to write to
* the bits for cores that are not present.
*/
bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff);
/* Make sure all cores except the first are off */
val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
for (i = 1; i < mp_ncpus; i++)
val |= 1 << i;
bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val);
/* Enable SCU power domain */
val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
val &= ~PMU_PWRDN_SCU;
bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val);
/* Enable SCU */
val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG,
val | SCU_CONTROL_ENABLE);
/*
* Cores will execute the code which resides at the start of
* the on-chip bootram/sram after power-on. This sram region
* should be reserved and the trampoline code that directs
* the core to the real startup code in ram should be copied
* into this sram region.
*
* First set boot function for the sram code.
*/
mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry);
/* Copy trampoline to sram, that runs during startup of the core */
bus_space_write_region_4(fdtbus_bs_tag, imem, 0,
(uint32_t *)&rk30xx_boot2, 8);
dcache_wbinv_poc_all();
/* Start all cores */
val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
for (i = 1; i < mp_ncpus; i++)
val &= ~(1 << i);
bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val);
dsb();
sev();
bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
bus_space_unmap(fdtbus_bs_tag, imem, IMEM_SIZE);
bus_space_unmap(fdtbus_bs_tag, pmu, PMU_SIZE);
}
void
platform_mp_start_ap(void)
{
uint32_t reg, *src, *dst, cpu_num, div_val, cputype;
vm_offset_t pmu_boot_off;
/*
* Initialization procedure depends on core revision,
* in this step CHIP ID is checked to choose proper procedure
*/
cputype = cpu_ident();
cputype &= CPU_ID_CPU_MASK;
/*
* Set the PA of CPU0 Boot Address Redirect register used in
* mptramp according to the actual SoC registers' base address.
*/
pmu_boot_off = (CPU_PMU(0) - MV_BASE) + CPU_PMU_BOOT;
mptramp_pmu_boot = fdt_immr_pa + pmu_boot_off;
dst = pmap_mapdev(0xffff0000, PAGE_SIZE);
for (src = (uint32_t *)mptramp; src < (uint32_t *)mptramp_end;
src++, dst++) {
*dst = *src;
}
pmap_unmapdev((vm_offset_t)dst, PAGE_SIZE);
if (cputype == CPU_ID_MV88SV584X_V7) {
/* Core rev A0 */
div_val = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);
div_val &= 0x3f;
for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) {
reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);
reg &= CPU_DIVCLK_MASK(cpu_num);
reg |= div_val << (cpu_num * 8);
write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg);
}
} else {
/* Core rev Z1 */
div_val = 0x01;
if (mp_ncpus > 1) {
reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0);
reg &= CPU_DIVCLK_MASK(3);
reg |= div_val << 24;
write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0, reg);
}
for (cpu_num = 2; cpu_num < mp_ncpus; cpu_num++ ) {
reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);
reg &= CPU_DIVCLK_MASK(cpu_num);
reg |= div_val << (cpu_num * 8);
write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg);
}
}
reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0);
reg |= ((0x1 << (mp_ncpus - 1)) - 1) << 21;
write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);
reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0);
reg |= 0x01000000;
write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);
DELAY(100);
reg &= ~(0xf << 21);
write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);
DELAY(100);
bus_space_write_4(fdtbus_bs_tag, MV_BASE, CPU_RESUME_CONTROL, 0);
for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ )
bus_space_write_4(fdtbus_bs_tag, CPU_PMU(cpu_num), CPU_PMU_BOOT,
pmap_kextract((vm_offset_t)mpentry));
dcache_wbinv_poc_all();
for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ )
bus_space_write_4(fdtbus_bs_tag, MP, MP_SW_RESET(cpu_num), 0);
/* XXX: Temporary workaround for hangup after releasing AP's */
wmb();
DELAY(10);
armadaxp_init_coher_fabric();
}
