static void spl_dram_init(void)
{
if (is_mx6dq())
ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
else if (is_mx6dqp())
ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
}
void uemd_em_init(void)
{
MEM(0x2003c050)=0x9; //DDR PHY ODT ON
ddr_init(DMC0_APB_BASE);
MEM(0x2003c064)=0x9; //DDR PHY ODT ON
ddr_init(DMC1_APB_BASE);
}
void spl_dram_init(void)
{
/* ddr init */
if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
ddr_init(&dram_timing);
else
ddr_init(&dram_timing_b0);
}
void arm_boot(void)
{
int *ddr_p = (void *)0x57000000;
WTCON = 0;
__asm__ __volatile__(
"mrs r0, cpsr\n"
"bic r0, r0, #0xc0\n"
"msr cpsr, r0\n"
:
:
:"r0"
);
clock_init();
ddr_init();
nand_init();
led_init();
nand_read(ddr_p, 0, 0x40000);
__asm__ __volatile__(
"mov sp, #0x58000000\n"
"mov lr, pc\n"
"ldr pc, =main\n"
"there:\n"
"b there\n"
);
}
void startup(void)
{
#if defined(CONFIG_BAREMETAL_ENABLE_DCACHE)
init_tlb(main_tlb);
assign_tlb(main_tlb);
enable_cache();
#elif defined(CONFIG_BAREMETAL_ENABLE_ICACHE)
enable_cache();
#endif
#if defined(CONFIG_BAREMETAL_DDR_INIT)
ddr_init();
#endif
#if defined(CONFIG_BAREMETAL_PLL0_INIT)
pll0_init();
#endif
#if defined(CONFIG_BAREMETAL_UART_BASIC)
uart_basic_init();
#endif
main();
halt();
}
int board_early_init_f(void)
{
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
#endif
ddr_init();
return 0;
}
STATIC_PREFIX void debugrom_ddr_init(int argc, char * argv[])
{
unsigned i=0;
if(argv[1])
get_dword(argv[1],&i);
//ddr_pll_init(&__ddr_setting);
ddr_init(i);
}
static void spl_dram_init(void)
{
int minc, maxc;
switch (get_cpu_temp_grade(&minc, &maxc)) {
case TEMP_COMMERCIAL:
case TEMP_EXTCOMMERCIAL:
puts("Commercial temperature grade DDR3 timings.\n");
ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
break;
case TEMP_INDUSTRIAL:
case TEMP_AUTOMOTIVE:
default:
puts("Industrial temperature grade DDR3 timings.\n");
ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
break;
};
udelay(100);
}
void board_init_f(ulong dummy)
{
arch_cpu_init();
gpr_init();
board_early_init_f();
timer_init();
preloader_console_init();
ddr_init();
memset(__bss_start, 0, __bss_end - __bss_start);
board_init_r(NULL, 0);
}
static int __init rk3188_ddr_init(void)
{
if (cpu_is_rk3188()) {
ddr_change_freq = _ddr_change_freq;
ddr_round_rate = _ddr_round_rate;
ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
ddr_init(DDR3_DEFAULT, 300);
}
return 0;
}
void spl_board_init(void)
{
/* First of all silence buzzer controlled by GPO_20 */
writel((1 << 20), &gpio->p3_outp_clr);
lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
preloader_console_init();
ddr_init(&dram_64mb);
/*
* NAND initialization is done by nand_init(),
* here just enable NAND SLC clocks
*/
lpc32xx_slc_nand_init();
}
static int __init rockchip_ddr_probe(struct platform_device *pdev)
{
struct device_node *np;
np = pdev->dev.of_node;
ddr_data =
devm_kzalloc(&pdev->dev, sizeof(struct rockchip_ddr), GFP_KERNEL);
if (!ddr_data) {
dev_err(&pdev->dev, "no memory for state\n");
return -ENOMEM;
}
/* ddrpctl */
ddr_data->ddrpctl_regs =
syscon_regmap_lookup_by_phandle(np, "rockchip,ddrpctl");
if (IS_ERR(ddr_data->ddrpctl_regs)) {
dev_err(&pdev->dev, "%s: could not find ddrpctl dt node\n",
__func__);
return -ENXIO;
}
/* grf */
ddr_data->grf_regs =
syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
if (IS_ERR(ddr_data->grf_regs)) {
dev_err(&pdev->dev, "%s: could not find grf dt node\n",
__func__);
return -ENXIO;
}
/* msch */
ddr_data->msch_regs =
syscon_regmap_lookup_by_phandle(np, "rockchip,msch");
if (IS_ERR(ddr_data->msch_regs)) {
dev_err(&pdev->dev, "%s: could not find msch dt node\n",
__func__);
return -ENXIO;
}
platform_set_drvdata(pdev, ddr_data);
ddr_change_freq = _ddr_change_freq;
ddr_round_rate = _ddr_round_rate;
ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
ddr_bandwidth_get = _ddr_bandwidth_get;
ddr_recalc_rate = _ddr_recalc_rate;
ddr_init(DDR3_DEFAULT, 0);
pr_info("%s: success\n", __func__);
return 0;
}
static int __init rk3288_ddr_init(void)
{
if (cpu_is_rk3288()
#ifdef CONFIG_ARM_TRUSTZONE
&& false
#endif
)
{
ddr_change_freq = _ddr_change_freq;
ddr_round_rate = _ddr_round_rate;
ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
ddr_bandwidth_get = _ddr_bandwidth_get;
ddr_init(DDR3_DEFAULT, 0);
}
return 0;
}
void
main_sh (void)
{
led(0x40);
uart_set_baudrate ();
led(0x042);
putstr ("CPU tests passed\n");
led(0x043);
putstr ("DDR Init\n");
led(0x042);
ddr_init ();
putstr ("GDB Stub for HS-2J0 SH2 ROM\n");
putstr (version_string);
led(0x50);
}
int main(int argc, char *argv[])
{
int i = 0;
char *p=(void *)0x52000000;
char *buf=(void *)0x51000000;
WTCON=0;
clock_init();
uart_init();
ddr_init();
nand_init();
memcpy(buf,"helloworld\n",12);
memset(p,0,12);
nand_erase(0x200000,12);
nand_write(buf,0x200000,12);
nand_read(p,0x200000,12);
uprintf(p);
uprintf("\n");
return 0;
}
static int ddr_init_resume(struct platform_device *pdev)
{
ddr_init(DDR3_DEFAULT, 0);
return 0;
}
static int bcm_download_config_file(struct bcm_mini_adapter *Adapter, struct bcm_firmware_info *psFwInfo)
{
int retval = STATUS_SUCCESS;
B_UINT32 value = 0;
if (Adapter->pstargetparams == NULL) {
Adapter->pstargetparams = kmalloc(sizeof(STARGETPARAMS), GFP_KERNEL);
if (Adapter->pstargetparams == NULL)
return -ENOMEM;
}
if (psFwInfo->u32FirmwareLength != sizeof(STARGETPARAMS))
return -EIO;
retval = copy_from_user(Adapter->pstargetparams, psFwInfo->pvMappedFirmwareAddress, psFwInfo->u32FirmwareLength);
if (retval) {
kfree(Adapter->pstargetparams);
Adapter->pstargetparams = NULL;
return -EFAULT;
}
/* Parse the structure and then Download the Firmware */
beceem_parse_target_struct(Adapter);
/* Initializing the NVM. */
BcmInitNVM(Adapter);
retval = InitLedSettings(Adapter);
if (retval) {
BCM_DEBUG_PRINT(Adapter, DBG_TYPE_INITEXIT, MP_INIT, DBG_LVL_ALL, "INIT LED Failed\n");
return retval;
}
if (Adapter->LEDInfo.led_thread_running & BCM_LED_THREAD_RUNNING_ACTIVELY) {
Adapter->LEDInfo.bLedInitDone = FALSE;
Adapter->DriverState = DRIVER_INIT;
wake_up(&Adapter->LEDInfo.notify_led_event);
}
if (Adapter->LEDInfo.led_thread_running & BCM_LED_THREAD_RUNNING_ACTIVELY) {
Adapter->DriverState = FW_DOWNLOAD;
wake_up(&Adapter->LEDInfo.notify_led_event);
}
/* Initialize the DDR Controller */
retval = ddr_init(Adapter);
if (retval) {
BCM_DEBUG_PRINT (Adapter, DBG_TYPE_INITEXIT, MP_INIT, DBG_LVL_ALL, "DDR Init Failed\n");
return retval;
}
value = 0;
wrmalt(Adapter, EEPROM_CAL_DATA_INTERNAL_LOC - 4, &value, sizeof(value));
wrmalt(Adapter, EEPROM_CAL_DATA_INTERNAL_LOC - 8, &value, sizeof(value));
if (Adapter->eNVMType == NVM_FLASH) {
retval = PropagateCalParamsFromFlashToMemory(Adapter);
if (retval) {
BCM_DEBUG_PRINT(Adapter, DBG_TYPE_INITEXIT, MP_INIT, DBG_LVL_ALL, "propagaion of cal param failed with status :%d", retval);
return retval;
}
}
retval = buffDnldVerify(Adapter, (PUCHAR)Adapter->pstargetparams, sizeof(STARGETPARAMS), CONFIG_BEGIN_ADDR);
if (retval)
BCM_DEBUG_PRINT(Adapter, DBG_TYPE_INITEXIT, MP_INIT, DBG_LVL_ALL, "configuration file not downloaded properly");
else
Adapter->bCfgDownloaded = TRUE;
return retval;
}
/*FUNCTION*---------------------------------------------------------------------
*
* Function Name : init_hardware
* Returned Value : void
* Comments :
* Initialize device.
*
*END*-------------------------------------------------------------------------*/
void init_hardware(void)
{
clocks_init();
ddr_init();
}
