void uart_init(int idx)
{
struct am335x_uart *uart = uart_platform_baseptr(idx);
uint16_t div = (uint16_t) uart_baudrate_divisor(
default_baudrate(), uart_platform_refclk(), 16);
am335x_uart_init(uart, div);
}
void uart_init(int idx)
{
unsigned int div;
div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK,
BAUDRATE_OVERSAMPLE);
uart8250_init(uart_platform_base(idx), div);
}
void uart_init(int idx)
{
unsigned int div;
div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(),
uart_input_clock_divider());
uart8250_init(uart_platform_base(idx), div);
}
void uart_init(int idx)
{
struct a10_uart *uart_base = uart_platform_baseptr(idx);
/* Use default 8N1 encoding */
a10_uart_configure(uart_base, default_baudrate(),
8, UART_PARITY_NONE, 1);
a10_uart_enable_fifos(uart_base);
}
void uart_init(int idx)
{
void *base = uart_platform_baseptr(idx);
if (!base)
return;
unsigned int div;
div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), 16);
uart8250_mem_init(base, div);
}
void uart_fill_lb(void *data)
{
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_IO_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data);
}
/* TODO: Implement function */
void uart_fill_lb(void *data)
{
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = (uint32_t)UART1_DM_BASE;
serial.baud = default_baudrate();
serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
}
void uart_fill_lb(void *data)
{
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_IO_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
serial.regwidth = 1;
serial.input_hertz = uart_platform_refclk();
serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data);
}
void uart_fill_lb(void *data)
{
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
if (IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
serial.regwidth = sizeof(uint32_t);
else
serial.regwidth = sizeof(uint8_t);
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
}
static void serial_setbrg_dev(struct s5p_uart *uart)
{
u32 uclk;
u32 val;
// All UARTs share the same clock.
uclk = clock_get_periph_rate(PERIPH_ID_UART3);
val = uclk / default_baudrate();
writel(val / 16 - 1, &uart->ubrdiv);
/*
* FIXME(dhendrix): the original uart.h had a "br_rest" value which
* does not seem relevant to the exynos5420... not entirely sure
* where/if we need to worry about it here
*/
#if 0
if (s5p_uart_divslot())
writel(udivslot[val % 16], &uart->rest.slot);
else
writeb(val % 16, &uart->rest.value);
#endif
}
