int bus_minfreq_handle(unsigned int req_value)
{
    return dfs_qos_update(DFS_QOS_ID_BUS_MINFREQ, &bus_minfreq_qos_req_id, req_value);
}
int pwrctrl_dfs_qos_update(unsigned int dev_id, int* req_id, unsigned int req_value)
{
    struct acpufreqinfo *p_freqinfo = (struct acpufreqinfo *)g_dfs_data_addr;
    int ret=0;
    int i=0;
    if(DEVICE_ID_ACPU == dev_id)
    {
    	p_freqinfo->dfs_acpu_freq = req_value;
    	ret=pwrctrl_acpu_dfs_cmd();
    	/*重新投需要的DDR 票*/
    	if((g_acpu_ddr_freqlink.acpu_not_suspend == 1)&&(g_acpu_ddr_freqlink.acpu_ddr_freq_switch == 1))
        {
        	for(i=0;i<10;i++)
        	{
        		if((g_acpu_ddr_freqlink.acpu_ddr_freqlink_cfg[i].cur_acpu_freq) == req_value)
        			break;
        	}
        	if(i == 10)
        	{
        		return -1;
        	}
                   /*最大DDR 票处理*/
        	if(g_acpu_ddr_freqlink.acpu_ddr_freqlink_cfg[i].ddr_max_freq_limit != 0)
            {
                ret=dfs_qos_update(DFS_QOS_ID_DDR_MAXFREQ,&(g_acpu_ddr_freqlink.acpu_ddr_maxfreq_req_id), g_acpu_ddr_freqlink.acpu_ddr_freqlink_cfg[i].ddr_max_freq_limit);
                g_acpu_ddr_freqlink.acpu_ddr_link_max_running_flag = 1;
/*===tele_mntn===*/
#if defined (CONFIG_HISILICON_PLATFORM_TELE_MNTN)
#if defined (CONFIG_HISILICON_PLATFORM_POWER_CONTROL)
                tele_mntn_acpu_ddr_freqlink(PM_QOS_MEMORY_THROUGHPUT_UP_THRESHOLD, g_acpu_ddr_freqlink.acpu_ddr_freqlink_cfg[i].ddr_max_freq_limit);
#endif
#endif
/*===tele_mntn===*/
            }
            else
            {
                if(g_acpu_ddr_freqlink.acpu_ddr_link_max_running_flag == 1)
                {
                    ret=pwrctrl_dfs_qos_update(DEVICE_ID_DDR_MAX,&(g_acpu_ddr_freqlink.acpu_ddr_maxfreq_req_id),ACPU_SUSPEND_RLQOS_DDR_MAX_VALUE);
                    g_acpu_ddr_freqlink.acpu_ddr_link_max_running_flag = 0;
/*===tele_mntn===*/
#if defined (CONFIG_HISILICON_PLATFORM_TELE_MNTN)
#if defined (CONFIG_HISILICON_PLATFORM_POWER_CONTROL)
                    tele_mntn_acpu_ddr_freqlink(PM_QOS_MEMORY_THROUGHPUT_UP_THRESHOLD, ACPU_SUSPEND_RLQOS_DDR_MAX_VALUE);
#endif
#endif
/*===tele_mntn===*/
                }
                else
                {
                    ret = RET_OK;
                }
            }
        	if(RET_OK != ret)
        	{
        		pr_err(" pwrctrl_dfs_qos_update MAX failed .\n");

        	}
                    /*最小DDR 票处理*/
            if(g_acpu_ddr_freqlink.acpu_ddr_freqlink_cfg[i].ddr_min_freq_limit != 0)
            {
                ret=dfs_qos_update(DFS_QOS_ID_DDR_MINFREQ,&(g_acpu_ddr_freqlink.acpu_ddr_minfreq_req_id),g_acpu_ddr_freqlink.acpu_ddr_freqlink_cfg[i].ddr_min_freq_limit);
                g_acpu_ddr_freqlink.acpu_ddr_link_min_running_flag = 1;
/*===tele_mntn===*/
#if defined (CONFIG_HISILICON_PLATFORM_TELE_MNTN)
#if defined (CONFIG_HISILICON_PLATFORM_POWER_CONTROL)
                tele_mntn_acpu_ddr_freqlink(PM_QOS_MEMORY_THROUGHPUT, g_acpu_ddr_freqlink.acpu_ddr_freqlink_cfg[i].ddr_min_freq_limit);
#endif
#endif
/*===tele_mntn===*/
            }
            else
            {
                if(g_acpu_ddr_freqlink.acpu_ddr_link_min_running_flag == 1)
                {
                    ret=pwrctrl_dfs_qos_update(DEVICE_ID_DDR_MIN,&(g_acpu_ddr_freqlink.acpu_ddr_minfreq_req_id),ACPU_SUSPEND_RLQOS_DDR_MIN_VALUE);
                    g_acpu_ddr_freqlink.acpu_ddr_link_min_running_flag = 0;
/*===tele_mntn===*/
#if defined (CONFIG_HISILICON_PLATFORM_TELE_MNTN)
#if defined (CONFIG_HISILICON_PLATFORM_POWER_CONTROL)
                    tele_mntn_acpu_ddr_freqlink(PM_QOS_MEMORY_THROUGHPUT, ACPU_SUSPEND_RLQOS_DDR_MIN_VALUE);
#endif
#endif
/*===tele_mntn===*/
                }
            else
            {
                ret = RET_OK;
            }

            }
        	if(RET_OK != ret)
        	{
        		pr_err(" pwrctrl_dfs_qos_update MIN failed .\n");

        	}
        }
    	return 0;
    }
    else if(DEVICE_ID_DDR_MIN == dev_id)
    {
        return dfs_qos_update(DFS_QOS_ID_DDR_MINFREQ, req_id, req_value);
    }
    else if(DEVICE_ID_DDR_MAX == dev_id)
    {
        return dfs_qos_update(DFS_QOS_ID_DDR_MAXFREQ, req_id, req_value);
    }
    else
    {
        return -1;
    }
}
int ddr_maxfreq_handle(unsigned int req_value)
{
    return dfs_qos_update(DFS_QOS_ID_DDR_MAXFREQ, &ddr_maxfreq_qos_req_id, req_value);
}
int ddr_safefreq_handle(unsigned int freq)
{
    return dfs_qos_update(DFS_QOS_ID_DDR_MAXFREQ, &ddr_maxfreq_qos_req_id, freq);
}
local_t int gpu_maxfreq_notify(struct notifier_block *b, unsigned long req_value,    void *v)
{
    return dfs_qos_update(DFS_QOS_ID_GPU_MAXFREQ, &gpu_maxfreq_qos_req_id, req_value);
}
local_t int bus100M_minfreq_notify(struct notifier_block *b, unsigned long req_value, void *v)
{
    return dfs_qos_update(DFS_QOS_ID_BUS100M_MINFREQ, &bus100M_minfreq_qos_req_id, req_value);
}
int acpu_maxfreq_handle(unsigned int req_value)
{
    return dfs_qos_update(DFS_QOS_ID_ACPU_MAXFREQ, &acpu_maxfreq_qos_req_id, req_value);
}
int acpu_safefreq_handle(unsigned int freq)
{
    return dfs_qos_update(DFS_QOS_ID_ACPU_MAXFREQ, &acpu_maxfreq_qos_req_id, freq);
}
local_t int acpu_minfreq_notify(struct notifier_block *b, unsigned long req_value,    void *v)
{
    return dfs_qos_update(DFS_QOS_ID_ACPU_MINFREQ, &acpu_minfreq_qos_req_id, req_value);
}