e_MQTTSN_RETURNS_t pwmRegisterOD(indextable_t *pIdx)
{
uint16_t base = pIdx->sidx.Base;
uint8_t dio = hal_dio_base2pin(base);
if((dioCheckBase(dio) != 0) || hal_pwm_busy(base))
return MQTTSN_RET_REJ_INV_ID;
dioTake(dio);
hal_pwm_configure(base, (pIdx->sidx.Type == objPinNPN));
pIdx->cbWrite = &pwmWriteOD;
return MQTTSN_RET_ACCEPTED;
}
// Register Object
e_MQTTSN_RETURNS_t serRegisterOD(indextable_t *pIdx)
{
uint8_t port = pIdx->sidx.Base / 10;
uint8_t nBaud = pIdx->sidx.Base % 10;
eObjTyp_t type = pIdx->sidx.Type;
uint8_t TxPin, RxPin;
hal_uart_get_pins(port, &RxPin, &TxPin);
if(type == ObjSerTx)
{
if(dioCheckBase(TxPin) != 0)
return MQTTSN_RET_REJ_INV_ID;
}
else
{
if(dioCheckBase(RxPin) == 2)
return MQTTSN_RET_REJ_INV_ID;
}
if(extSerV[port] != NULL)
{
if(extSerV[port]->nBaud != nBaud)
return MQTTSN_RET_REJ_INV_ID;
if(type == ObjSerTx)
{
if(extSerV[port]->flags & EXTSER_FLAG_TXEN)
return MQTTSN_RET_REJ_INV_ID;
}
else
{
if(extSerV[port]->flags & EXTSER_FLAG_RXEN)
return MQTTSN_RET_REJ_INV_ID;
}
}
else
{
extSerV[port] = mqAlloc(sizeof(EXTSER_VAR_t));
if(extSerV[port] == NULL)
return MQTTSN_RET_REJ_CONG;
extSerV[port]->nBaud = nBaud;
extSerV[port]->flags = 0;
extSerV[port]->pRxBuf = NULL;
extSerV[port]->RxHead = 0;
extSerV[port]->RxTail = 0;
extSerV[port]->pTxBuf = NULL;
}
if(type == ObjSerTx)
{
extSerV[port]->flags |= EXTSER_FLAG_TXEN;
pIdx->cbWrite = &serWriteOD;
dioTake(TxPin);
hal_uart_init_hw(port, nBaud, 2);
}
else // ObjSerRx
{
if(extSerV[port]->pRxBuf == NULL)
{
extSerV[port]->pRxBuf = mqAlloc(sizeof(MQ_t));
if(extSerV[port]->pRxBuf == NULL)
return MQTTSN_RET_REJ_CONG;
}
extSerV[port]->flags |= EXTSER_FLAG_RXEN;
pIdx->cbRead = &serReadOD;
pIdx->cbPoll = &serPollOD;
dioTake(RxPin);
hal_uart_init_hw(port, nBaud, 1);
}
return MQTTSN_RET_ACCEPTED;
}