static void exynos4_cpu_prepare(void)
{
if (exynos4_sleep_gpio_table_set)
exynos4_sleep_gpio_table_set();
/* Set value of power down register for sleep mode */
exynos4_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, REG_INFORM1);
/* ensure at least INFORM0 has the resume address */
__raw_writel(virt_to_phys(s3c_cpu_resume), REG_INFORM0);
/* Before enter central sequence mode, clock src register have to set */
#ifdef CONFIG_CACHE_L2X0
/* Disable the full line of zero */
disable_cache_foz();
#endif
s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
if (soc_is_exynos4210())
s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
}
static int exynos4_pm_prepare(void)
{
int ret = 0;
#if defined(CONFIG_REGULATOR) && (defined (CONFIG_MX_SERIAL_TYPE) || defined(CONFIG_MX2_SERIAL_TYPE))
ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
#endif
#ifdef CONFIG_CACHE_L2X0
/* Disable the full line of zero */
disable_cache_foz();
#endif
return ret;
}
void exynos4_cpu_suspend(void)
{
unsigned int tmp;
if (soc_is_exynos4210()) {
/* eMMC power off delay (hidden register)
* 0x10020988 => 0: 300msec, 1: 6msec
*/
__raw_writel(1, S5P_PMUREG(0x0988));
}
if ((!soc_is_exynos4210()) && (exynos4_is_c2c_use())) {
/* Gating CLK_IEM_APC & Enable CLK_SSS */
tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC);
tmp &= ~(0x1 << 17);
tmp |= (0x1 << 4);
__raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC);
/* Set MAX divider for PWI */
tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1);
tmp |= (0xF << 8);
__raw_writel(tmp, EXYNOS4_CLKDIV_DMC1);
/* Set clock source for PWI */
tmp = __raw_readl(EXYNOS4_CLKSRC_DMC);
tmp &= ~EXYNOS4_CLKSRC_DMC_MASK;
tmp |= ((0x6 << 16)|(0x1 << 12));
__raw_writel(tmp, EXYNOS4_CLKSRC_DMC);
}
outer_flush_all();
/* Disable the full line of zero */
disable_cache_foz();
#ifdef CONFIG_ARM_TRUSTZONE
exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
#else
/* issue the standby signal into the pm unit. */
cpu_do_idle();
#endif
}
