/* interrupt service routine */ void rt_dm9000_isr() { rt_uint16_t int_status; rt_uint16_t last_io; last_io = DM9000_IO; /* Disable all interrupts */ // dm9000_io_write(DM9000_IMR, IMR_PAR); /* Got DM9000 interrupt status */ int_status = dm9000_io_read(DM9000_ISR); /* Got ISR */ dm9000_io_write(DM9000_ISR, int_status); /* Clear ISR status */ DM9000_TRACE("dm9000 isr: int status %04x\n", int_status); /* receive overflow */ if (int_status & ISR_ROS) { rt_kprintf("overflow\n"); } if (int_status & ISR_ROOS) { rt_kprintf("overflow counter overflow\n"); } /* Received the coming packet */ if (int_status & ISR_PRS) { /* disable receive interrupt */ dm9000_io_write(DM9000_IMR, IMR_PAR); dm9000_device.imr_all = IMR_PAR | IMR_PTM; dm9000_io_write(DM9000_IMR, dm9000_device.imr_all); /* a frame has been received */ eth_device_ready(&(dm9000_device.parent)); } /* Transmit Interrupt check */ if (int_status & ISR_PTS) { /* transmit done */ int tx_status = dm9000_io_read(DM9000_NSR); /* Got TX status */ if (tx_status & (NSR_TX2END | NSR_TX1END)) { dm9000_device.packet_cnt --; if (dm9000_device.packet_cnt > 0) { DM9000_TRACE("dm9000 isr: tx second packet\n"); /* transmit packet II */ /* Set TX length to DM9000 */ dm9000_io_write(DM9000_TXPLL, dm9000_device.queue_packet_len & 0xff); dm9000_io_write(DM9000_TXPLH, (dm9000_device.queue_packet_len >> 8) & 0xff); /* Issue TX polling command */ dm9000_io_write(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ }
/* Read a word from phyxcer */ rt_inline rt_uint16_t phy_read(rt_uint16_t reg) { rt_uint16_t val; /* Fill the phyxcer register into REG_0C */ dm9000_io_write(DM9000_EPAR, DM9000_PHY | reg); dm9000_io_write(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ delay_ms(100); /* Wait read complete */ dm9000_io_write(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ val = (dm9000_io_read(DM9000_EPDRH) << 8) | dm9000_io_read(DM9000_EPDRL); return val; }