//! [config_dma_for_wave]
static void config_dma_for_wave(void)
{
//! [config_dma_resource_for_wave]
struct dma_resource_config config;
dma_get_config_defaults(&config);
config.trigger_action = DMA_TRIGGER_ACTON_BEAT;
config.peripheral_trigger = CONF_COMPARE_TRIGGER;
dma_allocate(&compare_dma_resource, &config);
//! [config_dma_resource_for_wave]
//! [config_dma_descriptor_for_wave]
struct dma_descriptor_config descriptor_config;
dma_descriptor_get_config_defaults(&descriptor_config);
descriptor_config.block_transfer_count = 3;
descriptor_config.beat_size = DMA_BEAT_SIZE_HWORD;
descriptor_config.dst_increment_enable = false;
descriptor_config.source_address =
(uint32_t)compare_values + sizeof(compare_values);
descriptor_config.destination_address =
(uint32_t)&CONF_PWM_MODULE->CC[CONF_PWM_CHANNEL];
dma_descriptor_create(&compare_dma_descriptor, &descriptor_config);
//! [config_dma_descriptor_for_wave]
//! [config_dma_job_for_wave]
dma_add_descriptor(&compare_dma_resource, &compare_dma_descriptor);
dma_add_descriptor(&compare_dma_resource, &compare_dma_descriptor);
dma_start_transfer_job(&compare_dma_resource);
//! [config_dma_job_for_wave]
}
//! [config_dma_for_capture]
static void config_dma_for_capture(void)
{
//! [config_dma_resource_for_capture]
//! [dma_setup_1]
struct dma_resource_config config;
//! [dma_setup_1]
//! [dma_setup_2]
dma_get_config_defaults(&config);
//! [dma_setup_2]
//! [dma_setup_3]
config.trigger_action = DMA_TRIGGER_ACTON_BEAT;
config.peripheral_trigger = CONF_CAPTURE_TRIGGER;
//! [dma_setup_3]
//! [dma_setup_4]
dma_allocate(&capture_dma_resource, &config);
//! [dma_setup_4]
//! [config_dma_resource_for_capture]
//! [config_dma_descriptor_for_capture]
//! [dma_setup_5]
struct dma_descriptor_config descriptor_config;
//! [dma_setup_5]
//! [dma_setup_6]
dma_descriptor_get_config_defaults(&descriptor_config);
//! [dma_setup_6]
//! [dma_setup_7]
descriptor_config.block_transfer_count = 3;
descriptor_config.beat_size = DMA_BEAT_SIZE_HWORD;
descriptor_config.step_selection = DMA_STEPSEL_SRC;
descriptor_config.src_increment_enable = false;
descriptor_config.source_address =
(uint32_t)&CONF_PWM_MODULE->CC[CONF_TCC_CAPTURE_CHANNEL];
descriptor_config.destination_address =
(uint32_t)capture_values + sizeof(capture_values);
//! [dma_setup_7]
//! [dma_setup_8]
dma_descriptor_create(&capture_dma_descriptor, &descriptor_config);
//! [dma_setup_8]
//! [config_dma_descriptor_for_capture]
//! [config_dma_job_for_capture]
//! [dma_setup_10]
dma_add_descriptor(&capture_dma_resource, &capture_dma_descriptor);
dma_add_descriptor(&capture_dma_resource, &capture_dma_descriptor);
//! [dma_setup_10]
//! [dma_setup_11]
dma_start_transfer_job(&capture_dma_resource);
//! [dma_setup_11]
//! [config_dma_job_for_capture]
}
/**
* \brief Configure DMA AES DATA read trigger.
*/
static void configure_dma_aes_rd(void)
{
struct dma_resource_config rx_config;
dma_get_config_defaults(&rx_config);
rx_config.peripheral_trigger = AES_DMAC_ID_RD;
rx_config.trigger_action = DMA_TRIGGER_ACTON_BLOCK;
/* Allocate DMA resource.*/
dma_allocate(&example_resource_rx, &rx_config);
struct dma_descriptor_config rx_descriptor_config;
dma_descriptor_get_config_defaults(&rx_descriptor_config);
rx_descriptor_config.beat_size = DMA_BEAT_SIZE_WORD;
rx_descriptor_config.src_increment_enable = false;
rx_descriptor_config.block_transfer_count = AES_EXAMPLE_REFBUF_SIZE;
rx_descriptor_config.source_address = (uint32_t)&(AES->INDATA);
rx_descriptor_config.destination_address =
(uint32_t)output_data + sizeof(output_data);
/* Create a DMA transfer descriptor.*/
dma_descriptor_create(&example_descriptor_rx, &rx_descriptor_config);
/* Add DMA transfer descriptor to DMA resource.*/
dma_add_descriptor(&example_resource_rx, &example_descriptor_rx);
}
/**
* \brief Configure DMA AES DATA write trigger.
*/
static void configure_dma_aes_wr(void)
{
struct dma_resource_config tx_config;
dma_get_config_defaults(&tx_config);
tx_config.peripheral_trigger = AES_DMAC_ID_WR;
tx_config.trigger_action = DMA_TRIGGER_ACTON_BLOCK;
/* Allocate DMA resource.*/
dma_allocate(&example_resource_tx, &tx_config);
struct dma_descriptor_config tx_descriptor_config;
dma_descriptor_get_config_defaults(&tx_descriptor_config);
tx_descriptor_config.beat_size = DMA_BEAT_SIZE_WORD;
tx_descriptor_config.dst_increment_enable = false;
tx_descriptor_config.block_transfer_count = AES_EXAMPLE_REFBUF_SIZE;
tx_descriptor_config.source_address = (uint32_t)ref_plain_text + sizeof(ref_plain_text);
tx_descriptor_config.destination_address =(uint32_t) &(AES->INDATA);
dma_descriptor_create(&example_descriptor_tx, &tx_descriptor_config);
/* Add DMA transfer descriptor to DMA resource.*/
dma_add_descriptor(&example_resource_tx, &example_descriptor_tx);
}
//! [config_dma_for_tx]
static void _config_dma_for_tx(void)
{
//! [config_dma_resource_for_tx]
struct dma_resource_config config;
dma_get_config_defaults(&config);
config.trigger_action = DMA_TRIGGER_ACTON_BEAT;
config.peripheral_trigger = CONF_TX_TRIGGER;
dma_allocate(&tx_dma_resource, &config);
//! [config_dma_resource_for_tx]
//! [config_dma_descriptor_for_tx]
struct dma_descriptor_config descriptor_config;
dma_descriptor_get_config_defaults(&descriptor_config);
descriptor_config.block_transfer_count = 4;
descriptor_config.beat_size = DMA_BEAT_SIZE_HWORD;
descriptor_config.dst_increment_enable = false;
descriptor_config.source_address =
(uint32_t)tx_values + sizeof(tx_values);
descriptor_config.destination_address = (uint32_t)&CONF_I2S_MODULE->DATA[0];
dma_descriptor_create(&tx_dma_descriptor, &descriptor_config);
tx_dma_descriptor.DESCADDR.reg = (uint32_t)&tx_dma_descriptor;
//! [config_dma_descriptor_for_tx]
//! [config_dma_job_for_tx]
dma_add_descriptor(&tx_dma_resource, &tx_dma_descriptor);
dma_start_transfer_job(&tx_dma_resource);
//! [config_dma_job_for_tx]
}
int main(void)
{
//! [sample_resource]
struct dma_resource example_resource;
//! [sample_resource]
system_init();
//! [setup_init]
//! [setup_dma_resource]
configure_dma_resource(&example_resource);
//! [setup_dma_resource]
//! [setup_transfer_descriptor]
setup_transfer_descriptor(&example_descriptor);
//! [setup_transfer_descriptor]
//! [add_descriptor_to_dma_resource]
dma_add_descriptor(&example_resource, &example_descriptor);
//! [add_descriptor_to_dma_resource]
//! [setup_callback_register]
dma_register_callback(&example_resource, transfer_done,
DMA_CALLBACK_TRANSFER_DONE);
//! [setup_callback_register]
//! [setup_enable_callback]
dma_enable_callback(&example_resource, DMA_CALLBACK_TRANSFER_DONE);
//! [setup_enable_callback]
//! [setup_source_memory_content]
for (uint32_t i = 0; i < DATA_LENGTH; i++) {
source_memory[i] = i;
}
//! [setup_source_memory_content]
//! [setup_init]
//! [main]
//! [main_1]
dma_start_transfer_job(&example_resource);
//! [main_1]
//! [main_1_1]
dma_trigger_transfer(&example_resource);
//! [main_1_1]
//! [main_2]
while (!transfer_is_done) {
/* Wait for transfer done */
}
//! [main_2]
while (true) {
/* Nothing to do */
}
//! [main]
}
//! [config_dma_for_rx]
static void _config_dma_for_rx(void)
{
//! [config_dma_resource_for_rx]
//! [dma_setup_1]
struct dma_resource_config config;
//! [dma_setup_1]
//! [dma_setup_2]
dma_get_config_defaults(&config);
//! [dma_setup_2]
//! [dma_setup_3]
config.trigger_action = DMA_TRIGGER_ACTON_BEAT;
config.peripheral_trigger = CONF_RX_TRIGGER;
//! [dma_setup_3]
//! [dma_setup_4]
dma_allocate(&rx_dma_resource, &config);
//! [dma_setup_4]
//! [config_dma_resource_for_rx]
//! [config_dma_descriptor_for_rx]
//! [dma_setup_5]
struct dma_descriptor_config descriptor_config;
//! [dma_setup_5]
//! [dma_setup_6]
dma_descriptor_get_config_defaults(&descriptor_config);
//! [dma_setup_6]
//! [dma_setup_7]
descriptor_config.block_transfer_count = 4;
descriptor_config.beat_size = DMA_BEAT_SIZE_HWORD;
descriptor_config.step_selection = DMA_STEPSEL_SRC;
descriptor_config.src_increment_enable = false;
descriptor_config.destination_address =
(uint32_t)rx_values + sizeof(rx_values);
descriptor_config.source_address = (uint32_t)&CONF_I2S_MODULE->DATA[1];
//! [dma_setup_7]
//! [dma_setup_8]
dma_descriptor_create(&rx_dma_descriptor, &descriptor_config);
//! [dma_setup_8]
//! [dma_setup_9]
rx_dma_descriptor.DESCADDR.reg = (uint32_t)&rx_dma_descriptor;
//! [dma_setup_9]
//! [config_dma_descriptor_for_rx]
//! [config_dma_job_for_rx]
//! [dma_setup_10]
dma_add_descriptor(&rx_dma_resource, &rx_dma_descriptor);
//! [dma_setup_10]
//! [dma_setup_11]
dma_start_transfer_job(&rx_dma_resource);
//! [dma_setup_11]
//! [config_dma_job_for_rx]
}
/**
* \brief Config DMA to make peripheral-to-memory transfer scrolling string to
* SLCD memory.
*/
static void configure_dma(void)
{
configure_dma_resource(&example_resource);
setup_transfer_descriptor(&example_descriptor);
if (STATUS_OK != dma_add_descriptor(&example_resource,
&example_descriptor)) {
printf("Descriptor status error\n\n\r");
}
dma_register_callback(&example_resource, dma_callback,
DMA_CALLBACK_TRANSFER_DONE);
dma_enable_callback(&example_resource, DMA_CALLBACK_TRANSFER_DONE);
}
/**
* \brief configure and enable DMA multiple channel (in this case it is 3)
*/
void configure_dma(void)
{
/* Configure DMA channel 0 */
configure_dma_resource(&dmac_adc_channel0, DMAC_CHANNEL0_ID);
/* Configure descriptor for channel 1 */
setup_transfer_descriptor(&dmac_adc_descriptor1, DMAC_DESCRIPTOR1_ID);
/* Assign descriptor 1 to DMA channel 0 */
dma_add_descriptor(&dmac_adc_channel0, &dmac_adc_descriptor1);
/*
* Register call back for DMA channel 0 transfer complete interrupt
* which will get triggered for every block transfer (I.e. 1024 beats
* in this case
*/
dma_register_callback(&dmac_adc_channel0, dmac_calback_channel0,
DMA_CALLBACK_TRANSFER_DONE);
/* Enable Call back for channel 0 */
dma_enable_callback(&dmac_adc_channel0, DMA_CALLBACK_TRANSFER_DONE);
/* Enable DMA channel 0 and its interrupt */
dma_start_transfer_job(&dmac_adc_channel0);
}
