void blank_display(BYTE side) { int i; // check which side to blank if(side == BOTH) { // loop through digits and blank them for(i = 1; i < 8; i++) { driver_write(i, BLANK); } } else if(side == LEFT) { for(i = 1; i < 4; i++) { driver_write(i, BLANK); } } // right side else { for(i = 4; i < 7; i++) { driver_write(i, BLANK); } } return; }
void write_gear(BYTE gear) { // convert gear value to data to be sent to display driver if(gear != 7) gear = num_arr[gear]; else gear = num_arr[11]; // write the gear position driver_write(DIG6, gear); return; }
size_t vmi_write_pa (vmi_instance_t vmi, addr_t paddr, void *buf, size_t count) { if (NULL == buf){ dbprint("--%s: buf passed as NULL, returning without write\n", __FUNCTION__); return 0; } if (VMI_SUCCESS == driver_write(vmi, paddr, buf, count)){ return count; } else{ return 0; } }
size_t vmi_write_va (vmi_instance_t vmi, addr_t vaddr, int pid, void *buf, size_t count) { addr_t paddr = 0; addr_t pfn = 0; addr_t offset = 0; size_t buf_offset = 0; if (NULL == buf){ dbprint("--%s: buf passed as NULL, returning without write\n", __FUNCTION__); return 0; } while (count > 0){ size_t write_len = 0; if (pid){ paddr = vmi_translate_uv2p(vmi, vaddr + buf_offset, pid); } else{ paddr = vmi_translate_kv2p(vmi, vaddr + buf_offset); } if (!paddr){ return buf_offset; } /* determine how much we can write to this page */ offset = (vmi->page_size - 1) & paddr; if ((offset + count) > vmi->page_size){ write_len = vmi->page_size - offset; } else{ write_len = count; } /* do the write */ if (VMI_FAILURE == driver_write(vmi, paddr, ((char *) buf + (addr_t) buf_offset), write_len)){ return buf_offset; } /* set variables for next loop */ count -= write_len; buf_offset += write_len; } return buf_offset; }
void updateText(BYTE side, BYTE *state) { // update left or right display with text if(!side) { // send out characters one at a time driver_write(DIG2, text_arr[state[side]][0]); driver_write(DIG1, text_arr[state[side]][1]); driver_write(DIG0, text_arr[state[side]][2]); } else { driver_write(DIG3, text_arr[state[side]][0]); driver_write(DIG4, text_arr[state[side]][1]); driver_write(DIG5, text_arr[state[side]][2]); } return; }
void write_num(int data, BYTE d_place, BYTE side) { BYTE num_0, num_1, num_2; // get individual digits of full number num_2 = data % 10; num_1 = (data % 100) / 10; num_0 = (data % 1000) / 100; // convert values to data bytes for display driver num_0 = num_arr[num_0]; num_1 = num_arr[num_1]; num_2 = num_arr[num_2]; // add decimal points to numbers if(d_place) { if(d_place == 1) { num_0 |= NUM_DP; } else if(d_place == 2) { num_1 |= NUM_DP; } else { num_2 |= NUM_DP; } } // write the number to the indicated side if(!side) { driver_write(DIG2, num_0); driver_write(DIG1, num_1); driver_write(DIG0, num_2); } else { driver_write(DIG3, num_0); driver_write(DIG4, num_1); driver_write(DIG5, num_2); } return; }
void main(void) { /************************* * Variable Declarations * *************************/ BYTE radio_sw[2], drs_over_sw[2], fan_over_sw[2], fuel_map_sw[2], paddle_l_sw[2], paddle_r_sw[2]; BYTE ADLmsg[8]; BYTE cycleStates[2], intensity; unsigned int bounceTimer[2]; unsigned int CAN_tmr; /********************* * Oscillator Set-Up * *********************/ #ifdef INTERNAL // OSCTUNE OSCTUNEbits.INTSRC = 0; // Internal Oscillator Low-Frequency Source Select (1 for 31.25 kHz from 16MHz/512 or 0 for internal 31kHz) OSCTUNEbits.PLLEN = 1; // Frequency Multiplier PLL Select (1 to enable) OSCTUNEbits.TUN5 = 0; // Fast RC Oscillator Frequency Tuning (seems to be 2's comp encoding) OSCTUNEbits.TUN4 = 0; // 011111 = max OSCTUNEbits.TUN3 = 0; // ... 000001 OSCTUNEbits.TUN2 = 0; // 000000 = center (running at calibrated frequency) OSCTUNEbits.TUN1 = 0; // 111111 ... OSCTUNEbits.TUN0 = 0; // 100000 // OSCCCON OSCCONbits.IDLEN = 1; // Idle Enable Bit (1 to enter idle mode after SLEEP instruction else sleep mode is entered) OSCCONbits.IRCF2 = 1; // Internal Oscillator Frequency Select Bits OSCCONbits.IRCF1 = 1; // When using HF, settings are: OSCCONbits.IRCF0 = 1; // 111 - 16 MHz, 110 - 8MHz (default), 101 - 4MHz, 100 - 2 MHz, 011 - 1 MHz OSCCONbits.SCS1 = 0; OSCCONbits.SCS0 = 0; // OSCCON2 OSCCON2bits.MFIOSEL = 0; while(!OSCCONbits.HFIOFS); // wait for stable clock #else // OSCTUNE OSCTUNEbits.INTSRC = 0; // Internal Oscillator Low-Frequency Source Select (1 for 31.25 kHz from 16MHz/512 or 0 for internal 31kHz) OSCTUNEbits.PLLEN = 1; // Frequency Multiplier PLL Select (1 to enable) // OSCCCON OSCCONbits.SCS1 = 0; // select configuration chosen oscillator OSCCONbits.SCS0 = 0; // SCS = 00 // OSCCON2 OSCCON2bits.MFIOSEL = 0; while(!OSCCONbits.OSTS); // wait for stable external clock #endif /********************* * Peripherals Setup * *********************/ // turn on and configure the A/D converter module OpenADC(ADC_FOSC_64 & ADC_RIGHT_JUST & ADC_4_TAD, ADC_CH0 & ADC_INT_OFF, ADC_REF_VDD_VDD & ADC_REF_VDD_VSS & ADC_NEG_CH0); ANCON0 = 0b00100111; // AN0 - 2 and AN5 are analog ANCON1 = 0x00; // rest are digital TRISAbits.TRISA0 = INPUT; TRISAbits.TRISA1 = INPUT; TRISAbits.TRISA2 = INPUT; TRISAbits.TRISA5 = INPUT; // turn on and configure the TIMER1 oscillator OpenTimer0(TIMER_INT_ON & T0_8BIT & T0_SOURCE_INT & T0_PS_1_128); WriteTimer0(0x82); // load timer register millis = 0; // clear milliseconds count INTCONbits.TMR0IE = 1; // turn on timer0 interupts // SPI setup SSPSTATbits.CKE = 1; // SPI Clock Select, 1 = transmit on active to idle SSPCON1bits.CKP = 0; // Clock Polarity Select, 0 = low level is idle state SSPCON1bits.SSPM = 0b1010; // Clk Frequecy (Note: FOSC = 64MHz) SSPCON1bits.SSPEN = 1; // SPI Enable, 1 enables // SPI pin I/O setup TRISCbits.TRISC3 = OUTPUT; // SCK TRISCbits.TRISC5 = OUTPUT; // SDO TRISDbits.TRISD3 = OUTPUT; // CS CS = 1; // driver set up intensity = 0x0F; driver_write(DISP_MODE, NORMAL); // leave test mode driver_write(SHUTDOWN, SHUTDOWN_OFF); // leave shutdown mode driver_write(INTENSITY, intensity); // set brightness to highest driver_write(SCAN, FULL_SCAN); // Set scan to all digits driver_write(DECODE, NO_DECODE); // Decoding disabled // set displays to display zero write_gear(0); write_num(0, 2, LEFT); write_num(0, 2, RIGHT); // intialize states cycleStates[LEFT] = CYCLE_L; cycleStates[RIGHT] = CYCLE_R; holdText[LEFT] = holdText[RIGHT] = TRUE; refreshTime[LEFT] = refreshTime[RIGHT] = holdTimer[LEFT] = holdTimer[RIGHT] = blinkTimer[LEFT] = blinkTimer[RIGHT] = millis; displayStates[LEFT] = OIL_T; displayStates[RIGHT] = ENGINE_T; ECANInitialize(); // setup ECAN // interrupts setup INTCONbits.GIE = 1; // Global Interrupt Enable (1 enables) INTCONbits.PEIE = 1; // Peripheral Interrupt Enable (1 enables) RCONbits.IPEN = 0; // Interrupt Priority Enable (1 enables) TRISCbits.TRISC6 = OUTPUT; // programmable termination TERM_LAT = FALSE; while(1) { // check for change in button state if(cycleStates[LEFT] != CYCLE_L & millis - bounceTimer[LEFT] > BOUNCE_TIME) { // save new state cycleStates[LEFT] = CYCLE_L; bounceTimer[LEFT] = millis; // only change display if button is low if(!cycleStates[LEFT]) { if(++displayStates[LEFT] == NUM_CHAN) displayStates[LEFT] = 0; // put the appropriate text on the displays and // get the current time for timing logic updateText(LEFT, displayStates); holdText[LEFT] = TRUE; blinkTimer[LEFT] = holdTimer[LEFT] = millis; } } if(cycleStates[RIGHT] != CYCLE_R & millis - bounceTimer[RIGHT] > BOUNCE_TIME) { cycleStates[RIGHT] = CYCLE_R; bounceTimer[RIGHT] = millis; if(!cycleStates[RIGHT]) { if(++displayStates[RIGHT] == NUM_CHAN) displayStates[RIGHT] = 0; updateText(RIGHT, displayStates); holdText[RIGHT] = TRUE; blinkTimer[RIGHT] = holdTimer[RIGHT] = millis; } } // update left and right displays with text or numerical data updateDisp(LEFT); updateDisp(RIGHT); write_gear(gear); // radio button if(!RADIO) { radio_sw[0] = 0x13; radio_sw[1] = 0x88; } else *(int *)radio_sw = 0; #if 0 // paddle switches if(PADDLE_L) { paddle_l_sw[0] = 0x13; paddle_l_sw[1] = 0x88; } else *(int *)paddle_l_sw = 0; if(PADDLE_R) { paddle_r_sw[0] = 0x13; paddle_r_sw[1] = 0x88; } else *(int *)paddle_r_sw = 0; #endif // DRS override switch if(DRS_OVER) { drs_over_sw[0] = 0x13; drs_over_sw[1] = 0x88; } else *(int *)drs_over_sw = 0; // fan override switch if(FAN_OVER) { fan_over_sw[0] = 0x13; fan_over_sw[1] = 0x88; } else *(int *)fan_over_sw = 0; // fuel map switch if(FUEL_MAP) { fuel_map_sw[0] = 0x13; fuel_map_sw[1] = 0x88; } else *(int *)fuel_map_sw = 0; if(millis - CAN_tmr > CAN_PER) { CAN_tmr = millis; // send out the first three sampled switches ADLmsg[0] = 0x00; ADLmsg[1] = 0x00; ADLmsg[ADL1] = radio_sw[0]; ADLmsg[ADL1 + 1] = radio_sw[1]; ADLmsg[ADL2] = fan_over_sw[0]; ADLmsg[ADL2 + 1] = fan_over_sw[1]; ADLmsg[ADL3] = fuel_map_sw[0]; ADLmsg[ADL3 + 1] = fuel_map_sw[1]; ECANSendMessage(ADLid, ADLmsg, 8, ECAN_TX_STD_FRAME | ECAN_TX_NO_RTR_FRAME | ECAN_TX_PRIORITY_1); // send out first three rotary encoders ADLmsg[0] = 0x01; ADLmsg[1] = 0x00; ADLsample(ADLmsg, ADL4, LAUNCH_ROT); ADLsample(ADLmsg, ADL5, TRAC_ROT); ADLsample(ADLmsg, ADL6, DRS_ROT); ECANSendMessage(ADLid, ADLmsg, 8, ECAN_TX_STD_FRAME | ECAN_TX_NO_RTR_FRAME | ECAN_TX_PRIORITY_1); } } // end main loop return; }
int output_buffer_flush (DRIVER_USERDATA_T inst, int driver) { ROAR_DBG("output_buffer_init(*): flushing output buffer"); return driver_write(inst, driver, g_output_buffer, g_output_buffer_len); }
/////////////////////////////////////////////////////////// // Classic write functions for access to memory size_t vmi_write( vmi_instance_t vmi, const access_context_t *ctx, void *buf, size_t count) { addr_t start_addr = 0; addr_t dtb = 0; addr_t paddr = 0; addr_t offset = 0; size_t buf_offset = 0; if (NULL == buf) { dbprint(VMI_DEBUG_WRITE, "--%s: buf passed as NULL, returning without write\n", __FUNCTION__); return 0; } if (NULL == ctx) { dbprint(VMI_DEBUG_WRITE, "--%s: ctx passed as NULL, returning without write\n", __FUNCTION__); return 0; } switch (ctx->translate_mechanism) { case VMI_TM_NONE: start_addr = ctx->addr; break; case VMI_TM_KERNEL_SYMBOL: if (!vmi->arch_interface || !vmi->os_interface || !vmi->kpgd) return 0; dtb = vmi->kpgd; start_addr = vmi_translate_ksym2v(vmi, ctx->ksym); break; case VMI_TM_PROCESS_PID: if (!vmi->arch_interface || !vmi->os_interface) { return 0; } if(ctx->pid) { dtb = vmi_pid_to_dtb(vmi, ctx->pid); } else { dtb = vmi->kpgd; } if (!dtb) { return 0; } start_addr = ctx->addr; break; case VMI_TM_PROCESS_DTB: if (!vmi->arch_interface) { return 0; } dtb = ctx->dtb; start_addr = ctx->addr; break; default: errprint("%s error: translation mechanism is not defined.\n", __FUNCTION__); return 0; } while (count > 0) { size_t write_len = 0; if(dtb) { if (VMI_SUCCESS != vmi_pagetable_lookup_cache(vmi, dtb, start_addr + buf_offset, &paddr)) { return buf_offset; } } else { paddr = start_addr + buf_offset; } /* determine how much we can write to this page */ offset = (vmi->page_size - 1) & paddr; if ((offset + count) > vmi->page_size) { write_len = vmi->page_size - offset; } else { write_len = count; } /* do the write */ if (VMI_FAILURE == driver_write(vmi, paddr, ((char *) buf + (addr_t) buf_offset), write_len)) { return buf_offset; } /* set variables for next loop */ count -= write_len; buf_offset += write_len; } return buf_offset; }