static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
struct drm_ati_pcigart_info *gart_info)
{
dev->sg->dmah = drm_pci_alloc(dev, gart_info->table_size,
PAGE_SIZE,
gart_info->table_mask);
if (dev->sg->dmah == NULL)
return ENOMEM;
return 0;
}
/**
* radeon_gart_table_ram_alloc - allocate system ram for gart page table
*
* @rdev: radeon_device pointer
*
* Allocate system memory for GART page table
* (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
* gart table to be in system memory.
* Returns 0 for success, -ENOMEM for failure.
*/
int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
{
drm_dma_handle_t *dmah;
dmah = drm_pci_alloc(rdev->ddev, rdev->gart.table_size,
PAGE_SIZE, 0xFFFFFFFFUL);
if (dmah == NULL) {
return -ENOMEM;
}
rdev->gart.dmah = dmah;
rdev->gart.ptr = dmah->vaddr;
#if defined(__i386) || defined(__amd64)
if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
pmap_change_attr((vm_offset_t)rdev->gart.ptr,
rdev->gart.table_size >> PAGE_SHIFT, PAT_UNCACHED);
}
int drm_ati_pcigart_init(struct drm_device *dev,
struct drm_ati_pcigart_info *gart_info)
{
unsigned long pages;
u32 *pci_gart = NULL, page_base;
int i, j;
if (dev->sg == NULL) {
DRM_ERROR( "no scatter/gather memory!\n" );
return 0;
}
if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
/* GART table in system memory */
dev->sg->dmah = drm_pci_alloc(dev, gart_info->table_size, 0,
0xfffffffful);
if (dev->sg->dmah == NULL) {
DRM_ERROR("cannot allocate PCI GART table!\n");
return 0;
}
gart_info->addr = (void *)dev->sg->dmah->vaddr;
gart_info->bus_addr = dev->sg->dmah->busaddr;
pci_gart = (u32 *)dev->sg->dmah->vaddr;
} else {
/* GART table in framebuffer memory */
pci_gart = gart_info->addr;
}
pages = DRM_MIN(dev->sg->pages, gart_info->table_size / sizeof(u32));
bzero(pci_gart, gart_info->table_size);
#if defined(__FreeBSD__)
KASSERT(PAGE_SIZE >= ATI_PCIGART_PAGE_SIZE, ("page size too small"));
#else
KASSERT(PAGE_SIZE >= ATI_PCIGART_PAGE_SIZE);
#endif
for ( i = 0 ; i < pages ; i++ ) {
page_base = (u32) dev->sg->busaddr[i];
for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
switch(gart_info->gart_reg_if) {
case DRM_ATI_GART_IGP:
*pci_gart = cpu_to_le32(page_base | 0xc);
break;
case DRM_ATI_GART_PCIE:
*pci_gart = cpu_to_le32((page_base >> 8) | 0xc);
break;
default:
*pci_gart = cpu_to_le32(page_base);
break;
}
pci_gart++;
page_base += ATI_PCIGART_PAGE_SIZE;
}
}
DRM_MEMORYBARRIER();
return 1;
}