int intel_configure_dsi_pll(struct intel_dsi *intel_dsi,
struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv =
intel_dsi->base.base.dev->dev_private;
int ret;
struct dsi_mnp dsi_mnp;
u32 dsi_clk;
DRM_DEBUG_KMS("\n");
if (intel_dsi->dsi_clock_freq)
dsi_clk = intel_dsi->dsi_clock_freq;
else
get_dsi_clk(intel_dsi, mode, &dsi_clk);
ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
/*ret = mnp_from_clk_table(dsi_clk, &dsi_mnp);*/
if (ret != 0)
return ret;
dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div);
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
return 0;
}
/*
* XXX: The muxing and gating is hard coded for now. Need to add support for
* sharing PLLs with two DSI outputs.
*/
int vlv_dsi_pll_compute(struct intel_encoder *encoder,
struct intel_crtc_state *config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int ret;
u32 dsi_clk;
dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
intel_dsi->lane_count);
ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
if (ret) {
DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
return ret;
}
if (intel_dsi->ports & (1 << PORT_A))
config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
if (intel_dsi->ports & (1 << PORT_C))
config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;
DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
config->dsi_pll.div, config->dsi_pll.ctrl);
return 0;
}
int intel_calculate_dsi_pll_mnp(struct intel_dsi *intel_dsi,
struct drm_display_mode *mode,
struct intel_dsi_mnp *intel_dsi_mnp, u32 dsi_clk)
{
int ret;
if (dsi_clk == 0) {
ret = intel_get_dsi_clk(intel_dsi, mode, &dsi_clk);
if (ret < 0)
return ret;
}
return dsi_calc_mnp(dsi_clk, intel_dsi_mnp);
}
int intel_configure_dsi_pll(struct intel_dsi *intel_dsi,
struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv =
intel_dsi->base.base.dev->dev_private;
int ret;
struct dsi_mnp dsi_mnp;
u32 dsi_clk;
get_dsi_clk(intel_dsi, mode, &dsi_clk);
ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
/*ret = mnp_from_clk_table(dsi_clk, &dsi_mnp);*/
if (ret != 0)
return ret;
intel_cck_write32(dev_priv, 0x48, 0x00000000);
intel_cck_write32(dev_priv, 0x4C, dsi_mnp.dsi_pll_div);
intel_cck_write32(dev_priv, 0x48, dsi_mnp.dsi_pll_ctrl);
return 0;
}
