void dsim_reg_set_dphy_timing_values(struct dphy_timing_value *t)
{
u32 val, mask;
val = DSIM_PHYTIMING_M_TLPXCTL(t->lpx) |
DSIM_PHYTIMING_M_THSEXITCTL(t->hs_exit);
dsim_write(DSIM_PHYTIMING, val);
val = DSIM_PHYTIMING1_M_TCLKPRPRCTL(t->clk_prepare) |
DSIM_PHYTIMING1_M_TCLKZEROCTL(t->clk_zero) |
DSIM_PHYTIMING1_M_TCLKPOSTCTL(t->clk_post) |
DSIM_PHYTIMING1_M_TCLKTRAILCTL(t->clk_trail);
dsim_write(DSIM_PHYTIMING1, val);
val = DSIM_PHYTIMING2_M_THSPRPRCTL(t->hs_prepare) |
DSIM_PHYTIMING2_M_THSZEROCTL(t->hs_zero) |
DSIM_PHYTIMING2_M_THSTRAILCTL(t->hs_trail);
dsim_write(DSIM_PHYTIMING2, val);
val = DSIM_PHYCTRL_B_DPHYCTL(t->b_dphyctl) |
DSIM_PHYCTRL_B_DPHYCTL_VREG_LP |
DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP;
mask = DSIM_PHYCTRL_B_DPHYCTL_MASK |
DSIM_PHYCTRL_B_DPHYCTL_VREG_LP |
DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP;
dsim_write_mask(DSIM_B_DPHYCTRL, val, mask);
val = DSIM_PHYCTRL_M_DPHYCTL_VREG_HS;
mask = DSIM_PHYCTRL_M_DPHYCTL_VREG_HS;
dsim_write_mask(DSIM_M_DPHYCTRL, val, mask);
}
void dsim_reg_wr_tx_header(u32 id, u32 data_id, unsigned long data0, u32 data1)
{
u32 val = DSIM_PKTHDR_ID(data_id) | DSIM_PKTHDR_DATA0(data0) |
DSIM_PKTHDR_DATA1(data1);
dsim_write(id, DSIM_PKTHDR, val);
}
void dsim_reg_set_porch(u32 id, struct decon_lcd *lcd)
{
u32 val, mask, width;
if (lcd->mode == DECON_VIDEO_MODE) {
val = DSIM_MVPORCH_CMD_ALLOW(DSIM_CMD_ALLOW_VALUE) |
DSIM_MVPORCH_STABLE_VFP(DSIM_STABLE_VFP_VALUE) |
DSIM_MVPORCH_VBP(lcd->vbp);
mask = DSIM_MVPORCH_CMD_ALLOW_MASK | DSIM_MVPORCH_VBP_MASK |
DSIM_MVPORCH_STABLE_VFP_MASK;
dsim_write_mask(id, DSIM_MVPORCH, val, mask);
val = DSIM_MHPORCH_HFP(lcd->hfp) | DSIM_MHPORCH_HBP(lcd->hbp);
dsim_write(id, DSIM_MHPORCH, val);
val = DSIM_MSYNC_VSA(lcd->vsa) | DSIM_MSYNC_HSA(lcd->hsa);
mask = DSIM_MSYNC_VSA_MASK | DSIM_MSYNC_HSA_MASK;
dsim_write_mask(id, DSIM_MSYNC, val, mask);
}
if (lcd->mic_enabled)
width = (lcd->xres/3) + (lcd->xres % 4);
else
width = lcd->xres;
/* TODO: will be added SHADOW_EN in EVT1 */
val = DSIM_MDRESOL_VRESOL(lcd->yres) | DSIM_MDRESOL_HRESOL(width);
mask = DSIM_MDRESOL_VRESOL_MASK | DSIM_MDRESOL_HRESOL_MASK;
dsim_write_mask(id, DSIM_MDRESOL, val, mask);
}
void dsim_reg_set_porch(struct decon_lcd *lcd)
{
u32 val, mask, width, height;
if (lcd->mode == VIDEO_MODE) {
val = DSIM_MVPORCH_CMD_ALLOW(DSIM_CMD_ALLOW_VALUE) |
DSIM_MVPORCH_STABLE_VFP(DSIM_STABLE_VFP_VALUE) |
DSIM_MVPORCH_VBP(lcd->vbp);
mask = DSIM_MVPORCH_CMD_ALLOW_MASK | DSIM_MVPORCH_VBP_MASK |
DSIM_MVPORCH_STABLE_VFP_MASK;
dsim_write_mask(DSIM_MVPORCH, val, mask);
val = DSIM_MHPORCH_HFP(lcd->hfp) | DSIM_MHPORCH_HBP(lcd->hbp);
dsim_write(DSIM_MHPORCH, val);
val = DSIM_MSYNC_VSA(lcd->vsa) | DSIM_MSYNC_HSA(lcd->hsa);
mask = DSIM_MSYNC_VSA_MASK | DSIM_MSYNC_HSA_MASK;
dsim_write_mask(DSIM_MSYNC, val, mask);
}
width = GET_W(lcd->hsync_2h_cycle, lcd->xres);
height = GET_H(lcd->hsync_2h_cycle, lcd->yres);
val = DSIM_MDRESOL_VRESOL(height) | DSIM_MDRESOL_HRESOL(width);
mask = DSIM_MDRESOL_VRESOL_MASK | DSIM_MDRESOL_HRESOL_MASK;
dsim_write_mask(DSIM_MDRESOL, val, mask);
}
void dsim_reg_set_dphy_timing_values(struct dphy_timing_value *t)
{
u32 val, mask;
val = DSIM_PHYTIMING_M_TLPXCTL(t->lpx) |
DSIM_PHYTIMING_M_THSEXITCTL(t->hs_exit);
dsim_write(DSIM_PHYTIMING, val);
val = DSIM_PHYTIMING1_M_TCLKPRPRCTL(t->clk_prepare) |
DSIM_PHYTIMING1_M_TCLKZEROCTL(t->clk_zero) |
DSIM_PHYTIMING1_M_TCLKPOSTCTL(t->clk_post) |
DSIM_PHYTIMING1_M_TCLKTRAILCTL(t->clk_trail);
dsim_write(DSIM_PHYTIMING1, val);
val = DSIM_PHYTIMING2_M_THSPRPRCTL(t->hs_prepare) |
DSIM_PHYTIMING2_M_THSZEROCTL(t->hs_zero) |
DSIM_PHYTIMING2_M_THSTRAILCTL(t->hs_trail);
dsim_write(DSIM_PHYTIMING2, val);
val = DSIM_PHYCTRL_B_DPHYCTL(t->b_dphyctl) |
DSIM_PHYCTRL_B_DPHYCTL_VREG_LP;
mask = DSIM_PHYCTRL_B_DPHYCTL_MASK | DSIM_PHYCTRL_B_DPHYCTL_VREG_LP;
#if defined(CONFIG_DECON_LCD_EA8064G) && !defined(CONFIG_SEC_FACTORY) /* Should be removed */
val |= DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP;
mask |= DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP;
#endif
dsim_write_mask(DSIM_B_DPHYCTRL, val, mask);
val = DSIM_PHYCTRL_M_DPHYCTL_VREG_HS;
mask = DSIM_PHYCTRL_M_DPHYCTL_VREG_HS;
dsim_write_mask(DSIM_M_DPHYCTRL, val, mask);
val = DSIM_M_PLLCTRL_SET1(t->m_pllctl) |
DSIM_M_PLLCTRL_SET3(DSIM_M_PLLCTRL_VALUE3) |
DSIM_M_PLLCTRL_SET2;
mask = DSIM_M_PLLCTRL_SET1_MASK |
DSIM_M_PLLCTRL_SET3_MASK |
DSIM_M_PLLCTRL_SET2;
dsim_write_mask(DSIM_M_PLLCTRL, val, mask);
}
void dsim_reg_set_dphy_timing_values(u32 id, struct dphy_timing_value *t)
{
u32 val;
val = DSIM_PHYTIMING_M_TLPXCTL(t->lpx) |
DSIM_PHYTIMING_M_THSEXITCTL(t->hs_exit);
dsim_write(id, DSIM_PHYTIMING, val);
val = DSIM_PHYTIMING1_M_TCLKPRPRCTL(t->clk_prepare) |
DSIM_PHYTIMING1_M_TCLKZEROCTL(t->clk_zero) |
DSIM_PHYTIMING1_M_TCLKPOSTCTL(t->clk_post) |
DSIM_PHYTIMING1_M_TCLKTRAILCTL(t->clk_trail);
dsim_write(id, DSIM_PHYTIMING1, val);
val = DSIM_PHYTIMING2_M_THSPRPRCTL(t->hs_prepare) |
DSIM_PHYTIMING2_M_THSZEROCTL(t->hs_zero) |
DSIM_PHYTIMING2_M_THSTRAILCTL(t->hs_trail);
dsim_write(id, DSIM_PHYTIMING2, val);
val = DSIM_PHYCTRL_B_DPHYCTL0(t->b_dphyctl);
dsim_write_mask(id, DSIM_PHYCTRL, val, DSIM_PHYCTRL_B_DPHYCTL0_MASK);
}
void dsim_reg_set_porch(u32 id, struct decon_lcd *lcd)
{
u32 val, mask, width;
if (lcd->mode == DECON_VIDEO_MODE) {
val = DSIM_MVPORCH_CMD_ALLOW(DSIM_CMD_ALLOW_VALUE) |
DSIM_MVPORCH_STABLE_VFP(DSIM_STABLE_VFP_VALUE) |
DSIM_MVPORCH_VBP(lcd->vbp);
mask = DSIM_MVPORCH_CMD_ALLOW_MASK | DSIM_MVPORCH_VBP_MASK |
DSIM_MVPORCH_STABLE_VFP_MASK;
dsim_write_mask(id, DSIM_MVPORCH, val, mask);
val = DSIM_MHPORCH_HFP(lcd->hfp) | DSIM_MHPORCH_HBP(lcd->hbp);
dsim_write(id, DSIM_MHPORCH, val);
val = DSIM_MSYNC_VSA(lcd->vsa) | DSIM_MSYNC_HSA(lcd->hsa);
mask = DSIM_MSYNC_VSA_MASK | DSIM_MSYNC_HSA_MASK;
dsim_write_mask(id, DSIM_MSYNC, val, mask);
}
if (lcd->mic_enabled)
width = (lcd->xres >> 1) + (lcd->xres % 4);
else
void dsim_reg_wr_tx_payload(u32 id, u32 payload)
{
dsim_write(id, DSIM_PAYLOAD, payload);
}
void dsim_reg_clear_int_all(u32 id)
{
dsim_write(id, DSIM_INTSRC, 0xffffffff);
}
void dsim_reg_clear_int(u32 id, u32 int_src)
{
dsim_write(id, DSIM_INTSRC, int_src);
}
void dsim_reg_pll_stable_time(u32 id)
{
dsim_write(id, DSIM_PLLTMR, DSIM_PLL_STABLE_TIME);
}
void dsim_reg_clear_int_all(void)
{
dsim_write(DSIM_INTSRC, 0xffffffff);
}
