static unsigned char add_sync_cap(dterm_t* dt, int fd)
{
dterm_mark_t prop;
dterm_mark_t c_list;
unsigned char bitmask[1]; // 4 SYN events.
int i = 0;
if (ioctl(fd, EVIOCGBIT(EV_SYN, sizeof(bitmask)), bitmask) < 0) {
return IEDRV_RES_IO_ERROR;
}
dterm_tuple_begin(dt, &prop);
dterm_atom(dt, ie_sync);
dterm_list_begin(dt, &c_list);
// Add all capabilities present
for(i = 0; i < sizeof(sync_cap_map) / sizeof(sync_cap_map[0]); ++i) {
if (t_bit(bitmask, sync_cap_map[i].bit)) {
dterm_mark_t cap_tuple;
dterm_tuple_begin(dt, &cap_tuple);
dterm_atom(dt, sync_cap_map[i].atom);
dterm_tuple_end(dt, &cap_tuple);
}
}
dterm_list_end(dt, &c_list);
dterm_tuple_end(dt, &prop);
return IEDRV_RES_OK;
}
static unsigned char add_switch_cap(dterm_t* dt, int fd)
{
dterm_mark_t prop;
dterm_mark_t c_list;
#ifndef SW_CNT
#define SW_CNT SW_MAX
#endif
unsigned char bitmask[SW_CNT / 8 + 1];
int i = 0;
if (ioctl(fd, EVIOCGBIT(EV_SW, sizeof(bitmask)), bitmask) < 0) {
return IEDRV_RES_IO_ERROR;
}
dterm_tuple_begin(dt, &prop);
dterm_atom(dt, ie_switch);
dterm_list_begin(dt, &c_list);
// Add all capabilities present
for(i = 0; i < sizeof(sw_cap_map) / sizeof(sw_cap_map[0]); ++i) {
if (t_bit(bitmask, sw_cap_map[i].bit)) {
dterm_mark_t cap_tuple;
dterm_tuple_begin(dt, &cap_tuple);
dterm_atom(dt, sw_cap_map[i].atom);
dterm_tuple_end(dt, &cap_tuple);
}
}
dterm_list_end(dt, &c_list);
dterm_tuple_end(dt, &prop);
return IEDRV_RES_OK;
}
static unsigned char add_key_cap(dterm_t* dt, int fd)
{
dterm_mark_t prop;
dterm_mark_t c_list;
#ifndef KEY_CNT
#define KEY_CNT KEY_UNKNOWN
#endif
unsigned char bitmask[KEY_CNT / 8 + 1];
int i = 0;
if (ioctl(fd, EVIOCGBIT(EV_KEY, sizeof(bitmask)), bitmask) < 0) {
return IEDRV_RES_IO_ERROR;
}
dterm_tuple_begin(dt, &prop);
dterm_atom(dt, ie_key);
dterm_list_begin(dt, &c_list);
// Add all capabilities present
for(i = 0; i < sizeof(key_cap_map) / sizeof(key_cap_map[0]); ++i)
if (t_bit(bitmask, key_cap_map[i].bit)) {
dterm_mark_t cap_tuple;
dterm_tuple_begin(dt, &cap_tuple);
dterm_atom(dt, key_cap_map[i].atom);
dterm_int(dt, key_cap_map[i].bit);
dterm_tuple_end(dt, &cap_tuple);
}
dterm_list_end(dt, &c_list);
dterm_tuple_end(dt, &prop);
return IEDRV_RES_OK;
}
static unsigned char add_abs_cap(dterm_t* dt, int fd)
{
dterm_mark_t prop;
dterm_mark_t c_list;
unsigned char bitmask[KEY_CNT / 8 + 1];
int i = 0;
if (ioctl(fd, EVIOCGBIT(EV_ABS, sizeof(bitmask)), bitmask) < 0) {
return IEDRV_RES_IO_ERROR;
}
dterm_tuple_begin(dt, &prop);
dterm_atom(dt, ie_abs);
dterm_list_begin(dt, &c_list);
// Add all capabilities present.
// Each element will have the format
// { Cap (abs_x), { CurrentVal, Min, Max, Fuzz, Flat, Resolution }}
for(i = 0; i < sizeof(abs_cap_map) / sizeof(abs_cap_map[0]); ++i) {
struct input_absinfo abs_info;
dterm_mark_t a_prop;
if (!t_bit(bitmask, abs_cap_map[i].bit))
continue;
if (ioctl(fd, EVIOCGABS(abs_cap_map[i].bit), &abs_info) < 0) {
continue;
}
dterm_tuple_begin(dt, &a_prop);{
dterm_mark_t cap_tuple;
dterm_tuple_begin(dt, &cap_tuple);
dterm_atom(dt, abs_cap_map[i].atom);
dterm_atom(dt, ie_absinfo);
dterm_int(dt, abs_info.value);
dterm_int(dt, abs_info.minimum);
dterm_int(dt, abs_info.maximum);
dterm_int(dt, abs_info.fuzz);
dterm_int(dt, abs_info.flat);
// dterm_int(dt, abs_info.resolution); // Not available in ARM7
dterm_tuple_end(dt, &cap_tuple);
}
dterm_tuple_end(dt, &a_prop);
}
dterm_list_end(dt, &c_list);
dterm_tuple_end(dt, &prop);
return IEDRV_RES_OK;
}
// Build a list of modem state flags
int modem_state_dterm(dterm_t* t, uart_modem_state_t state)
{
dterm_mark_t m;
dterm_list_begin(t, &m);
if (state & UART_DTR) dterm_atom(t, am_dtr);
if (state & UART_RTS) dterm_atom(t, am_rts);
if (state & UART_CTS) dterm_atom(t, am_cts);
if (state & UART_CD) dterm_atom(t, am_cd);
if (state & UART_RI) dterm_atom(t, am_ri);
if (state & UART_DSR) dterm_atom(t, am_dsr);
// SW is not really in modem state but used with flow control
if (state & UART_SW) dterm_atom(t, am_sw);
dterm_list_end(t, &m);
return dterm_used_size(t);
}
static unsigned char add_cap(dterm_t* dt, int fd)
{
unsigned char master_bitmask[EV_MAX / 8 + 1];
unsigned res = IEDRV_RES_OK;
dterm_mark_t c_list;
dterm_list_begin(dt, &c_list);
// Retrieve maste capabilities.
if (ioctl(fd, EVIOCGBIT(0, sizeof(master_bitmask)), master_bitmask) < 0) {
res = IEDRV_RES_IO_ERROR;
goto end;
}
if (t_bit(master_bitmask, EV_SYN) &&
(res = add_sync_cap(dt, fd)) != IEDRV_RES_OK)
goto end;
if (t_bit(master_bitmask, EV_REL) &&
(res = add_rel_cap(dt, fd)) != IEDRV_RES_OK)
goto end;
if (t_bit(master_bitmask, EV_ABS) &&
(res = add_abs_cap(dt, fd)) != IEDRV_RES_OK)
goto end;
if (t_bit(master_bitmask, EV_KEY) &&
(res = add_key_cap(dt, fd)) != IEDRV_RES_OK)
goto end;
if (t_bit(master_bitmask, EV_SW) &&
(res = add_switch_cap(dt, fd)) != IEDRV_RES_OK)
goto end;
end:
dterm_list_end(dt, &c_list);
return res;
}
