static void bridge_enable(struct device *dev)
{
u8 tmp;
print_debug("B188 device dump\n");
/* VIA recommends this, sorry no known info. */
writeback(dev, 0x40, 0x91);
writeback(dev, 0x41, 0x40);
writeback(dev, 0x43, 0x44);
writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet
* says it is reserved
*/
writeback(dev, 0x45, 0x3a);
writeback(dev, 0x46, 0x88); /* PCI ID lo */
writeback(dev, 0x47, 0xb1); /* PCI ID hi */
/* Bridge control, K8M890 bit 3 should be set to enable VGA on AGP
* (Forward VGA compatible memory and I/O cycles )
*/
writeback(dev, 0x3e, 0x16);
dump_south(dev);
/* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */
tmp = pci_read_config8(dev, PCI_COMMAND);
tmp &= ~0x3;
pci_write_config8(dev, PCI_COMMAND, tmp);
}
static void peg_init(struct device *dev)
{
u8 reg;
printk(BIOS_DEBUG, "Configuring PCIe PEG\n");
dump_south(dev);
/* Disable link. */
reg = pci_read_config8(dev, 0x50);
pci_write_config8(dev, 0x50, reg | 0x10);
/*
* pci_write_config8(dev, 0xe2, 0x0);
* pci_write_config8(dev, 0xe3, 0x92);
*/
/* Bit0 = 1 SDP (Start DLLP) always at Lane0. */
reg = pci_read_config8(dev, 0xb8);
pci_write_config8(dev, 0xb8, reg | 0x1);
/*
* Downstream wait and Upstream Checking Malformed TLP through
* "Byte Enable Rule" And "Over 4K Boundary Rule".
*/
reg = pci_read_config8(dev, 0xa4);
pci_write_config8(dev, 0xa4, reg | 0x30);
pcie_common_init(dev);
}
static void ctrl_init(struct device *dev)
{
/*
* TODO: Fix some ordering issue for V-link set Rx77[6] and
* PCI1_Rx4F[0] should to 1.
* FIXME DO you need?
*/
/*
* VT8237R specific configuration. Other SB are done in their own
* directories. TODO: Add A version.
*/
device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237S_LPC, 0);
if (devsb) {
vt8237s_vlink_init(dev);
}
devsb = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237A_LPC, 0);
if (devsb) {
vt8237a_vlink_init(dev);
}
/* Configure PCI1 and copy mirror registers from D0F3. */
vt8237_cfg(dev);
dump_south(dev);
}
static void host_enable(struct device *dev)
{
/* Multiple function control */
pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
print_debug(" VIA_X_0 device dump:\n");
dump_south(dev);
}
/* This fine tunes the HT link settings, which were loaded by ROM strap. */
static void host_ctrl_enable_k8t8xx(struct device *dev)
{
/*
* Bit 4 is reserved but set by AW. Set PCI to HT outstanding
* requests to 3.
*/
pci_write_config8(dev, 0xa0, 0x13);
/*
* NVRAM I/O base at K8T890_NVRAM_IO_BASE
* Some bits are set and reserved.
*/
pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
/* enable NB NVRAM and enable non-posted PCI writes. */
pci_write_config8(dev, 0xa1, 0x8f);
/* Arbitration control, some bits are reserved. */
pci_write_config8(dev, 0xa5, 0x3c);
/* Arbitration control 2 */
pci_write_config8(dev, 0xa6, 0x80);
/* this will be possibly removed, when I figure out
* if the ROM SIP is good, second reason is that the
* unknown bits are AGP related, which are dummy on K8T890
*/
writeback(dev, 0xa0, 0x13); /* Bit4 is reserved! */
writeback(dev, 0xa1, 0x8e); /* Some bits are reserved. */
writeback(dev, 0xa2, 0x0e); /* I/O NVRAM base 0xe00-0xeff disabled. */
writeback(dev, 0xa3, 0x31);
writeback(dev, 0xa4, 0x30);
writeback(dev, 0xa5, 0x3c); /* Some bits reserved. */
writeback(dev, 0xa6, 0x80); /* Some bits reserved. */
writeback(dev, 0xa7, 0x86); /* Some bits reserved. */
writeback(dev, 0xa8, 0x7f); /* Some bits reserved. */
writeback(dev, 0xa9, 0xcf); /* Some bits reserved. */
writeback(dev, 0xaa, 0x44);
writeback(dev, 0xab, 0x22);
writeback(dev, 0xac, 0x35); /* Maybe bit0 is read-only? */
writeback(dev, 0xae, 0x22);
writeback(dev, 0xaf, 0x40);
/* b0 is missing. */
writeback(dev, 0xb1, 0x13);
writeback(dev, 0xb4, 0x02); /* Some bits are reserved. */
writeback(dev, 0xc0, 0x20);
writeback(dev, 0xc1, 0xaa);
writeback(dev, 0xc2, 0xaa);
writeback(dev, 0xc3, 0x02);
writeback(dev, 0xc4, 0x50);
writeback(dev, 0xc5, 0x50);
printk(BIOS_DEBUG, " VIA_X_2 device dump:\n");
dump_south(dev);
}
static void pcie_init(struct device *dev)
{
u8 reg;
printk(BIOS_DEBUG, "Configuring PCIe PEXs\n");
dump_south(dev);
/* Disable link. */
reg = pci_read_config8(dev, 0x50);
pci_write_config8(dev, 0x50, reg | 0x10);
pcie_common_init(dev);
}
static void pcie_common_init(struct device *dev)
{
u8 reg;
int i, up;
/* Disable downstream read cycle retry,
* otherwise the bus scan will hang if no device is plugged in. */
reg = pci_read_config8(dev, 0xa3);
pci_write_config8(dev, 0xa3, reg & ~0x01);
/* Use PHY negotiation for lane config */
reg = pci_read_config8(dev, 0xc1);
pci_write_config8(dev, 0xc1, reg & ~0x1f);
/* Award has 0xb, VIA recommends 0xd, default 0x8.
* bit4: receive polarity change control
* bits3:2: squelch window select 64~175mv
* bit1: Number of non-idle bits detected before exiting idle state
* 0: 10 bits, 1: 2 bits
* bit0: Number of idle bits detected before entering idle state
* 0: 10 bits, 1: 2 bits
*/
pci_write_config8(dev, 0xe1, 0xb);
/* Set replay timer limit. */
pci_write_config8(dev, 0xb1, 0xf0);
/* Enable link. */
reg = pci_read_config8(dev, 0x50);
pci_write_config8(dev, 0x50, reg & ~0x10);
/* Wait up to 100ms for link to come up */
up = 0;
for (i=0; i<1000; i++) {
if (pci_read_config16(dev, 0x52) & (1<<13)) {
up = 1;
break;
}
udelay(100);
}
printk(BIOS_SPEW, "%s PCIe link ", dev_path(dev));
if (up)
printk(BIOS_SPEW, "up after %d us\n", i*100);
else
printk(BIOS_SPEW, "timeout\n");
dump_south(dev);
}
static void error_enable(struct device *dev)
{
print_debug(" K8x8xx: Enabling NB error reporting: ");
/*
* bit0 - Enable V-link parity error reporting in 0x50 bit0 (RWC)
* bit6 - Parity Error/SERR# Report Through V-Link to SB
* bit7 - Parity Error/SERR# Report Through NMI
*/
pci_write_config8(dev, 0x58, 0x81);
print_debug("Done\n");
/* TODO: enable AGP errors reporting on K8M890 */
print_debug(" VIA_X_1 device dump:\n");
dump_south(dev);
}
