static int __devinit dw_spi_c2000_probe(struct platform_device *pdev) { struct dw_spi_c2000 *dwsmmio; struct dw_spi *dws; struct resource *mem, *ioarea; struct spi_controller_pdata *pdata; struct clk *clk_spi; int ret; pdata = pdev->dev.platform_data; if(!pdata) { ret = -EINVAL; goto err_end; } dwsmmio = kzalloc(sizeof(struct dw_spi_c2000), GFP_KERNEL); if (!dwsmmio) { ret = -ENOMEM; goto err_end; } dws = &dwsmmio->dws; clk_spi = clk_get(NULL,pdata->clk_name); if (IS_ERR(clk_spi)) { ret = PTR_ERR(clk_spi); pr_err("%s:Unable to obtain spi clock: %d\n",\ __func__, ret); goto err_kfree; } dws->clk_spi=clk_spi; dws->max_freq = clk_get_rate(dws->clk_spi); printk ("%s:Initializing SPI Controller : use_dma=%d CLK(%s)=%d Hz\n", __func__, \ pdata->use_dma, pdata->clk_name, dws->max_freq); if(memcmp(pdata->clk_name, "DUS", 3)) c2000_block_reset(COMPONENT_AXI_LEGACY_SPI, 0); else c2000_block_reset(COMPONENT_AXI_FAST_SPI, 0); if(pdata->use_dma) /* DMA */ { ret = dw_spi_dma_init(dws); if (ret) goto err_clk; } dws->bus_num = pdata->bus_num; dws->num_cs = pdata->num_chipselects; /* Get basic io resource and map it */ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!mem) { dev_err(&pdev->dev, "no mem resource?\n"); ret = -EINVAL; goto err_clk; } ioarea = request_mem_region(mem->start, resource_size(mem), pdev->name); if (!ioarea) { dev_err(&pdev->dev, "SPI region already claimed\n"); ret = -EBUSY; goto err_clk; } dws->regs = ioremap_nocache(mem->start, resource_size(mem)); if (!dws->regs) { dev_err(&pdev->dev, "SPI region already mapped\n"); ret = -ENOMEM; goto err_release_reg; } dws->irq = platform_get_irq(pdev, 0); if (dws->irq < 0) { dev_err(&pdev->dev, "no irq resource?\n"); ret = dws->irq; /* -ENXIO */ goto err_unmap; } dws->parent_dev = &pdev->dev; ret = dw_spi_add_host(dws); if (ret) goto err_unmap; platform_set_drvdata(pdev, dwsmmio); return 0; err_unmap: iounmap(dws->regs); err_release_reg: release_mem_region(mem->start, resource_size(mem)); err_clk: if(memcmp(pdata->clk_name, "DUS", 3)) c2000_block_reset(COMPONENT_AXI_LEGACY_SPI, 1); else c2000_block_reset(COMPONENT_AXI_FAST_SPI, 1); clk_put(dws->clk_spi); err_kfree: kfree(dwsmmio); err_end: return ret; }
static int rockchip_spi_probe(struct platform_device *pdev) { struct resource *mem_res; struct rockchip_spi_driver_data *sdd; struct rockchip_spi_info *info = pdev->dev.platform_data; struct dw_spi *dws; int ret, irq; char clk_name[16]; if (!info && pdev->dev.of_node) { info = rockchip_spi_parse_dt(&pdev->dev); if (IS_ERR(info)) return PTR_ERR(info); } if (!info) { dev_err(&pdev->dev, "platform_data missing!\n"); return -ENODEV; } sdd = kzalloc(sizeof(struct rockchip_spi_driver_data), GFP_KERNEL); if (!sdd) { ret = -ENOMEM; goto err_kfree; } sdd->pdev = pdev; sdd->info = info; dws = &sdd->dws; atomic_set(&dws->debug_flag, 0);//debug flag /* Get basic io resource and map it */ irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); return irq; } mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (mem_res == NULL) { dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); ret = -ENXIO; goto err_unmap; } dws->regs = ioremap(mem_res->start, (mem_res->end - mem_res->start) + 1); if (!dws->regs){ ret = -EBUSY; goto err_unmap; } dws->paddr = mem_res->start; dws->iolen = (mem_res->end - mem_res->start) + 1; printk(KERN_INFO "dws->regs: %p\n", dws->regs); //get bus num if (pdev->dev.of_node) { ret = of_alias_get_id(pdev->dev.of_node, "spi"); if (ret < 0) { dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); goto err_release_mem; } info->bus_num = ret; } else { info->bus_num = pdev->id; } /* Setup clocks */ sdd->clk_spi = devm_clk_get(&pdev->dev, "spi"); if (IS_ERR(sdd->clk_spi)) { dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); ret = PTR_ERR(sdd->clk_spi); goto err_clk; } if (clk_prepare_enable(sdd->clk_spi)) { dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); ret = -EBUSY; goto err_clk; } sprintf(clk_name, "pclk_spi%d", info->src_clk_nr); sdd->pclk_spi = devm_clk_get(&pdev->dev, clk_name); if (IS_ERR(sdd->pclk_spi)) { dev_err(&pdev->dev, "Unable to acquire clock '%s'\n", clk_name); ret = PTR_ERR(sdd->pclk_spi); goto err_pclk; } if (clk_prepare_enable(sdd->pclk_spi)) { dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); ret = -EBUSY; goto err_pclk; } clk_set_rate(sdd->clk_spi, info->spi_freq); dws->max_freq = clk_get_rate(sdd->clk_spi); dws->parent_dev = &pdev->dev; dws->bus_num = info->bus_num; dws->num_cs = info->num_cs; dws->irq = irq; dws->clk_spi = sdd->clk_spi; dws->pclk_spi = sdd->pclk_spi; /* * handling for rockchip paltforms, like dma setup, * clock rate, FIFO depth. */ #ifdef CONFIG_SPI_ROCKCHIP_DMA ret = dw_spi_dma_init(dws); if (ret) printk("%s:fail to init dma\n",__func__); #endif ret = dw_spi_add_host(dws); if (ret) goto err_release_mem; platform_set_drvdata(pdev, sdd); printk("%s:num_cs=%d,irq=%d,freq=%d ok\n",__func__, info->num_cs, irq, dws->max_freq); return 0; err_release_mem: release_mem_region(mem_res->start, (mem_res->end - mem_res->start) + 1); err_pclk: clk_disable_unprepare(sdd->pclk_spi); err_clk: clk_disable_unprepare(sdd->clk_spi); err_unmap: iounmap(dws->regs); err_kfree: kfree(sdd); return ret; }