static int ddr_training_hardware(unsigned int mode)
{
int result = 0;
int timeout = 500000;
unsigned int pir_val = DDRP_PIR_INIT;
pir_val |= DDRP_PIR_QSTRN | DDRP_PIR_DLLLOCK;
// if(IS_BYPASS_MODE(mode))
// pir_val |= DDRP_PIR_DLLBYP | (1 << 29);
ddr_writel(pir_val, DDRP_PIR);
while ((ddr_readl(DDRP_PGSR) != (DDRP_PGSR_IDONE
| DDRP_PGSR_DLDONE
| DDRP_PGSR_ZCDONE
| DDRP_PGSR_DIDONE
| DDRP_PGSR_DTDONE))
&& !(ddr_readl(DDRP_PGSR)
& (DDRP_PGSR_DTDONE | DDRP_PGSR_DTERR | DDRP_PGSR_DTIERR))
&& --timeout);
if (timeout == 0) {
dwc_debug("DDR training timeout\n");
result = -1;
} else if (ddr_readl(DDRP_PGSR)
& (DDRP_PGSR_DTERR | DDRP_PGSR_DTIERR)) {
dwc_debug("DDR hardware training error\n");
result = ddr_readl(DDRP_PGSR);
}
return result;
}
static int ddr_training_software(unsigned int mode)
{
unsigned int result = 0;
unsigned int ddr_bl, ddr_cl;
unsigned int mr0_tmp = 1;
unsigned int cs0;
unsigned int cs1;
unsigned int tmp = 0;
dwc_debug("Now try soft training\n");
#ifdef CONFIG_DDR_HOST_CC
cs0 = CONFIG_DDR_CS0;
cs1 = CONFIG_DDR_CS1;
#else /* CONFIG_DDR_HOST_CC */
cs0 = ddr_params_p->cs0;
cs1 = ddr_params_p->cs1;
#endif /* CONFIG_DDR_HOST_CC */
if (dqs_gate_train(cs0 + cs1, 4)) {
dwc_debug("DDR soft train fail too!!!\n");
dump_ddrp_register();
result = 1;
}
if((result) && (!cs1)){
printf("try again to soft train may be the problem for cs\n");
tmp = ddr_readl(DDRC_CFG);
tmp |= 3 << 6;
ddr_writel(tmp, DDRC_CFG);
if (dqs_gate_train(cs0, 4)) {
dwc_debug("try again DDR soft train fail too please check the hardware!!!\n");
dump_ddrp_register();
result = -1;
}
}
#ifdef CONFIG_DDR_HOST_CC
ddr_bl = DDR_BL;
ddr_cl = DDR_CL;
#else /* CONFIG_DDR_HOST_CC */
ddr_cl = ddr_params_p->cl;
ddr_bl = ddr_params_p->bl;
#endif /* CONFIG_DDR_HOST_CC */
if(DDR_TYPE_MODE(mode) == LPDDR){
while (ddr_bl >> mr0_tmp)
mr0_tmp++;
ddr_writel((ddr_cl << 4) | (mr0_tmp - 1), DDRP_MR0);
send_MR0(ddr_readl(DDRP_MR0));
}
return result;
}
void ddr_phy_init(unsigned int mode)
{
unsigned int timeout = 10000, i;
unsigned int mr0_tmp = 1;
bool soft_training = false;
unsigned int ddr_bl, ddr_cl;
dwc_debug("DDR PHY init\n");
ddr_writel(0x150000, DDRP_DTAR);
/* DDR training address set*/
ddr_phy_param_init(mode);
ddr_chip_init(mode);
ddr_training(mode);
ddr_impedance_matching();
dwc_debug("DDR PHY init OK\n");
}
static void ddr_training(unsigned int mode)
{
unsigned int training_state = -1;
dwc_debug("DDR training\n");
#ifndef CONFIG_DDR_FORCE_SOFT_TRAINING
training_state = ddr_training_hardware(mode);
#endif
if(training_state)
{
int i = 0;
for (i = 0; i < 4; i++) {
dwc_debug("DX%dGSR0: %x\n", i, ddr_readl(DDRP_DXGSR0(i)));
}
dump_ddrp_register();
#ifdef CONFIG_SPL_DDR_SOFT_TRAINING
training_state = ddr_training_software(mode);
#endif // CONFIG_SPL_DDR_SOFT_TRAINING
}
if(DDR_TYPE_MODE(mode) == LPDDR)
training_state = lpddr_retrain_bypass();
if(training_state)
hang();
}
static void ddr_chip_init(unsigned int mode)
{
int timeout = 10000;
unsigned int pir_val = DDRP_PIR_INIT;
unsigned int val;
dwc_debug("DDR chip init\n");
// DDRP_PIR_DRAMRST for ddr3 only
#ifndef CONFIG_FPGA
pir_val |= DDRP_PIR_DRAMINT | DDRP_PIR_DLLSRST;
#else
pir_val |= DDRP_PIR_DRAMINT | DDRP_PIR_DRAMRST | DDRP_PIR_DLLBYP;
#endif
// if(IS_BYPASS_MODE(mode)) {
// pir_val |= DDRP_PIR_DLLBYP | (1 << 29);
// pir_val &= ~DDRP_PIR_DLLSRST;
// // DLL Disable: only bypassmode
// ddr_writel(0x1 << 31, DDRP_ACDLLCR);
// val = ddr_readl(DDRP_DSGCR);
// /* LPDLLPD: only for ddr bypass mode
// * Low Power DLL Power Down: Specifies if set that the PHY should respond to the *
// * DFI low power opportunity request and power down the DLL of the PHY if the *
// * wakeup time request satisfies the DLL lock time */
// val &= ~(1 << 4);
// ddr_writel(val,DDRP_DSGCR);
//
// val = ddr_readl(DDRP_DLLGCR);
// val |= 1 << 23;
// ddr_writel(val,DDRP_DLLGCR);
//
// }
ddr_writel(pir_val, DDRP_PIR);
while (!(ddr_readl(DDRP_PGSR) == (DDRP_PGSR_IDONE
| DDRP_PGSR_DLDONE
| DDRP_PGSR_ZCDONE
| DDRP_PGSR_DIDONE))
&& (ddr_readl(DDRP_PGSR) != 0x1f)
&& --timeout);
if (timeout == 0) {
printf("DDR init timeout: PGSR=%X\n", ddr_readl(DDRP_PGSR));
hang();
}
}
/**
* This function cancels an I/O request from an EP.
*/
static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
{
dwc_debug("%s(%p,%p)\n", __func__, usb_ep, usb_req);
if (!usb_ep || !usb_req) {
DWC_WARN("bad argument\n");
return -EINVAL;
}
if (!gadget_wrapper->driver ||
gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
DWC_WARN("bogus device state\n");
return -ESHUTDOWN;
}
if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) {
return -EINVAL;
}
return 0;
}
void ddr_controller_init(void)
{
dwc_debug("DDR Controller init\n");
// dsqiu
// mdelay(1);
ddr_writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, DDRC_CTRL);
ddr_writel(0, DDRC_CTRL);
/* DDRC CFG init*/
ddr_writel(DDRC_CFG_VALUE, DDRC_CFG);
/* DDRC timing init*/
ddr_writel(DDRC_TIMING1_VALUE, DDRC_TIMING(1));
ddr_writel(DDRC_TIMING2_VALUE, DDRC_TIMING(2));
ddr_writel(DDRC_TIMING3_VALUE, DDRC_TIMING(3));
ddr_writel(DDRC_TIMING4_VALUE, DDRC_TIMING(4));
ddr_writel(DDRC_TIMING5_VALUE, DDRC_TIMING(5));
ddr_writel(DDRC_TIMING6_VALUE, DDRC_TIMING(6));
/* DDRC memory map configure*/
ddr_writel(DDRC_MMAP0_VALUE, DDRC_MMAP0);
ddr_writel(DDRC_MMAP1_VALUE, DDRC_MMAP1);
ddr_writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, DDRC_CTRL);
ddr_writel(DDRC_REFCNT_VALUE, DDRC_REFCNT);
ddr_writel(DDRC_CTRL_VALUE, DDRC_CTRL);
}
/* DDR sdram init */
void sdram_init(void)
{
int type = VARIABLE;
unsigned int mode;
unsigned int bypass = 0;
unsigned int rate;
#ifdef CONFIG_DDR_TYPE_DDR3
type = DDR3;
#endif
#ifdef CONFIG_DDR_TYPE_LPDDR
type = LPDDR;
#endif
#ifdef CONFIG_DDR_TYPE_LPDDR2
type = LPDDR2;
#endif
#ifdef CONFIG_DDR_TYPE_DDR2
type = DDR2;
#endif
#ifndef CONFIG_DDR_HOST_CC
struct ddrc_reg ddrc;
struct ddrp_reg ddrp;
#ifndef CONFIG_DDR_TYPE_VARIABLE
struct ddr_params ddr_params;
ddr_params_p = &ddr_params;
#else
ddr_params_p = &gd->arch.gi->ddr_params;
ddr_params_p->freq = gd->arch.gi->cpufreq / gd->arch.gi->ddr_div;
#endif
fill_in_params(ddr_params_p, type);
ddr_params_creator(&ddrc, &ddrp, ddr_params_p);
ddr_params_assign(&ddrc, &ddrp, ddr_params_p);
#endif /* CONFIG_DDR_HOST_CC */
dwc_debug("sdram init start\n");
#ifndef CONFIG_FPGA
clk_set_rate(DDR, gd->arch.gi->ddrfreq);
reset_dll();
rate = clk_get_rate(DDR);
#else
rate = gd->arch.gi->ddrfreq;
#endif
#ifdef CONFIG_M200
if(rate <= 150000000)
bypass = 1;
#endif
reset_controller();
#ifdef CONFIG_DDR_AUTO_SELF_REFRESH
ddr_writel(0x0 ,DDRC_AUTOSR_EN);
#endif
/*force CKE1 HIGH*/
ddr_writel(DDRC_CFG_VALUE, DDRC_CFG);
ddr_writel((1 << 1), DDRC_CTRL);
mode = (type << 1) | (bypass & 1);
/* DDR PHY init*/
ddr_phy_init(mode);
dump_ddrp_register();
ddr_writel(0, DDRC_CTRL);
/* DDR Controller init*/
ddr_controller_init();
dump_ddrc_register();
/* DDRC address remap configure*/
// mem_remap();
ddr_writel(ddr_readl(DDRC_STATUS) & ~DDRC_DSTATUS_MISS, DDRC_STATUS);
#ifdef CONFIG_DDR_AUTO_SELF_REFRESH
if(!bypass)
ddr_writel(0 , DDRC_DLP);
ddr_writel(0x1 ,DDRC_AUTOSR_EN);
#endif
dwc_debug("sdram init finished\n");
#undef DDRTYPE
}
