/**
* Dump global registers and either host or device registers (depending on the
* current mode of the core).
*/
static ssize_t regdump_show( struct device *_dev,
struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = _dev->platform_data;
dwc_otg_dump_global_registers( otg_dev->core_if);
if (dwc_otg_is_host_mode(otg_dev->core_if)) {
dwc_otg_dump_host_registers( otg_dev->core_if);
} else {
dwc_otg_dump_dev_registers( otg_dev->core_if);
}
return sprintf( buf, "Register Dump\n" );
}
/**
* Dump global registers and either host or device registers (depending on the
* current mode of the core).
*/
static ssize_t regdump_show(struct device *_dev,
struct device_attribute *attr,
char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
dwc_otg_dump_global_registers(otg_dev->core_if);
if (dwc_otg_is_host_mode(otg_dev->core_if))
dwc_otg_dump_host_registers(otg_dev->core_if);
else
dwc_otg_dump_dev_registers(otg_dev->core_if);
return sprintf(buf, "Register Dump\n");
}
/**
* Dump global registers and either host or device registers (depending on the
* current mode of the core).
*/
static ssize_t regdump_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifdef DEBUG
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
printk("%s otg_dev=0x%p\n", __FUNCTION__, otg_dev);
dwc_otg_dump_global_registers( otg_dev->core_if);
if (dwc_otg_is_host_mode(otg_dev->core_if)) {
dwc_otg_dump_host_registers( otg_dev->core_if);
} else {
dwc_otg_dump_dev_registers( otg_dev->core_if);
}
#endif
return sprintf( buf, "Register Dump\n" );
}
/**
* Dump global registers and either host or device registers (depending on the
* current mode of the core).
*/
static ssize_t regdump_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = get_otg_dev();
DWC_PRINTF("otg_dev:%p\n", otg_dev);
DWC_PRINTF("core_if:%p\n", otg_dev->core_if);
dwc_otg_dump_global_registers(otg_dev->core_if);
if (dwc_otg_is_host_mode(otg_dev->core_if)) {
dwc_otg_dump_host_registers(otg_dev->core_if);
} else {
dwc_otg_dump_dev_registers(otg_dev->core_if);
}
return sprintf(buf, "Register Dump\n");
}
/**
* Dump global registers and either host or device registers (depending on the
* current mode of the core).
*/
static ssize_t regdump_show( struct device *_dev,
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
struct device_attribute *attr,
#endif
char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
dwc_otg_dump_global_registers( otg_dev->core_if);
if (dwc_otg_is_host_mode(otg_dev->core_if)) {
dwc_otg_dump_host_registers( otg_dev->core_if);
} else {
dwc_otg_dump_dev_registers( otg_dev->core_if);
}
return sprintf( buf, "Register Dump\n" );
}
/**
* Set the register offset for the next Register Access Read/Write
*/
static ssize_t regoffset_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t offset = simple_strtoul(buf, NULL, 16);
#if defined(PCI_INTERFACE)
if (offset < 0x00040000) {
#else
if (offset < SZ_256K) {
#endif
otg_dev->reg_offset = offset;
} else {
dev_err(_dev, "invalid offset\n");
}
return count;
}
DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);
/**
* Show the value of the register at the offset in the reg_offset
* attribute.
*/
static ssize_t regvalue_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t val;
volatile uint32_t *addr;
if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
/* Calculate the address */
addr = (uint32_t *)(otg_dev->reg_offset +
(uint8_t *)otg_dev->base);
val = dwc_read_reg32(addr);
return snprintf(buf,
sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1,
"Reg@0x%06x = 0x%08x\n", otg_dev->reg_offset,
val);
} else {
dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->reg_offset);
return sprintf(buf, "invalid offset\n");
}
}
/**
* Store the value in the register at the offset in the reg_offset
* attribute.
*
*/
static ssize_t regvalue_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
volatile uint32_t *addr;
uint32_t val = simple_strtoul(buf, NULL, 16);
/* dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val); */
if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
/* Calculate the address */
addr = (uint32_t *)(otg_dev->reg_offset +
(uint8_t *)otg_dev->base);
dwc_write_reg32(addr, val);
} else {
dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
otg_dev->reg_offset);
}
return count;
}
DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);
/*
* Attributes
*/
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC");
/* DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); */
/* DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); */
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected");
DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL");
DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,
&(otg_dev->core_if->core_global_regs->gusbcfg),
"GUSBCFG");
DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,
&(otg_dev->core_if->core_global_regs->grxfsiz),
"GRXFSIZ");
DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,
&(otg_dev->core_if->core_global_regs->gnptxfsiz),
"GNPTXFSIZ");
DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,
&(otg_dev->core_if->core_global_regs->gpvndctl),
"GPVNDCTL");
DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,
&(otg_dev->core_if->core_global_regs->ggpio),
"GGPIO");
DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),
"GUID");
DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,
&(otg_dev->core_if->core_global_regs->gsnpsid),
"GSNPSID");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed");
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed");
DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,
&(otg_dev->core_if->core_global_regs->hptxfsiz),
"HPTXFSIZ");
DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0");
/**
* @todo Add code to initiate the HNP.
*/
/**
* Show the HNP status bit
*/
static ssize_t hnp_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
return sprintf(buf, "HstNegScs = 0x%x\n",
dwc_otg_get_hnpstatus(otg_dev->core_if));
}
/**
* Set the HNP Request bit
*/
static ssize_t hnp_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t in = simple_strtoul(buf, NULL, 16);
dwc_otg_set_hnpreq(otg_dev->core_if, in);
return count;
}
DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
/**
* @todo Add code to initiate the SRP.
*/
/**
* Show the SRP status bit
*/
static ssize_t srp_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifndef DWC_HOST_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
return sprintf(buf, "SesReqScs = 0x%x\n",
dwc_otg_get_srpstatus(otg_dev->core_if));
#else
return sprintf(buf, "Host Only Mode!\n");
#endif
}
/**
* Set the SRP Request bit
*/
static ssize_t srp_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifndef DWC_HOST_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
if (NULL != otg_dev->pcd)
dwc_otg_pcd_initiate_srp(otg_dev->pcd);
#endif
return count;
}
DEVICE_ATTR(srp, 0644, srp_show, srp_store);
/**
* @todo Need to do more for power on/off?
*/
/**
* Show the Bus Power status
*/
static ssize_t buspower_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
return sprintf(buf, "Bus Power = 0x%x\n",
dwc_otg_get_prtpower(otg_dev->core_if));
}
/**
* Set the Bus Power status
*/
static ssize_t buspower_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t on = simple_strtoul(buf, NULL, 16);
dwc_otg_set_prtpower(otg_dev->core_if, on);
return count;
}
DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
/**
* @todo Need to do more for suspend?
*/
/**
* Show the Bus Suspend status
*/
static ssize_t bussuspend_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
return sprintf(buf, "Bus Suspend = 0x%x\n",
dwc_otg_get_prtsuspend(otg_dev->core_if));
}
/**
* Set the Bus Suspend status
*/
static ssize_t bussuspend_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t in = simple_strtoul(buf, NULL, 16);
dwc_otg_set_prtsuspend(otg_dev->core_if, in);
return count;
}
DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
/**
* Show the status of Remote Wakeup.
*/
static ssize_t remote_wakeup_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifndef DWC_HOST_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
return sprintf(buf,
"Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n",
dwc_otg_get_remotewakesig(otg_dev->core_if),
dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),
dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));
#else
return sprintf(buf, "Host Only Mode!\n");
#endif /* DWC_HOST_ONLY */
}
/**
* Initiate a remote wakeup of the host. The Device control register
* Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
* flag is set.
*
*/
static ssize_t remote_wakeup_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifndef DWC_HOST_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t val = simple_strtoul(buf, NULL, 16);
if (val & 1)
dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
else
dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
#endif /* DWC_HOST_ONLY */
return count;
}
DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,
remote_wakeup_store);
/**
* Show the whether core is hibernated or not.
*/
static ssize_t rem_wakeup_pwrdn_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifndef DWC_HOST_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
if (dwc_otg_get_core_state(otg_dev->core_if))
DWC_PRINTF("Core is in hibernation\n");
else
DWC_PRINTF("Core is not in hibernation\n");
#endif /* DWC_HOST_ONLY */
return 0;
}
/**
* Initiate a remote wakeup of the device to exit from hibernation.
*/
static ssize_t rem_wakeup_pwrdn_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifndef DWC_HOST_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0);
#endif
return count;
}
DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show,
rem_wakeup_pwrdn_store);
static ssize_t disconnect_us(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifndef DWC_HOST_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t val = simple_strtoul(buf, NULL, 16);
DWC_PRINTF("The Passed value is %04x\n", val);
dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50);
#endif /* DWC_HOST_ONLY */
return count;
}
DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us);
/**
* Dump global registers and either host or device registers (depending on the
* current mode of the core).
*/
static ssize_t regdump_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
#ifdef CONFIG_KONA_USB_CONTROL
/* We want to be able to do this with and without
* USB-PMU-xceiver interface so use direct API
*/
bcm_hsotgctrl_en_clock(true);
dwc_otg_dump_global_registers(otg_dev->core_if);
if (dwc_otg_is_host_mode(otg_dev->core_if))
dwc_otg_dump_host_registers(otg_dev->core_if);
else
dwc_otg_dump_dev_registers(otg_dev->core_if);
bcm_hsotgctrl_en_clock(false);
#else
dwc_otg_dump_global_registers(otg_dev->core_if);
if (dwc_otg_is_host_mode(otg_dev->core_if))
dwc_otg_dump_host_registers(otg_dev->core_if);
else
dwc_otg_dump_dev_registers(otg_dev->core_if);
#endif
return sprintf(buf, "Register Dump\n");
}
DEVICE_ATTR(regdump, S_IRUGO | S_IWUSR, regdump_show, 0);
/**
* Dump global registers and either host or device registers (depending on the
* current mode of the core).
*/
static ssize_t spramdump_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
dwc_otg_dump_spram(otg_dev->core_if);
return sprintf(buf, "SPRAM Dump\n");
}
DEVICE_ATTR(spramdump, S_IRUGO | S_IWUSR, spramdump_show, 0);
/**
* Dump the current hcd state.
*/
static ssize_t hcddump_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifndef DWC_DEVICE_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
dwc_otg_hcd_dump_state(otg_dev->hcd);
#endif /* DWC_DEVICE_ONLY */
return sprintf(buf, "HCD Dump\n");
}
DEVICE_ATTR(hcddump, S_IRUGO | S_IWUSR, hcddump_show, 0);
/**
* Dump the average frame remaining at SOF. This can be used to
* determine average interrupt latency. Frame remaining is also shown for
* start transfer and two additional sample points.
*/
static ssize_t hcd_frrem_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifndef DWC_DEVICE_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
dwc_otg_hcd_dump_frrem(otg_dev->hcd);
#endif /* DWC_DEVICE_ONLY */
return sprintf(buf, "HCD Dump Frame Remaining\n");
}
DEVICE_ATTR(hcd_frrem, S_IRUGO | S_IWUSR, hcd_frrem_show, 0);
/**
* Displays the time required to read the GNPTXFSIZ register many times (the
* output shows the number of times the register is read).
*/
#define RW_REG_COUNT 10000000
#define MSEC_PER_JIFFIE (1000/HZ)
static ssize_t rd_reg_test_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
int i;
int time;
int start_jiffies;
pr_info("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
start_jiffies = jiffies;
for (i = 0; i < RW_REG_COUNT; i++)
dwc_otg_get_gnptxfsiz(otg_dev->core_if);
time = jiffies - start_jiffies;
return sprintf(buf,
"Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
}
DEVICE_ATTR(rd_reg_test, S_IRUGO | S_IWUSR, rd_reg_test_show, 0);
/**
* Displays the time required to write the GNPTXFSIZ register many times (the
* output shows the number of times the register is written).
*/
static ssize_t wr_reg_test_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t reg_val;
int i;
int time;
int start_jiffies;
pr_info("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);
start_jiffies = jiffies;
for (i = 0; i < RW_REG_COUNT; i++)
dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);
time = jiffies - start_jiffies;
return sprintf(buf,
"Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
}
DEVICE_ATTR(wr_reg_test, S_IRUGO | S_IWUSR, wr_reg_test_show, 0);
#ifdef CONFIG_USB_DWC_OTG_LPM
/**
* Show the lpm_response attribute.
*/
static ssize_t lpmresp_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
return sprintf(buf, "** LPM is DISABLED **\n");
if (!dwc_otg_is_device_mode(otg_dev->core_if))
return sprintf(buf, "** Current mode is not device mode\n");
return sprintf(buf, "lpm_response = %d\n",
dwc_otg_get_lpmresponse(otg_dev->core_if));
}
/**
* Store the lpm_response attribute.
*/
static ssize_t lpmresp_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t val = simple_strtoul(buf, NULL, 16);
if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
return 0;
if (!dwc_otg_is_device_mode(otg_dev->core_if))
return 0;
dwc_otg_set_lpmresponse(otg_dev->core_if, val);
return count;
}
DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);
/**
* Show the sleep_status attribute.
*/
static ssize_t sleepstatus_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
return sprintf(buf, "Sleep Status = %d\n",
dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));
}
/**
* Store the sleep_status attribure.
*/
static ssize_t sleepstatus_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
dwc_otg_core_if_t *core_if = otg_dev->core_if;
if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
if (dwc_otg_is_host_mode(core_if)) {
DWC_PRINTF("Host initiated resume\n");
dwc_otg_set_prtresume(otg_dev->core_if, 1);
}
}
return count;
}
DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,
sleepstatus_store);
#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */
/**
* Show the value of Host mode Connection Timeout.
*/
static ssize_t h_conn_wait_tmout_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifndef DWC_DEVICE_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
return sprintf(buf, "Connection wait timeout in ms = %d\n",
otg_dev->hcd->conn_wait_timeout);
#else
return sprintf(buf, "Device Only Mode!\n");
#endif /* #ifndef DWC_DEVICE_ONLY */
}
/**
* Set the value of host mode connection timeout
*
*/
static ssize_t h_conn_wait_tmout_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifndef DWC_DEVICE_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
otg_dev->hcd->conn_wait_timeout = simple_strtoul(buf, NULL, 10);
#endif
return count;
}
DEVICE_ATTR(h_conn_wait_tmout, S_IRUGO | S_IWUSR, h_conn_wait_tmout_show,
h_conn_wait_tmout_store);
/**@}*/
/**
* Create the device files
*/
void dwc_otg_attr_create(
#ifdef LM_INTERFACE
struct lm_device *dev
#elif defined(PCI_INTERFACE)
struct pci_dev *dev
#else
struct platform_device *dev
#endif
)
{
int error;
error = device_create_file(&dev->dev, &dev_attr_regoffset);
error = device_create_file(&dev->dev, &dev_attr_regvalue);
error = device_create_file(&dev->dev, &dev_attr_mode);
error = device_create_file(&dev->dev, &dev_attr_hnpcapable);
error = device_create_file(&dev->dev, &dev_attr_srpcapable);
error = device_create_file(&dev->dev, &dev_attr_hsic_connect);
error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);
error = device_create_file(&dev->dev, &dev_attr_hnp);
error = device_create_file(&dev->dev, &dev_attr_srp);
error = device_create_file(&dev->dev, &dev_attr_buspower);
error = device_create_file(&dev->dev, &dev_attr_bussuspend);
error = device_create_file(&dev->dev, &dev_attr_busconnected);
error = device_create_file(&dev->dev, &dev_attr_gotgctl);
error = device_create_file(&dev->dev, &dev_attr_gusbcfg);
error = device_create_file(&dev->dev, &dev_attr_grxfsiz);
error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);
error = device_create_file(&dev->dev, &dev_attr_gpvndctl);
error = device_create_file(&dev->dev, &dev_attr_ggpio);
error = device_create_file(&dev->dev, &dev_attr_guid);
error = device_create_file(&dev->dev, &dev_attr_gsnpsid);
error = device_create_file(&dev->dev, &dev_attr_devspeed);
error = device_create_file(&dev->dev, &dev_attr_enumspeed);
error = device_create_file(&dev->dev, &dev_attr_hptxfsiz);
error = device_create_file(&dev->dev, &dev_attr_hprt0);
error = device_create_file(&dev->dev, &dev_attr_remote_wakeup);
error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
error = device_create_file(&dev->dev, &dev_attr_disconnect_us);
error = device_create_file(&dev->dev, &dev_attr_regdump);
error = device_create_file(&dev->dev, &dev_attr_spramdump);
error = device_create_file(&dev->dev, &dev_attr_hcddump);
error = device_create_file(&dev->dev, &dev_attr_hcd_frrem);
error = device_create_file(&dev->dev, &dev_attr_rd_reg_test);
error = device_create_file(&dev->dev, &dev_attr_wr_reg_test);
#ifdef CONFIG_USB_DWC_OTG_LPM
error = device_create_file(&dev->dev, &dev_attr_lpm_response);
error = device_create_file(&dev->dev, &dev_attr_sleep_status);
#endif
error = device_create_file(&dev->dev, &dev_attr_h_conn_wait_tmout);
}
/**
* Remove the device files
*/
void dwc_otg_attr_remove(
#ifdef LM_INTERFACE
struct lm_device *dev
#elif defined(PCI_INTERFACE)
struct pci_dev *dev
#else
struct platform_device *dev
#endif
)
{
device_remove_file(&dev->dev, &dev_attr_regoffset);
device_remove_file(&dev->dev, &dev_attr_regvalue);
device_remove_file(&dev->dev, &dev_attr_mode);
device_remove_file(&dev->dev, &dev_attr_hnpcapable);
device_remove_file(&dev->dev, &dev_attr_srpcapable);
device_remove_file(&dev->dev, &dev_attr_hsic_connect);
device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);
device_remove_file(&dev->dev, &dev_attr_hnp);
device_remove_file(&dev->dev, &dev_attr_srp);
device_remove_file(&dev->dev, &dev_attr_buspower);
device_remove_file(&dev->dev, &dev_attr_bussuspend);
device_remove_file(&dev->dev, &dev_attr_busconnected);
device_remove_file(&dev->dev, &dev_attr_gotgctl);
device_remove_file(&dev->dev, &dev_attr_gusbcfg);
device_remove_file(&dev->dev, &dev_attr_grxfsiz);
device_remove_file(&dev->dev, &dev_attr_gnptxfsiz);
device_remove_file(&dev->dev, &dev_attr_gpvndctl);
device_remove_file(&dev->dev, &dev_attr_ggpio);
device_remove_file(&dev->dev, &dev_attr_guid);
device_remove_file(&dev->dev, &dev_attr_gsnpsid);
device_remove_file(&dev->dev, &dev_attr_devspeed);
device_remove_file(&dev->dev, &dev_attr_enumspeed);
device_remove_file(&dev->dev, &dev_attr_hptxfsiz);
device_remove_file(&dev->dev, &dev_attr_hprt0);
device_remove_file(&dev->dev, &dev_attr_remote_wakeup);
device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
device_remove_file(&dev->dev, &dev_attr_disconnect_us);
device_remove_file(&dev->dev, &dev_attr_regdump);
device_remove_file(&dev->dev, &dev_attr_spramdump);
device_remove_file(&dev->dev, &dev_attr_hcddump);
device_remove_file(&dev->dev, &dev_attr_hcd_frrem);
device_remove_file(&dev->dev, &dev_attr_rd_reg_test);
device_remove_file(&dev->dev, &dev_attr_wr_reg_test);
#ifdef CONFIG_USB_DWC_OTG_LPM
device_remove_file(&dev->dev, &dev_attr_lpm_response);
device_remove_file(&dev->dev, &dev_attr_sleep_status);
#endif
device_remove_file(&dev->dev, &dev_attr_h_conn_wait_tmout);
}
/**
* This function is called when the ADP vbus timer expires. Timeout is 1.1s.
*/
static void adp_vbuson_timeout(void *ptr)
{
gpwrdn_data_t gpwrdn;
dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
hprt0_data_t hprt0 = {.d32 = 0 };
pcgcctl_data_t pcgcctl = {.d32 = 0 };
DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__);
if (core_if) {
core_if->adp.vbuson_timer_started = 0;
/* Turn off vbus */
hprt0.b.prtpwr = 1;
DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0);
gpwrdn.d32 = 0;
/* Power off the core */
if (core_if->power_down == 2) {
/* Enable Wakeup Logic */
/* gpwrdn.b.wkupactiv = 1; */
gpwrdn.b.pmuactv = 0;
gpwrdn.b.pwrdnrstn = 1;
gpwrdn.b.pwrdnclmp = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
gpwrdn.d32);
/* Suspend the Phy Clock */
pcgcctl.b.stoppclk = 1;
DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
/* Switch on VDD */
/* gpwrdn.b.wkupactiv = 1;*/
gpwrdn.b.pmuactv = 1;
gpwrdn.b.pwrdnrstn = 1;
gpwrdn.b.pwrdnclmp = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
gpwrdn.d32);
} else {
/* Enable Power Down Logic */
gpwrdn.b.pmuintsel = 1;
gpwrdn.b.pmuactv = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
}
/* Power off the core */
if (core_if->power_down == 2) {
gpwrdn.d32 = 0;
gpwrdn.b.pwrdnswtch = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn,
gpwrdn.d32, 0);
}
/* Unmask SRP detected interrupt from Power Down Logic */
gpwrdn.d32 = 0;
gpwrdn.b.srp_det_msk = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
dwc_otg_adp_probe_start(core_if);
dwc_otg_dump_global_registers(core_if);
dwc_otg_dump_host_registers(core_if);
}
}
/**
* Start the ADP Initial Probe timer to detect if Port Connected interrupt is
* not asserted within 1.1 seconds.
*
* @param core_if the pointer to core_if strucure.
*/
void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if)
{
core_if->adp.vbuson_timer_started = 1;
if (core_if->adp.vbuson_timer)
{
DWC_PRINTF("SCHEDULING VBUSON TIMER\n");
/* 1.1 secs + 60ms necessary for cil_hcd_start*/
DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160);
} else {
DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer);
}
}
#if 0
/**
* Masks all DWC OTG core interrupts
*
*/
static void mask_all_interrupts(dwc_otg_core_if_t * core_if)
{
int i;
gahbcfg_data_t ahbcfg = {.d32 = 0 };
/* Mask Host Interrupts */
/* Clear and disable HCINTs */
for (i = 0; i < core_if->core_params->host_channels; i++) {
DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0);
DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF);
}
/* Clear and disable HAINT */
DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000);
DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF);
/* Mask Device Interrupts */
if (!core_if->multiproc_int_enable) {
/* Clear and disable IN Endpoint interrupts */
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0);
for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
diepint, 0xFFFFFFFF);
}
/* Clear and disable OUT Endpoint interrupts */
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0);
for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
doepint, 0xFFFFFFFF);
}
/* Clear and disable DAINT */
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint,
0xFFFFFFFF);
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0);
} else {
for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
diepeachintmsk[i], 0);
DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
diepint, 0xFFFFFFFF);
}
for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
doepeachintmsk[i], 0);
DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
doepint, 0xFFFFFFFF);
}
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
0);
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint,
0xFFFFFFFF);
}
/* Disable interrupts */
ahbcfg.b.glblintrmsk = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
/* Disable all interrupts. */
DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
/* Clear any pending interrupts */
DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
/* Clear any pending OTG Interrupts */
DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF);
}
/**
* Unmask Port Connection Detected interrupt
*
*/
static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if)
{
gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 };
DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
}
#endif
/**
* Starts the ADP Probing
*
* @param core_if the pointer to core_if structure.
*/
uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if)
{
adpctl_data_t adpctl = {.d32 = 0};
gpwrdn_data_t gpwrdn;
#if 0
adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1,
.b.adp_sns_int = 1, b.adp_tmout_int};
#endif
dwc_otg_disable_global_interrupts(core_if);
DWC_PRINTF("ADP Probe Start\n");
core_if->adp.probe_enabled = 1;
adpctl.b.adpres = 1;
dwc_otg_adp_write_reg(core_if, adpctl.d32);
while (adpctl.b.adpres) {
adpctl.d32 = dwc_otg_adp_read_reg(core_if);
}
adpctl.d32 = 0;
gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
/* In Host mode unmask SRP detected interrupt */
gpwrdn.d32 = 0;
gpwrdn.b.sts_chngint_msk = 1;
if (!gpwrdn.b.idsts) {
gpwrdn.b.srp_det_msk = 1;
}
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
adpctl.b.adp_tmout_int_msk = 1;
adpctl.b.adp_prb_int_msk = 1;
adpctl.b.prb_dschg = 1;
adpctl.b.prb_delta = 1;
adpctl.b.prb_per = 1;
adpctl.b.adpen = 1;
adpctl.b.enaprb = 1;
dwc_otg_adp_write_reg(core_if, adpctl.d32);
DWC_PRINTF("ADP Probe Finish\n");
return 0;
}
/**
* Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted
* within 3 seconds.
*
* @param core_if the pointer to core_if strucure.
*/
void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if)
{
core_if->adp.sense_timer_started = 1;
DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ );
}
/**
* Starts the ADP Sense
*
* @param core_if the pointer to core_if strucure.
*/
uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if)
{
adpctl_data_t adpctl;
DWC_PRINTF("ADP Sense Start\n");
/* Unmask ADP sense interrupt and mask all other from the core */
adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
adpctl.b.adp_sns_int_msk = 1;
dwc_otg_adp_write_reg(core_if, adpctl.d32);
dwc_otg_disable_global_interrupts(core_if); // vahrama
/* Set ADP reset bit*/
adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
adpctl.b.adpres = 1;
dwc_otg_adp_write_reg(core_if, adpctl.d32);
while (adpctl.b.adpres) {
adpctl.d32 = dwc_otg_adp_read_reg(core_if);
}
adpctl.b.adpres = 0;
adpctl.b.adpen = 1;
adpctl.b.enasns = 1;
dwc_otg_adp_write_reg(core_if, adpctl.d32);
dwc_otg_adp_sense_timer_start(core_if);
return 0;
}
