void e_irq_mask(e_irq_type_t irq, e_bool_t state)
{
unsigned previous;
previous = e_reg_read(E_REG_IMASK);
if (state)
e_reg_write(E_REG_IMASK, previous | ( 1<<(irq - E_SYNC)));
else
e_reg_write(E_REG_IMASK, previous & (~(1<<(irq - E_SYNC))));
return;
}
//void check(unsigned int *argu, unsigned int time, unsigned int mask0, unsigned int mask1){
void check(e_core_reg_id_t argu, unsigned int time, unsigned int mask0, unsigned int mask1){
unsigned output = 0x0;
unsigned set0 = 0;
unsigned set1 = 0;
unsigned int m0, m1, current, t;
//unsigned int _RegAdd;
e_core_reg_id_t _RegAdd;
t = time;
_RegAdd = argu;
m0 = mask0;
m1 = mask1;
//get core id
e_coreid_t coreid;
coreid = e_get_coreid();
//save the current data
current = e_reg_read(_RegAdd);
//clear to 0
e_reg_write(_RegAdd, current & m0);
output = e_reg_read(_RegAdd);
if(output != (current & m0)){
set0 = 1;
sprintf(outbuf + strlen(outbuf), "Core 0x%03x set Reg %-20s TO 0 FAILED! The current value is 0x%08x! Expecting 0x%08x!\n", coreid, reg[t], output, current & m0);
}
//set to 1
e_reg_write(_RegAdd, current | m1);
output = e_reg_read(_RegAdd);
if(output != (current | m1)){
set1 = 1;
sprintf(outbuf + strlen(outbuf), "Core 0x%03x set Reg %-20s TO 1 FAILED! The current value is 0x%08x! Expecting 0x%08x!\n", coreid, reg[t], output, current | m1);
}
//clear to 0
e_reg_write(_RegAdd, current & m0);
output = e_reg_read(_RegAdd);
if(output != (current & m0)){
set0 = 1;
sprintf(outbuf + strlen(outbuf), "Core 0x%03x set Reg %-20s TO 0 FAILED! The current value is 0x%08x! Expecting 0x%08x!\n", coreid, reg[t], output, current & m0);
}
if(set1 == 0 & set0 == 0)
sprintf(outbuf + strlen(outbuf), "Core 0x%03x set Reg %-20s HAS PASSED!\n", coreid, reg[t]);
//store the old data
e_reg_write(_RegAdd, current);
}
int main(void) {
int i;
int *pt;
e_irq_attach(E_SW_EXCEPTION, swexception_isr);
e_irq_attach(E_MEM_FAULT, memfault_isr);
e_irq_attach(E_TIMER0_INT, timer0_isr);
e_irq_attach(E_TIMER1_INT, timer1_isr);
e_irq_attach(E_DMA0_INT, dma0_isr);
e_irq_attach(E_DMA1_INT, dma1_isr);
e_irq_attach(E_USER_INT, user_isr);
e_irq_global_mask(E_FALSE);
e_reg_write(E_REG_IMASK,0x0);
//reset the target mem
pt = (int *)0x5200;
for(i=0;i<7;i++)
{
pt[i] = 0x0;
}
while(1) ;
return EXIT_SUCCESS;
}
int main(void)
{
unsigned i;
*signal = start;
//attach the isr handlers
e_irq_attach(E_SW_EXCEPTION, swexception_isr);
e_irq_attach(E_MEM_FAULT, memfault_isr);
e_irq_attach(E_TIMER0_INT, timer0_isr);
e_irq_attach(E_TIMER1_INT, timer1_isr);
e_irq_attach(E_DMA0_INT, dma0_isr);
e_irq_attach(E_DMA1_INT, dma1_isr);
e_irq_attach(E_USER_INT, user_isr);
//enable interrupts
e_irq_global_mask(E_FALSE);
e_reg_write(E_REG_IMASK,0x0);
//initialize the target mem
result = (unsigned *)resultbase;
for(i=0;i<7;i++)
{
result[i] = 0x0;
}
//wait for the finished signal from master
while(*signal != finish) ;
return EXIT_SUCCESS;
}
void check_ILAT(unsigned int num){
unsigned output, current, t;
unsigned set0 = 0;
unsigned set1 = 0;
e_core_reg_id_t _RegAdd;
t = num;
_RegAdd = E_REG_ILAT;
//get core id
e_coreid_t coreid;
coreid = e_get_coreid();
//save the current data
current = e_reg_read(_RegAdd);
//clear to 0
e_reg_write(E_REG_ILATCL, 0xffffffff);
output = e_reg_read(_RegAdd);
if(output != 0x0){
set0 = 1;
sprintf(outbuf + strlen(outbuf), "Core 0x%03x set Reg %-20s TO 0 FAILED! The current value is 0x%08x! Expecting 0x%08x!\n", coreid, reg[t], output, 0x0);
}
//set to 1
e_reg_write(E_REG_ILATST, 0xffffffff);
output = e_reg_read(_RegAdd);
if(output != 0xffffffff){
set1 = 1;
sprintf(outbuf + strlen(outbuf), "Core 0x%03x set Reg %-20s TO 1 FAILED! The current value is 0x%08x! Expecting 0x%08x!\n", coreid, reg[t], output, 0xffffffff);
}
//clear to 0
e_reg_write(E_REG_ILATCL, 0xffffffff);
output = e_reg_read(_RegAdd);
if(output != 0x0){
set0 = 1;
sprintf(outbuf + strlen(outbuf), "Core 0x%03x set Reg %-20s TO 0 FAILED! The current value is 0x%08x! Expecting 0x%08x!\n", coreid, reg[t], output, 0x0);
}
if(set1 == 0 & set0 == 0)
sprintf(outbuf + strlen(outbuf), "Core 0x%03x set Reg %-20s HAS PASSED!\n", coreid, reg[t]);
//store the old data
e_reg_write(_RegAdd, current);
}
int main(void)
{
unsigned k,i,j;
unsigned *dst, *mst;
unsigned tran;
e_dma_desc_t dma_desc;
tran = 128;
dst = (unsigned *)0x2000;
mst = (unsigned *)0x4000;
e_reg_write(E_REG_DMA0CONFIG, 0);
e_reg_write(E_REG_DMA1CONFIG, 0);
// Initialize the buffer in receiver core
for (i=0; i<tran*5; i++)
{
dst[i] = 0x00000000;
}
mst[0] = 0x00000000;
// Initialize the auto dma register in receiver core
e_reg_write(E_REG_DMA0AUTODMA0, 0x00000000);
// Prepare for the descriptor slave dma
e_dma_set_desc(E_DMA_0,(E_DMA_ENABLE|E_DMA_WORD), 0x0000,
0x0000, 0x0004,
0x0400, 0x0001,
0x0000, 0x0000,
0x0000,(void *)dst, &dma_desc);
// Wait for the signal to start dma transfering
while(*mst == 0x00000000){};
e_dma_start(&dma_desc, E_DMA_0);
e_dma_wait(E_DMA_0);
return 0;
}
int trace_start_wait_all()
{
unsigned irqState;
e_irq_global_mask(E_FALSE);
e_irq_attach(E_WAND_INT, wand_trace_isr);
e_irq_mask(E_WAND_INT, E_FALSE);
__asm__ __volatile__("wand"); // Set our WAND bit
__asm__ __volatile__("idle"); // Idle and wait for an interrupt
irqState = e_reg_read(E_REG_STATUS);
irqState = irqState & (~0x8); // This is the WAND interrupt flag
e_reg_write(E_REG_FSTATUS, irqState);
//e_ctimer_start(E_CTIMER_1, E_CTIMER_CLK); // Start counting
return 0;
}
static void sync(void)
{
uint32_t irq_state;
/* enable WAND interrupt */
e_irq_attach(WAND_BIT, wand_trace_isr);
e_irq_mask(WAND_BIT, E_FALSE);
/* WAND + IDLE */
__asm__ __volatile__("wand");
__asm__ __volatile__("idle");
/* acknowledge interrupt */
irq_state = e_reg_read(E_REG_STATUS);
irq_state &= ~WAND_BIT;
e_reg_write(E_REG_STATUS, irq_state);
}
unsigned e_ctimer_stop(e_ctimer_id_t timer)
{
// TODO convert to assembly to eliminate 2 function calls.
unsigned shift;
unsigned mask;
unsigned config;
unsigned count;
shift = (timer) ? 8:4;
mask = 0xf << shift;
config = e_reg_read(E_REG_CONFIG);
// stop the timer
e_reg_write(E_REG_CONFIG, config & (~mask));
count = e_reg_read(timer ? E_REG_CTIMER1 : E_REG_CTIMER0);
return count;
}
int main(void) {
//initialize
int i;
unsigned row, col, delay, num;
unsigned *ivt;
e_irq_global_mask(E_FALSE);
e_irq_attach(E_WAND_INT, wand_isr);
e_irq_mask(E_WAND_INT, E_FALSE);
row = e_group_config.core_row;
col = e_group_config.core_col;
num = row * e_group_config.group_cols + col;
pause = (volatile uint32_t *) (0x7000);
result = (volatile unsigned *) (0x8f000000 + 0x4*num);
delay = 0x2000 * num + 0x2000;
if (num == 0)
*pause = 0;
*result = 0xdeadbeef;
for(i=0; i<0x10000; i++)
{
*result = i;
e_wait(E_CTIMER_0, delay);
if (num == 0)
while ((*pause));
__asm__ __volatile__("wand");
__asm__ __volatile__("idle");
// clear wand bit
state = e_reg_read(E_REG_STATUS);
state = state & (~0x8);
e_reg_write(E_REG_FSTATUS, state);
}
return EXIT_SUCCESS;
}
int main(void)
{
e_coreid_t coreid;
unsigned int *po;
unsigned int reg;
unsigned int p_value;
unsigned int flag3, flag4, flag5;
unsigned int temp;
unsigned int k;
unsigned *pass;
pass = (unsigned *)7000;
po= (unsigned *) 0x600c;
po[0] = 0x00000000;
global_index = (unsigned *)0x80802000;
while(1)
{
pass[0] = (unsigned)0x00000000;
while(po[0] == (unsigned) 0x00000000)
{};
sprintf(outbuf,"");
// Store the previous value of the register
p_value = e_reg_read(*po);
// Disable interrupts
e_irq_global_mask(E_TRUE);
//For register EILAT
// Clear the EILAT
e_reg_write(E_REG_ILATCL, (unsigned)0xffffffff);
temp = e_reg_read(*po);
if (temp == (unsigned)0x00000000)
{
flag3=1;
}
else
{
flag3=0;
sprintf(outbuf,"We get 0x%08x instead of 0x%08x, ILAT\n", temp, 0x00000000);
global_index[0] = global_index[0] + 1;
}
// Set the EILAT
e_reg_write(E_REG_ILATST, (unsigned)0xffffffff);
temp = e_reg_read(*po);
if (temp == (unsigned)0x000003ff)
{
flag4=1;
}else
{
flag4=0;
sprintf(outbuf + strlen(outbuf),"We get 0x%08x instead of 0x%08x, ILAT\n", temp, 0x000003ff);
global_index[0] = global_index[0] + 1;
}
// Clear the EILAT
e_reg_write(E_REG_ILATCL, (unsigned)0xffffffff);
temp = e_reg_read(*po);
if (temp == (unsigned)0x00000000)
{
flag5=1;
}else{
flag5=0;
sprintf(outbuf + strlen(outbuf),"We get 0x%08x instead of 0x%08x, ILAT\n", temp, 0x00000000);
global_index[0] = global_index[0] + 1;
}
if ((flag3 == 1) && (flag4 == 1) && (flag5 == 1))
{
pass[0] = 0xdeadbeef;
}
// Set the register to the previous value
e_reg_write(*po, p_value);
po[0] = (unsigned) 0x00000000;
// Enable the interrupts
e_irq_global_mask(E_FALSE);
}
return EXIT_SUCCESS;
}
int main(void) {
//initialize
int *p0, *p1, *p2;
int core_num, value, fault;
unsigned conf;
int i,j,k,co;
// co = 0;
fault = 0;
for(i=0;i<4;i++)
{
for(j=0;j<4;j++)
{
core_num = i * 4 + j;
//initialize the target mem
p2 = e_get_global_address(i,j,(void *)target);
*p2 = 0x0;
p1 = e_get_global_address(i,j,(void *)E_REG_MULTICAST);
/*
switch(core_num)
{
case 0: *p1 = _Z; break;
case 1: *p1 = _X; break;
case 2: *p1 = _Y; break;
case 3: *p1 = _Z; break;
case 4: *p1 = _W; break;
case 5: *p1 = _Y; break;
case 6: *p1 = _Z; break;
case 7: *p1 = _W; break;
case 8: *p1 = _X; break;
case 9: *p1 = _Z; break;
case 10: *p1 = _W; break;
case 11: *p1 = _X; break;
case 12: *p1 = _Y; break;
case 13: *p1 = _W; break;
case 14: *p1 = _X; break;
case 15: *p1 = _Y; break;
default: break;
}
*/
switch(core_num)
{
case 0: *p1 = _X; break;
case 1: *p1 = _X; break;
case 2: *p1 = _Y; break;
case 3: *p1 = _Y; break;
case 4: *p1 = _X; break;
case 5: *p1 = _X; break;
case 6: *p1 = _Y; break;
case 7: *p1 = _Y; break;
case 8: *p1 = _Z; break;
case 9: *p1 = _Z; break;
case 10: *p1 = _W; break;
case 11: *p1 = _W; break;
case 12: *p1 = _Z; break;
case 13: *p1 = _Z; break;
case 14: *p1 = _W; break;
case 15: *p1 = _W; break;
default: break;
}
}
}
e_wait(E_CTIMER_0, 0x30000);
//set the transaction mod to multicast
conf = e_reg_read(E_REG_CONFIG);
conf = conf & 0xffff0fff;
conf = conf | 0x00003000;
e_reg_write(E_REG_CONFIG, conf);
//do the multicast
p0 = (int *) _Xmail;
*p0 = 0x111;
//wait for some time
// for(k=0;k<50;k++) {co++;}
p0 = (int *) _Ymail;
*p0 = 0x222;
// for(k=0;k<50;k++) {co++;}
p0 = (int *) _Zmail;
*p0 = 0x333;
// for(k=0;k<50;k++) {co++;}
p0 = (int *) _Wmail;
*p0 = 0x444;
//set the transaction mod to regular transaction
conf = e_reg_read(E_REG_CONFIG);
conf = conf & 0xffff0fff;
e_reg_write(E_REG_CONFIG, conf);
e_wait(E_CTIMER_0, 0x30000);
//check the results
for(i=0;i<4;i++)
{
for(j=0;j<4;j++)
{
core_num = i * 4 + j;
//get the target mem address
p2 = e_get_global_address(i,j,(void *)target);
/*
switch(core_num)
{
case 0: value = _Zvalue; break;
case 1: value = _Xvalue; break;
case 2: value = _Yvalue; break;
case 3: value = _Zvalue; break;
case 4: value = _Wvalue; break;
case 5: value = _Yvalue; break;
case 6: value = _Zvalue; break;
case 7: value = _Wvalue; break;
case 8: value = _Xvalue; break;
case 9: value = _Zvalue; break;
case 10: value = _Wvalue; break;
case 11: value = _Xvalue; break;
case 12: value = _Yvalue; break;
case 13: value = _Wvalue; break;
case 14: value = _Xvalue; break;
case 15: value = _Yvalue; break;
default: break;
}
*/
switch(core_num)
{
case 0: value = _Xvalue; break;
case 1: value = _Xvalue; break;
case 2: value = _Yvalue; break;
case 3: value = _Yvalue; break;
case 4: value = _Xvalue; break;
case 5: value = _Xvalue; break;
case 6: value = _Yvalue; break;
case 7: value = _Yvalue; break;
case 8: value = _Zvalue; break;
case 9: value = _Zvalue; break;
case 10: value = _Wvalue; break;
case 11: value = _Wvalue; break;
case 12: value = _Zvalue; break;
case 13: value = _Zvalue; break;
case 14: value = _Wvalue; break;
case 15: value = _Wvalue; break;
default: break;
}
if(*p2 != value)
fault++;
}
}
//check the final result
*mailbox = fault;
return EXIT_SUCCESS;
}
int main(void)
{
unsigned mesh_reg;
unsigned mesh_reg_modify;
unsigned time_c, time_p;
unsigned time;
unsigned tran,k,i,j,h,m,n,q;
unsigned *mailbox, *mode;
unsigned *commander;
unsigned *counter;
unsigned *master, *slave, *p;
unsigned *row, *col;
unsigned *n_row, *n_col;
unsigned *neighbour0, *neighbour1, *neighbour2, *neighbour3;
row = (unsigned *)0x5000;
col = (unsigned *)0x5004;
n_row = (unsigned *)0x5008;
n_col = (unsigned *)0x500c;
master = (unsigned *)0x2000;
p =(unsigned *) 0x2000;
slave = (unsigned *) e_get_global_address(*row, *col, p);
commander = (unsigned *)0x5100;
p = (unsigned *) 0x5300;
counter = (unsigned *) e_get_global_address(*row, *col, p);
mailbox = (unsigned *)0x6000;
mode = (unsigned *)0x5400;
tran = 2048;
// Core number
k = (e_group_config.core_row)*e_group_config.group_cols + (e_group_config.core_col);
// Broadcast to all the other neighbours
p = (unsigned *)0x5100;
e_neighbor_id(E_PREV_CORE, E_ROW_WRAP, n_row, n_col);
neighbour0 = (unsigned *) e_get_global_address(*n_row, *n_col, p) ;
e_neighbor_id(E_NEXT_CORE, E_ROW_WRAP, n_row, n_col);
neighbour1 = (unsigned *) e_get_global_address(*n_row, *n_col, p) ;
e_neighbor_id(E_PREV_CORE, E_COL_WRAP, n_row, n_col);
neighbour2 = (unsigned *) e_get_global_address(*n_row, *n_col, p) ;
e_neighbor_id(E_NEXT_CORE, E_COL_WRAP, n_row, n_col);
neighbour3 = (unsigned *) e_get_global_address(*n_row, *n_col, p) ;
// Initialize master and slave
for(i=0; i<tran; i++)
{
master[i] = 0xdeadbee9;
slave[i] = 0x00000000;
}
while(1)
{
//Clear the mode box
mode[0] = 0xdeadbeef;
// Clear the start commander
commander[0] = 0x00000000;
// Wait for the mesh event
while(mode[0] == 0xdeadbeef)
{};
q = mode[0];
mesh_reg = e_reg_read(E_REG_MESH_CONFIG);
mesh_reg_modify = mesh_reg & 0xffffff0f;
mesh_reg_modify = mesh_reg_modify |mesh_type[1][q];
e_reg_write(E_REG_MESH_CONFIG, mesh_reg_modify);
// Set the ctimer
e_ctimer_set(E_CTIMER_0, E_CTIMER_MAX) ;
// Waiting for the signal to start transfering
while(commander[0] != 0xdeadbeef)
{};
// Start the ctimer and select the time type
time_p = e_ctimer_start(E_CTIMER_0, E_CTIMER_MESH_0);
// Broadcast to all the other neighbours
neighbour0[0] = 0xdeadbeef;
neighbour1[0] = 0xdeadbeef;
neighbour2[0] = 0xdeadbeef;
neighbour3[0] = 0xdeadbeef;
e_dma_copy(slave, master, 0x2000);
// Wait for transfer finishing
while(slave[2047] != 0xdeadbee9 )
{};
counter[k] = 1;
// Get the time now
time_c = e_ctimer_get(E_CTIMER_0);
time = time_p - time_c;
// Output the result
mailbox[q] = time;
// Load the original value of E_REG_MESH_CONFIG
e_reg_write(E_REG_MESH_CONFIG, mesh_reg);
// Check if all the mesh events have been through
if(q == 12)
{
break;
}
}
return 0;
}
int main(void)
{
unsigned mesh_reg;
unsigned mesh_reg_modify;
unsigned time_c, time_p;
unsigned time;
unsigned time_c1, time_p1;
unsigned time1;
unsigned i,j,q,m,n,k;
unsigned *commander;
unsigned *counter;
unsigned *mailbox,*mode;
unsigned *n_row, *n_col;
unsigned *neighbour0, *neighbour1, *neighbour2, *neighbour3, *p;
commander = (unsigned *)0x5100;
counter = (unsigned *)0x5300;
mailbox = (unsigned *)0x6000;
mode = (unsigned *)0x5400;
n_row = (unsigned *)0x5008;
n_col = (unsigned *)0x500c;
p = (unsigned *)0x5100;
// Broadcast to neighbours
e_neighbor_id(E_PREV_CORE, E_ROW_WRAP, n_row, n_col);
neighbour0 = (unsigned *) e_get_global_address(*n_row, *n_col, p) ;
e_neighbor_id(E_NEXT_CORE, E_ROW_WRAP, n_row, n_col);
neighbour1 = (unsigned *) e_get_global_address(*n_row, *n_col, p) ;
e_neighbor_id(E_PREV_CORE, E_COL_WRAP, n_row, n_col);
neighbour2 = (unsigned *) e_get_global_address(*n_row, *n_col, p) ;
e_neighbor_id(E_NEXT_CORE, E_COL_WRAP, n_row, n_col);
neighbour3 = (unsigned *) e_get_global_address(*n_row, *n_col, p) ;
// Get core information
k = e_group_config.core_row * e_group_config.group_cols + e_group_config.core_col;
while(1)
{
// Clear the counter of finishing transfering
for(m=0; m<(e_group_config.group_rows*e_group_config.group_cols); m++)
{
counter[m] = 0;
}
// Initialize the commander and counter
counter[k] = 1;
//Clear the mode box
mode[0] = 0xdeadbeef;
// Clear the start commander
commander[0] = 0x00000000;
// Wait for the mesh event
while(mode[0] == 0xdeadbeef)
{};
q = mode[0];
mesh_reg = e_reg_read(E_REG_MESH_CONFIG);
mesh_reg_modify = mesh_reg & 0xffffff0f;
mesh_reg_modify = mesh_reg_modify |mesh_type[1][q];
e_reg_write(E_REG_MESH_CONFIG, mesh_reg_modify);
// Set the ctimer
e_ctimer_set(E_CTIMER_0, E_CTIMER_MAX) ;
// Waiting for the signal to start transfering
while(commander[0] != 0xdeadbeef)
{};
// Start the ctimer and select the time type
time_p = e_ctimer_start(E_CTIMER_0, E_CTIMER_MESH_0);
// Broadcast to all the other neighbours
neighbour0[0] = 0xdeadbeef;
neighbour1[0] = 0xdeadbeef;
neighbour2[0] = 0xdeadbeef;
neighbour3[0] = 0xdeadbeef;
while((counter[0]&counter[1]&counter[2]&counter[3]&counter[4]&counter[5]&counter[6]
&counter[7]&counter[8]&counter[9]&counter[10]&counter[11]&counter[12]&counter[13]
&counter[14]&counter[15]) == 0) {};
time_c = e_ctimer_get(E_CTIMER_0);
time = time_p - time_c;
mailbox[(*mode)] = time;
// Load the original value to E_REG_MESH_CONFIG system register
e_reg_write(E_REG_MESH_CONFIG, mesh_reg);
if(mode[0] == 12)
{
break;
}
}
return 0;
}
