int iommu_supports_eim(void)
{
struct acpi_drhd_unit *drhd;
int apic;
if ( !iommu_qinval || !iommu_intremap || list_empty(&acpi_drhd_units) )
return 0;
/* We MUST have a DRHD unit for each IOAPIC. */
for ( apic = 0; apic < nr_ioapics; apic++ )
if ( !ioapic_to_drhd(IO_APIC_ID(apic)) )
{
dprintk(XENLOG_WARNING VTDPREFIX,
"There is not a DRHD for IOAPIC %#x (id: %#x)!\n",
apic, IO_APIC_ID(apic));
return 0;
}
for_each_drhd_unit ( drhd )
if ( !ecap_queued_inval(drhd->iommu->ecap) ||
!ecap_intr_remap(drhd->iommu->ecap) ||
!ecap_eim(drhd->iommu->ecap) )
return 0;
return 1;
}
void vtd_dump_iommu_info(unsigned char key)
{
struct acpi_drhd_unit *drhd;
struct iommu *iommu;
int i;
for_each_drhd_unit ( drhd )
{
u32 status = 0;
iommu = drhd->iommu;
printk("\niommu %x: nr_pt_levels = %x.\n", iommu->index,
iommu->nr_pt_levels);
if ( ecap_queued_inval(iommu->ecap) || ecap_intr_remap(iommu->ecap) )
status = dmar_readl(iommu->reg, DMAR_GSTS_REG);
printk(" Queued Invalidation: %ssupported%s.\n",
ecap_queued_inval(iommu->ecap) ? "" : "not ",
(status & DMA_GSTS_QIES) ? " and enabled" : "" );
printk(" Interrupt Remapping: %ssupported%s.\n",
ecap_intr_remap(iommu->ecap) ? "" : "not ",
(status & DMA_GSTS_IRES) ? " and enabled" : "" );
printk(" Interrupt Posting: %ssupported.\n",
cap_intr_post(iommu->cap) ? "" : "not ");
if ( status & DMA_GSTS_IRES )
{
/* Dump interrupt remapping table. */
u64 iremap_maddr = dmar_readq(iommu->reg, DMAR_IRTA_REG);
int nr_entry = 1 << ((iremap_maddr & 0xF) + 1);
struct iremap_entry *iremap_entries = NULL;
int print_cnt = 0;
printk(" Interrupt remapping table (nr_entry=%#x. "
"Only dump P=1 entries here):\n", nr_entry);
printk("R means remapped format, P means posted format.\n");
printk("R: SVT SQ SID V AVL FPD DST DLM TM RH DM P\n");
printk("P: SVT SQ SID V AVL FPD PDA URG P\n");
for ( i = 0; i < nr_entry; i++ )
{
struct iremap_entry *p;
if ( i % (1 << IREMAP_ENTRY_ORDER) == 0 )
{
/* This entry across page boundry */
if ( iremap_entries )
unmap_vtd_domain_page(iremap_entries);
GET_IREMAP_ENTRY(iremap_maddr, i,
iremap_entries, p);
}
else
p = &iremap_entries[i % (1 << IREMAP_ENTRY_ORDER)];
if ( !p->remap.p )
continue;
if ( !p->remap.im )
printk("R: %04x: %x %x %04x %02x %x %x %08x %x %x %x %x %x\n",
i,
p->remap.svt, p->remap.sq, p->remap.sid,
p->remap.vector, p->remap.avail, p->remap.fpd,
p->remap.dst, p->remap.dlm, p->remap.tm, p->remap.rh,
p->remap.dm, p->remap.p);
else
printk("P: %04x: %x %x %04x %02x %x %x %16lx %x %x\n",
i,
p->post.svt, p->post.sq, p->post.sid, p->post.vector,
p->post.avail, p->post.fpd,
((u64)p->post.pda_h << 32) | (p->post.pda_l << 6),
p->post.urg, p->post.p);
print_cnt++;
}
if ( iremap_entries )
unmap_vtd_domain_page(iremap_entries);
if ( iommu_ir_ctrl(iommu)->iremap_num != print_cnt )
printk("Warning: Print %d IRTE (actually have %d)!\n",
print_cnt, iommu_ir_ctrl(iommu)->iremap_num);
}
}
/* Dump the I/O xAPIC redirection table(s). */
if ( iommu_enabled )
{
int apic;
union IO_APIC_reg_01 reg_01;
struct IO_APIC_route_remap_entry *remap;
struct ir_ctrl *ir_ctrl;
for ( apic = 0; apic < nr_ioapics; apic++ )
{
iommu = ioapic_to_iommu(mp_ioapics[apic].mpc_apicid);
ir_ctrl = iommu_ir_ctrl(iommu);
if ( !ir_ctrl || !ir_ctrl->iremap_maddr || !ir_ctrl->iremap_num )
continue;
printk( "\nRedirection table of IOAPIC %x:\n", apic);
/* IO xAPIC Version Register. */
reg_01.raw = __io_apic_read(apic, 1);
printk(" #entry IDX FMT MASK TRIG IRR POL STAT DELI VECTOR\n");
for ( i = 0; i <= reg_01.bits.entries; i++ )
{
struct IO_APIC_route_entry rte =
__ioapic_read_entry(apic, i, TRUE);
remap = (struct IO_APIC_route_remap_entry *) &rte;
if ( !remap->format )
continue;
printk(" %02x: %04x %x %x %x %x %x %x"
" %x %02x\n", i,
remap->index_0_14 | (remap->index_15 << 15),
remap->format, remap->mask, remap->trigger, remap->irr,
remap->polarity, remap->delivery_status, remap->delivery_mode,
remap->vector);
}
}
}
}
