static int _emxx_hc_start(struct usb_hcd *hcd)
{
int nret;
#ifdef CONFIG_MACH_EMGR
u32 val;
val = readl(SMU_OSC1CTRL1);
writel(val & ~0x1, SMU_OSC1CTRL1);
if (val == 0xff) {
while ((readl(SMU_PLL_STATUS) & 0x00100000) == 0)
udelay(10);
}
writel(1, SMU_USBPHY_HOST_FUNC_SEL);
#endif
/* Start Clock */
#ifdef CONFIG_MACH_EMEV
emxx_open_clockgate(EMXX_CLK_USB0 | EMXX_CLK_USB_PCI);
#elif defined(CONFIG_MACH_EMGR)
emxx_open_clockgate(EMXX_CLK_USB0 | EMXX_CLK_USB1 | EMXX_CLK_USB_PCI);
#endif
/* Reset State OFF */
emxx_unreset_device(EMXX_RST_USB0);
#ifdef CONFIG_MACH_EMGR
emxx_unreset_device(EMXX_RST_USB1);
val = readl(IO_ADDRESS(EMXX_USBS1_BASE) + 0x1010) & ~0x1000;
writel(val, IO_ADDRESS(EMXX_USBS1_BASE) + 0x1010);
val = readl(IO_ADDRESS(EMXX_USBS1_BASE) + 0x1014) | 0x80000000;
writel(val, IO_ADDRESS(EMXX_USBS1_BASE) + 0x1014);
#endif
nret = _ahb_pci_bridge_init();
return nret;
}
/* Setup watchdog timer. */
void emxx_wdt_setup(void)
{
unsigned int regval;
unsigned int tm_delay;
struct timer_reg_t *reg = tm_reg[TIMER_WDT].reg;
tm_delay = TIMER_DELAY(TW_CLOCK_TICK_RATE) * 2;
spin_lock(&wdt_spinlock);
writel(readl(SMU_WDT_INT_RESET) | 0x01003003, SMU_WDT_INT_RESET);
emxx_open_clockgate(EMXX_CLK_TIM_P);
emxx_open_clockgate(tm_reg[TIMER_WDT].clkdev);
emxx_unreset_device(tm_reg[TIMER_WDT].rstdev);
/* stop timer for sure. */
reg->tm_op = TSTOP;
/* set counter */
regval = get_tw_count_value(TIMER_WDT, tm_param[TIMER_WDT].usecs);
udelay(tm_delay);
reg->tm_set = regval;
spin_unlock(&wdt_spinlock);
}
static void __init emxx_clocksource_init(void)
{
/* Setup system timer */
writel(0, SMU_STI_CLKSEL); /* 32768 */
emxx_open_clockgate(EMXX_CLK_STI_P | EMXX_CLK_STI_S);
emxx_unreset_device(EMXX_RST_STI);
sti_timer->set_h = 0x80000000;
sti_timer->set_l = 0x00000000;
sti_timer->intenclr = 0x3;
sti_timer->intffclr = 0x3;
clocksource_emxx.mult =
clocksource_hz2mult(32768, clocksource_emxx.shift);
clocksource_register(&clocksource_emxx);
}
/*
* Init CFI module
*/
static void emxx_cfi_enable(void)
{
u32 val;
#ifdef CONFIG_MACH_EMEV
if ((system_rev & EMXX_REV_MASK) != EMXX_REV_ES1) {
#endif /* CONFIG_MACH_EMEV */
emxx_reset_device(EMXX_RST_CFI);
emxx_close_clockgate(EMXX_CLK_CFI | EMXX_CLK_CFI_H);
/* card power on */
pwc_reg_write(DA9052_LDO8_REG, 0x6A);
udelay(300);
#ifdef CONFIG_MACH_EMEV
}
#endif /* CONFIG_MACH_EMEV */
emxx_open_clockgate(EMXX_CLK_CFI | EMXX_CLK_CFI_H);
emxx_unreset_device(EMXX_RST_CFI);
/* config the CFI work in the PIO mode, hardware reset, 16 bit data */
writel(CFI_CONTROL_0_IDE, EMXX_CFI_CONTROL_0);
/* hardware reset release in CFI module */
val = readl(EMXX_CFI_CONTROL_0) | CFI_CONTROL_0_HRST;
writel(val, EMXX_CFI_CONTROL_0);
/* disable all the interrupts */
writel(0x00000000, EMXX_CFI_CONTROL_1);
/* clear all the interrupt */
writel(0xffffffff, EMXX_CFI_INTERRUPT);
/* PIO mode access timing confige */
writel(0x00001319, EMXX_CFI_TIMING_1);
/* setting for PIO */
val = readl(EMXX_CFI_BUSIF_CTRL) & 0xFFFFFF00;
writel(val | 0x00000062 | emxx_cfi_burst_mode, EMXX_CFI_BUSIF_CTRL);
}
/*
* Setup the local clock events for a CPU.
*/
void __cpuinit local_timer_setup(void)
{
unsigned int cpu = smp_processor_id();
struct clock_event_device *clk;
unsigned long flags;
void __iomem *int_reg;
u32 val, int_shift, irq;
if (cpu == 1) {
clk = &timer1_clockevent;
irq = tm_reg[TIMER_SYSTEM2].irq;
clk->cpumask = &cpumask_of_cpu(cpu);
clk->irq = irq;
clk->mult = div_sc(TIMER_CLOCK_TICK_RATE_PLL3,
NSEC_PER_SEC, clk->shift);
clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
clk->min_delta_ns = clockevent_delta2ns(0x7f, clk);
emxx_open_clockgate(tm_reg[TIMER_SYSTEM2].clkdev);
emxx_unreset_device(tm_reg[TIMER_SYSTEM2].rstdev);
local_irq_save(flags);
setup_irq(irq, &emxx_system_timer1_irq);
irq_desc[irq].cpu = cpu;
/* Setting interrupt */
int_reg = __io_address(EMXX_INTA_DIST_BASE) +
GIC_DIST_TARGET + (INT_TIMER1 & ~3);
int_shift = (irq % 4) * 8;
val = readl(int_reg) & ~(0xff << int_shift);
val |= 1 << (cpu + int_shift);
writel(val, int_reg);
local_irq_restore(flags);
clockevents_register_device(clk);
}
}
void timer_set_clock(unsigned int mode)
{
int i;
unsigned int count;
unsigned int tm_delay;
struct timer_reg_t *reg;
static unsigned int timer_pmu_flag;
/* delay value set */
tm_delay = TIMER_DELAY(TIMER_CLOCK_TICK_RATE_32K);
switch (mode) {
case TIMER_SUSPEND:
/* close clockgate */
emxx_close_clockgate(tm_reg[TIMER_SYSTEM].clkdev);
emxx_close_clockgate(tm_reg[TIMER_WDT].clkdev);
emxx_close_clockgate(tm_reg[TIMER_DSP].clkdev);
timer_pmu_flag = emxx_get_clockgate(tm_reg[TIMER_PMU].clkdev);
if (timer_pmu_flag)
emxx_close_clockgate(tm_reg[TIMER_PMU].clkdev);
for (i = 0; i < TIMER_TG_MAX_NUM; i++) {
if (tg_tm_op[i] == 1)
emxx_close_clockgate(
tm_reg[TIMER_TG0 + i].clkdev);
}
break;
case TIMER_RESUME:
emxx_open_clockgate(tm_reg[TIMER_SYSTEM].clkdev);
emxx_open_clockgate(tm_reg[TIMER_WDT].clkdev);
emxx_open_clockgate(tm_reg[TIMER_DSP].clkdev);
if (timer_pmu_flag)
emxx_open_clockgate(tm_reg[TIMER_PMU].clkdev);
for (i = 0; i < TIMER_TG_MAX_NUM; i++) {
if (tg_tm_op[i] == 1)
emxx_open_clockgate(
tm_reg[TIMER_TG0 + i].clkdev);
}
break;
case TIMER_INIT:
emxx_open_clockgate(EMXX_CLK_TIM_P);
emxx_open_clockgate(tm_reg[TIMER_SYSTEM].clkdev);
emxx_open_clockgate(tm_reg[TIMER_DSP].clkdev);
emxx_open_clockgate(tm_reg[TIMER_PMU].clkdev);
emxx_unreset_device(tm_reg[TIMER_SYSTEM].rstdev);
emxx_unreset_device(tm_reg[TIMER_DSP].rstdev);
emxx_unreset_device(tm_reg[TIMER_PMU].rstdev);
for (i = 0; i < TIMER_TG_MAX_NUM; i++)
emxx_unreset_device(tm_reg[TIMER_TG0 + i].rstdev);
reg = tm_reg[TIMER_SYSTEM].reg;
reg->tm_op = TSTOP;
reg->tm_clr = TCR_CLR;
reg = tm_reg[TIMER_WDT].reg;
reg->tm_op = TSTOP;
reg->tm_clr = TCR_CLR;
reg = tm_reg[TIMER_DSP].reg;
reg->tm_op = TSTOP;
reg->tm_clr = TCR_CLR;
reg->tm_set = TIMER_INTERVAL_DSP;
reg = tm_reg[TIMER_PMU].reg;
reg->tm_op = TSTOP;
reg->tm_clr = TCR_CLR;
emxx_close_clockgate(tm_reg[TIMER_PMU].clkdev);
/* select TIN clock */
writel(TINTIN_SEL_PLL3 | TWNTIN_SEL_32K, SMU_TWI0TIN_SEL);
writel(TINTIN_SEL_PLL3 | TWNTIN_SEL_PLL3, SMU_TWI1TIN_SEL);
writel(TINTIN_SEL_32K | TWNTIN_SEL_PLL3, SMU_TWI2TIN_SEL);
writel(TINTIN_SEL_32K | TWNTIN_SEL_PLL3, SMU_TWI3TIN_SEL);
writel(TINTIN_SEL_32K, SMU_TW4TIN_SEL);
writel(TGNTIN_SEL_PLL3, SMU_TGNTIN_SEL);
/* DIVTIMTIN Register set */
writel(SMU_PLLSEL_PLL3 | SMU_DIV(40), SMU_TIMCLKDIV);
for (i = 0; i < TIMER_TG_MAX_NUM; i++) {
count = get_count_value(i,
tm_param[TIMER_TG0 + i].usecs);
reg = tm_reg[TIMER_TG0 + i].reg;
reg->tm_set = count;
}
break;
default:
printk(KERN_INFO "%s(): set clock error mode = %d.\n",
__func__, mode);
break;
}
}
static inline void pwm_dev_unreset(void)
{
emxx_unreset_device(EMXX_RST_PWM);
}
