int board_eth_init(bd_t *bis)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct eth_device *dev;
int ret;
ret = cpu_eth_init(bis);
/* MX28EVK uses ENET_CLK PAD to drive FEC clock */
writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
&clkctrl_regs->hw_clkctrl_enet);
/* Power-on FECs */
gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
/* Reset FEC PHYs */
gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
udelay(200);
gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
if (ret) {
puts("FEC MXS: Unable to init FEC0\n");
return ret;
}
ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
if (ret) {
puts("FEC MXS: Unable to init FEC1\n");
return ret;
}
dev = eth_get_dev_by_name("FEC0");
if (!dev) {
puts("FEC MXS: Unable to get FEC0 device entry\n");
return -EINVAL;
}
ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
if (ret) {
puts("FEC MXS: Unable to register FEC0 mii postcall\n");
return ret;
}
dev = eth_get_dev_by_name("FEC1");
if (!dev) {
puts("FEC MXS: Unable to get FEC1 device entry\n");
return -EINVAL;
}
ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
if (ret) {
puts("FEC MXS: Unable to register FEC1 mii postcall\n");
return ret;
}
return ret;
}
int board_eth_init(bd_t *bis)
{
struct eth_device *dev;
int ret;
ret = cpu_eth_init(bis);
if (ret) {
printf("FEC MXC: %s:failed\n", __func__);
return ret;
}
dev = eth_get_dev_by_name("FEC");
if (!dev) {
printf("FEC MXC: Unable to get FEC device entry\n");
return -EINVAL;
}
ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
if (ret) {
printf("FEC MXC: Unable to register FEC mii postcall\n");
return ret;
}
return 0;
}
at91_emac_t *get_emacbase_by_name(char *devname)
{
struct eth_device *netdev;
netdev = eth_get_dev_by_name(devname);
return (at91_emac_t *) netdev->iobase;
}
int board_eth_init(bd_t *bis)
{
int ret;
struct eth_device *dev;
ret = cpu_eth_init(bis);
if (ret) {
printf("FEC MXS: Unable to init FEC clocks\n");
return ret;
}
ret = fecmxc_initialize(bis);
if (ret) {
printf("FEC MXS: Unable to init FEC\n");
return ret;
}
dev = eth_get_dev_by_name("FEC");
if (!dev) {
printf("FEC MXS: Unable to get FEC device entry\n");
return -EINVAL;
}
ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
if (ret) {
printf("FEC MXS: Unable to register FEC MII postcall\n");
return ret;
}
return ret;
}
int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
u16 value)
{
#ifdef CONFIG_DM_ETH
struct udevice *dev = eth_get_dev_by_name(bus->name);
struct macb_device *macb = dev_get_priv(dev);
#else
struct eth_device *dev = eth_get_dev_by_name(bus->name);
struct macb_device *macb = to_macb(dev);
#endif
if (macb->phy_addr != phy_adr)
return -1;
arch_get_mdio_control(bus->name);
macb_mdio_write(macb, reg, value);
return 0;
}
int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
{
u16 value = 0;
#ifdef CONFIG_DM_ETH
struct udevice *dev = eth_get_dev_by_name(bus->name);
struct macb_device *macb = dev_get_priv(dev);
#else
struct eth_device *dev = eth_get_dev_by_name(bus->name);
struct macb_device *macb = to_macb(dev);
#endif
if (macb->phy_addr != phy_adr)
return -1;
arch_get_mdio_control(bus->name);
value = macb_mdio_read(macb, reg);
return value;
}
int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
struct macb_device *macb = to_macb(dev);
if ( macb->phy_addr != phy_adr )
return -1;
macb_mdio_write(macb, reg, value);
return 0;
}
int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
struct macb_device *macb = to_macb(dev);
if ( macb->phy_addr != phy_adr )
return -1;
arch_get_mdio_control(devname);
*value = macb_mdio_read(macb, reg);
return 0;
}
int eth_initialize(void)
{
int num_devices = 0;
struct udevice *dev;
eth_common_init();
/*
* Devices need to write the hwaddr even if not started so that Linux
* will have access to the hwaddr that u-boot stored for the device.
* This is accomplished by attempting to probe each device and calling
* their write_hwaddr() operation.
*/
uclass_first_device(UCLASS_ETH, &dev);
if (!dev) {
printf("No ethernet found.\n");
bootstage_error(BOOTSTAGE_ID_NET_ETH_START);
} else {
char *ethprime = getenv("ethprime");
struct udevice *prime_dev = NULL;
if (ethprime)
prime_dev = eth_get_dev_by_name(ethprime);
if (prime_dev) {
eth_set_dev(prime_dev);
eth_current_changed();
} else {
eth_set_dev(NULL);
}
bootstage_mark(BOOTSTAGE_ID_NET_ETH_INIT);
do {
if (num_devices)
printf(", ");
printf("eth%d: %s", dev->seq, dev->name);
if (ethprime && dev == prime_dev)
printf(" [PRIME]");
eth_write_hwaddr(dev);
uclass_next_device(&dev);
num_devices++;
} while (dev);
putc('\n');
}
return num_devices;
}
void ft_fixup_enet_phy_connect_type(void *fdt)
{
struct eth_device *dev;
struct tsec_private *priv;
const char *enet_path, *phy_path;
char enet[16];
char phy[16];
int phy_node;
int i = 0;
uint32_t ph;
char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
for (; i < ARRAY_SIZE(name); i++) {
dev = eth_get_dev_by_name(name[i]);
if (dev) {
sprintf(enet, "ethernet%d", i);
sprintf(phy, "enet%d_rgmii_phy", i);
} else {
continue;
}
priv = dev->priv;
if (priv->flags & TSEC_SGMII)
continue;
enet_path = fdt_get_alias(fdt, enet);
if (!enet_path)
continue;
phy_path = fdt_get_alias(fdt, phy);
if (!phy_path)
continue;
phy_node = fdt_path_offset(fdt, phy_path);
if (phy_node < 0)
continue;
ph = fdt_create_phandle(fdt, phy_node);
if (ph)
do_fixup_by_path_u32(fdt, enet_path,
"phy-handle", ph, 1);
do_fixup_by_path(fdt, enet_path, "phy-connection-type",
phy_string_for_interface(
PHY_INTERFACE_MODE_RGMII_ID),
sizeof(phy_string_for_interface(
PHY_INTERFACE_MODE_RGMII_ID)),
1);
}
}
static int ftmac110_mdio_write(
const char *devname, uint8_t addr, uint8_t reg, uint16_t value)
{
int ret = 0;
struct eth_device *dev;
dev = eth_get_dev_by_name(devname);
if (dev == NULL) {
printf("%s: no such device\n", devname);
ret = -1;
} else {
mdio_write(dev, addr, reg, value);
}
return ret;
}
/*
* smi_reg_write - imiiphy_write callback function.
*
* Returns 0 if write succeed, -EINVAL on bad parameters
* -ETIME on timeout
*/
static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
u32 smi_reg;
u32 timeout;
/* Phyadr write request*/
if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
KWGBEREG_WR(regs->phyadr, data);
return 0;
}
/* check parameters */
if (phy_adr > PHYADR_MASK) {
printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
return -EINVAL;
}
if (reg_ofs > PHYREG_MASK) {
printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
return -EINVAL;
}
/* wait till the SMI is not busy */
timeout = KWGBE_PHY_SMI_TIMEOUT;
do {
/* read smi register */
smi_reg = KWGBEREG_RD(regs->smi);
if (timeout-- == 0) {
printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
return -ETIME;
}
} while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
/* fill the phy addr and reg offset and write opcode and data */
smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
| (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
/* write the smi register */
KWGBEREG_WR(regs->smi, smi_reg);
return 0;
}
/*
* MII-interface related functions
*/
static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr,
uint16_t *retVal)
{
struct eth_device *edev = eth_get_dev_by_name(dev);
struct fec_priv *fec = (struct fec_priv *)edev->priv;
struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
uint32_t reg; /* convenient holder for the PHY register */
uint32_t phy; /* convenient holder for the PHY */
uint32_t start;
/*
* reading from any PHY's register is done by properly
* programming the FEC's MII data register.
*/
writel(FEC_IEVENT_MII, ð->ievent);
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
phy | reg, ð->mii_data);
/*
* wait for the related interrupt
*/
start = get_timer(0);
while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
printf("Read MDIO failed...\n");
return -1;
}
}
/*
* clear mii interrupt bit
*/
writel(FEC_IEVENT_MII, ð->ievent);
/*
* it's now safe to read the PHY's register
*/
*retVal = readl(ð->mii_data);
debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
regAddr, *retVal);
return 0;
}
static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
uint16_t data)
{
struct eth_device *edev = eth_get_dev_by_name(dev);
struct fec_priv *fec = (struct fec_priv *)edev->priv;
struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
uint32_t reg; /* convenient holder for the PHY register */
uint32_t phy; /* convenient holder for the PHY */
uint32_t start;
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
/*
* wait for the MII interrupt
*/
start = get_timer(0);
while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
printf("Write MDIO failed...\n");
return -1;
}
}
/*
* clear MII interrupt bit
*/
writel(FEC_IEVENT_MII, ð->ievent);
debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
regAddr, data);
return 0;
}
static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type)
{
int i, err = 0, ret = 0;
char ethname[ETH_NAME_LEN];
struct eth_device *eth_dev;
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
/* port not enabled */
if (wriop_is_enabled_dpmac(i) != 1)
continue;
snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s", i,
phy_interface_strings[wriop_get_enet_if(i)]);
eth_dev = eth_get_dev_by_name(ethname);
if (eth_dev == NULL)
continue;
switch (type) {
case MC_FIXUP_DPL:
err = mc_fixup_dpl_mac_addr(blob, i, eth_dev);
break;
case MC_FIXUP_DPC:
err = mc_fixup_dpc_mac_addr(blob, i, eth_dev);
break;
default:
break;
}
if (err)
printf("fsl-mc: ERROR fixing mac address for %s\n",
ethname);
ret |= err;
}
return ret;
}
/*
* smi_reg_read - miiphy_read callback function.
*
* Returns 16bit phy register value, or 0xffff on error
*/
static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
u32 smi_reg;
u32 timeout;
/* Phyadr read request */
if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
/* */
*data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
return 0;
}
/* check parameters */
if (phy_adr > PHYADR_MASK) {
printf("Err..(%s) Invalid PHY address %d\n",
__FUNCTION__, phy_adr);
return -EFAULT;
}
if (reg_ofs > PHYREG_MASK) {
printf("Err..(%s) Invalid register offset %d\n",
__FUNCTION__, reg_ofs);
return -EFAULT;
}
timeout = KWGBE_PHY_SMI_TIMEOUT;
/* wait till the SMI is not busy */
do {
/* read smi register */
smi_reg = KWGBEREG_RD(regs->smi);
if (timeout-- == 0) {
printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
return -EFAULT;
}
} while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
/* fill the phy address and regiser offset and read opcode */
smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
| (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
| KWGBE_PHY_SMI_OPCODE_READ;
/* write the smi register */
KWGBEREG_WR(regs->smi, smi_reg);
/*wait till read value is ready */
timeout = KWGBE_PHY_SMI_TIMEOUT;
do {
/* read smi register */
smi_reg = KWGBEREG_RD(regs->smi);
if (timeout-- == 0) {
printf("Err..(%s) SMI read ready timeout\n",
__FUNCTION__);
return -EFAULT;
}
} while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
/* Wait for the data to update in the SMI register */
for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
*data = (u16) (KWGBEREG_RD(regs->smi) & KWGBE_PHY_SMI_DATA_MASK);
debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
reg_ofs, *data);
return 0;
}
int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
struct eth_device *dev;
char cs8900_name[10];
if (strcmp(argv[1], "info") == 0)
{
print_vcma9_info();
return 0;
}
#if defined(CONFIG_CS8900)
if (strcmp(argv[1], "cs8900") == 0) {
sprintf(cs8900_name, "%s-0", CS8900_DRIVERNAME);
dev = eth_get_dev_by_name(cs8900_name);
if (!dev) {
printf("Couldn't find CS8900 driver");
return 0;
}
if (strcmp(argv[2], "read") == 0) {
uchar addr; ushort data;
addr = simple_strtoul(argv[3], NULL, 16);
cs8900_e2prom_read(dev, addr, &data);
printf("0x%2.2X: 0x%4.4X\n", addr, data);
} else if (strcmp(argv[2], "write") == 0) {
uchar addr; ushort data;
addr = simple_strtoul(argv[3], NULL, 16);
data = simple_strtoul(argv[4], NULL, 16);
cs8900_e2prom_write(dev, addr, data);
} else if (strcmp(argv[2], "setaddr") == 0) {
uchar addr, i, csum; ushort data;
uchar ethaddr[6];
/* check for valid ethaddr */
if (eth_getenv_enetaddr("ethaddr", ethaddr)) {
addr = 1;
data = 0x2158;
cs8900_e2prom_write(dev, addr, data);
csum = cs8900_chksum(data);
addr++;
for (i = 0; i < 6; i+=2) {
data = ethaddr[i+1] << 8 |
ethaddr[i];
cs8900_e2prom_write(dev, addr, data);
csum += cs8900_chksum(data);
addr++;
}
/* calculate header link byte */
data = 0xA100 | (addr * 2);
cs8900_e2prom_write(dev, 0, data);
csum += cs8900_chksum(data);
/* write checksum word */
cs8900_e2prom_write(dev, addr, (0 - csum) << 8);
} else {
puts("\nplease defined 'ethaddr'\n");
}
} else if (strcmp(argv[2], "dump") == 0) {
uchar addr = 0, endaddr, csum; ushort data;
puts("Dump of CS8900 config device: ");
cs8900_e2prom_read(dev, addr, &data);
if ((data & 0xE000) == 0xA000) {
endaddr = (data & 0x00FF) / 2;
csum = cs8900_chksum(data);
for (addr = 1; addr <= endaddr; addr++) {
cs8900_e2prom_read(dev, addr, &data);
printf("\n0x%2.2X: 0x%4.4X", addr, data);
csum += cs8900_chksum(data);
}
printf("\nChecksum: %s", (csum == 0) ? "ok" : "wrong");
} else {
puts("no valid config found");
}
puts("\n");
}
return 0;
}
#endif
#if 0
if (strcmp(argv[1], "cantest") == 0) {
if (argc >= 3)
vcma9_cantest(strcmp(argv[2], "s") ? 0 : 1);
else
vcma9_cantest(0);
return 0;
}
if (strcmp(argv[1], "nandtest") == 0) {
vcma9_nandtest();
return 0;
}
if (strcmp(argv[1], "nanderase") == 0) {
vcma9_nanderase();
return 0;
}
if (strcmp(argv[1], "nandread") == 0) {
ulong offset = 0;
if (argc >= 3)
offset = simple_strtoul(argv[2], NULL, 16);
vcma9_nandread(offset);
return 0;
}
if (strcmp(argv[1], "nandwrite") == 0) {
ulong offset = 0;
if (argc >= 3)
offset = simple_strtoul(argv[2], NULL, 16);
vcma9_nandwrite(offset);
return 0;
}
if (strcmp(argv[1], "dactest") == 0) {
if (argc >= 3)
vcma9_dactest(strcmp(argv[2], "s") ? 0 : 1);
else
vcma9_dactest(0);
return 0;
}
#endif
return (do_mplcommon(cmdtp, flag, argc, argv));
}
int eth_init(void)
{
char *ethact = getenv("ethact");
char *ethrotate = getenv("ethrotate");
struct udevice *current = NULL;
struct udevice *old_current;
int ret = -ENODEV;
/*
* When 'ethrotate' variable is set to 'no' and 'ethact' variable
* is already set to an ethernet device, we should stick to 'ethact'.
*/
if ((ethrotate != NULL) && (strcmp(ethrotate, "no") == 0)) {
if (ethact) {
current = eth_get_dev_by_name(ethact);
if (!current)
return -EINVAL;
}
}
if (!current) {
current = eth_get_dev();
if (!current) {
printf("No ethernet found.\n");
return -ENODEV;
}
}
old_current = current;
do {
if (current) {
debug("Trying %s\n", current->name);
if (device_active(current)) {
ret = eth_get_ops(current)->start(current);
if (ret >= 0) {
struct eth_device_priv *priv =
current->uclass_priv;
priv->state = ETH_STATE_ACTIVE;
return 0;
}
} else {
ret = eth_errno;
}
debug("FAIL\n");
} else {
debug("PROBE FAIL\n");
}
/*
* If ethrotate is enabled, this will change "current",
* otherwise we will drop out of this while loop immediately
*/
eth_try_another(0);
/* This will ensure the new "current" attempted to probe */
current = eth_get_dev();
} while (old_current != current);
return ret;
}
int board_eth_init(bd_t *bis)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct eth_device *dev;
int ret;
ret = cpu_eth_init(bis);
if (ret)
return ret;
clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
CLKCTRL_ENET_TIME_SEL_RMII_CLK);
#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
/* Reset the new PHY */
gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0);
udelay(10000);
gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1);
udelay(10000);
#endif
ret = fecmxc_initialize_multi(bis, 0, 1 << 0, MXS_ENET0_BASE);
if (ret) {
printf("FEC MXS: Unable to init FEC0\n");
return ret;
}
ret = fecmxc_initialize_multi(bis, 1, 1 << 3, MXS_ENET1_BASE);
if (ret) {
printf("FEC MXS: Unable to init FEC1\n");
return ret;
}
dev = eth_get_dev_by_name("FEC0");
if (!dev) {
printf("FEC MXS: Unable to get FEC0 device entry\n");
return -EINVAL;
}
ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
if (ret) {
printf("FEC MXS: Unable to register FEC0 mii postcall\n");
return ret;
}
dev = eth_get_dev_by_name("FEC1");
if (!dev) {
printf("FEC MXS: Unable to get FEC1 device entry\n");
return -EINVAL;
}
ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
if (ret) {
printf("FEC MXS: Unable to register FEC1 mii postcall\n");
return ret;
}
return ret;
}
