/* Is rs alignment needed? */
static bool is_rs_align(struct etna_screen *screen,
const struct pipe_resource *tmpl)
{
return screen->specs.use_blt ? false : (
VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) ||
!etna_resource_sampler_only(tmpl));
}
static struct pipe_resource *
etna_resource_create(struct pipe_screen *pscreen,
const struct pipe_resource *templat)
{
struct etna_screen *screen = etna_screen(pscreen);
/* Figure out what tiling to use -- for now, assume that texture cannot be linear.
* there is a capability LINEAR_TEXTURE_SUPPORT (supported on gc880 and
* gc2000 at least), but not sure how it works.
* Buffers always have LINEAR layout.
*/
unsigned layout = ETNA_LAYOUT_LINEAR;
if (etna_resource_sampler_only(templat)) {
/* The buffer is only used for texturing, so create something
* directly compatible with the sampler. Such a buffer can
* never be rendered to. */
layout = ETNA_LAYOUT_TILED;
if (util_format_is_compressed(templat->format))
layout = ETNA_LAYOUT_LINEAR;
} else if (templat->target != PIPE_BUFFER) {
bool want_multitiled = false;
bool want_supertiled = screen->specs.can_supertile;
/* When this GPU supports single-buffer rendering, don't ever enable
* multi-tiling. This replicates the blob behavior on GC3000.
*/
if (!screen->specs.single_buffer)
want_multitiled = screen->specs.pixel_pipes > 1;
/* Keep single byte blocksized resources as tiled, since we
* are unable to use the RS blit to de-tile them. However,
* if they're used as a render target or depth/stencil, they
* must be multi-tiled for GPUs with multiple pixel pipes.
* Ignore depth/stencil here, but it is an error for a render
* target.
*/
if (util_format_get_blocksize(templat->format) == 1 &&
!(templat->bind & PIPE_BIND_DEPTH_STENCIL)) {
assert(!(templat->bind & PIPE_BIND_RENDER_TARGET && want_multitiled));
want_multitiled = want_supertiled = false;
}
layout = ETNA_LAYOUT_BIT_TILE;
if (want_multitiled)
layout |= ETNA_LAYOUT_BIT_MULTI;
if (want_supertiled)
layout |= ETNA_LAYOUT_BIT_SUPER;
}
if (templat->target == PIPE_TEXTURE_3D)
layout = ETNA_LAYOUT_LINEAR;
/* modifier is only used for scanout surfaces, so safe to use LINEAR here */
return etna_resource_alloc(pscreen, layout, DRM_FORMAT_MOD_LINEAR, templat);
}
static struct pipe_resource *
etna_resource_create(struct pipe_screen *pscreen,
const struct pipe_resource *templat)
{
struct etna_screen *screen = etna_screen(pscreen);
/* Figure out what tiling to use -- for now, assume that textures cannot be
* supertiled, and cannot be linear.
* There is a feature flag SUPERTILED_TEXTURE (not supported on any known hw)
* that may allow this, as well
* as LINEAR_TEXTURE_SUPPORT (supported on gc880 and gc2000 at least), but
* not sure how it works.
* Buffers always have LINEAR layout.
*/
unsigned layout = ETNA_LAYOUT_LINEAR;
if (etna_resource_sampler_only(templat)) {
/* The buffer is only used for texturing, so create something
* directly compatible with the sampler. Such a buffer can
* never be rendered to. */
layout = ETNA_LAYOUT_TILED;
if (util_format_is_compressed(templat->format))
layout = ETNA_LAYOUT_LINEAR;
} else if (templat->target != PIPE_BUFFER) {
bool want_multitiled = screen->specs.pixel_pipes > 1;
bool want_supertiled = screen->specs.can_supertile && !DBG_ENABLED(ETNA_DBG_NO_SUPERTILE);
/* Keep single byte blocksized resources as tiled, since we
* are unable to use the RS blit to de-tile them. However,
* if they're used as a render target or depth/stencil, they
* must be multi-tiled for GPUs with multiple pixel pipes.
* Ignore depth/stencil here, but it is an error for a render
* target.
*/
if (util_format_get_blocksize(templat->format) == 1 &&
!(templat->bind & PIPE_BIND_DEPTH_STENCIL)) {
assert(!(templat->bind & PIPE_BIND_RENDER_TARGET && want_multitiled));
want_multitiled = want_supertiled = false;
}
layout = ETNA_LAYOUT_BIT_TILE;
if (want_multitiled)
layout |= ETNA_LAYOUT_BIT_MULTI;
if (want_supertiled)
layout |= ETNA_LAYOUT_BIT_SUPER;
}
if (templat->target == PIPE_TEXTURE_3D)
layout = ETNA_LAYOUT_LINEAR;
return etna_resource_alloc(pscreen, layout, templat);
}
/* Create a new resource object, using the given template info */
struct pipe_resource *
etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout,
uint64_t modifier, const struct pipe_resource *templat)
{
struct etna_screen *screen = etna_screen(pscreen);
struct etna_resource *rsc;
unsigned size;
DBG_F(ETNA_DBG_RESOURCE_MSGS,
"target=%d, format=%s, %ux%ux%u, array_size=%u, "
"last_level=%u, nr_samples=%u, usage=%u, bind=%x, flags=%x",
templat->target, util_format_name(templat->format), templat->width0,
templat->height0, templat->depth0, templat->array_size,
templat->last_level, templat->nr_samples, templat->usage,
templat->bind, templat->flags);
/* Determine scaling for antialiasing, allow override using debug flag */
int nr_samples = templat->nr_samples;
if ((templat->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) &&
!(templat->bind & PIPE_BIND_SAMPLER_VIEW)) {
if (DBG_ENABLED(ETNA_DBG_MSAA_2X))
nr_samples = 2;
if (DBG_ENABLED(ETNA_DBG_MSAA_4X))
nr_samples = 4;
}
int msaa_xscale = 1, msaa_yscale = 1;
if (!translate_samples_to_xyscale(nr_samples, &msaa_xscale, &msaa_yscale, NULL)) {
/* Number of samples not supported */
return NULL;
}
/* Determine needed padding (alignment of height/width) */
unsigned paddingX = 0, paddingY = 0;
unsigned halign = TEXTURE_HALIGN_FOUR;
if (!util_format_is_compressed(templat->format)) {
/* If we have the TEXTURE_HALIGN feature, we can always align to the
* resolve engine's width. If not, we must not align resources used
* only for textures. If this GPU uses the BLT engine, never do RS align.
*/
bool rs_align = screen->specs.use_blt ? false : (
VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) ||
!etna_resource_sampler_only(templat));
etna_layout_multiple(layout, screen->specs.pixel_pipes, rs_align, &paddingX,
&paddingY, &halign);
assert(paddingX && paddingY);
} else {
/* Compressed textures are padded to their block size, but we don't have
* to do anything special for that. */
paddingX = 1;
paddingY = 1;
}
if (!screen->specs.use_blt && templat->target != PIPE_BUFFER)
etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, &paddingY);
if (templat->bind & PIPE_BIND_SCANOUT) {
struct pipe_resource scanout_templat = *templat;
struct renderonly_scanout *scanout;
struct winsys_handle handle;
/* pad scanout buffer size to be compatible with the RS */
if (!screen->specs.use_blt && modifier == DRM_FORMAT_MOD_LINEAR)
etna_adjust_rs_align(screen->specs.pixel_pipes, &paddingX, &paddingY);
scanout_templat.width0 = align(scanout_templat.width0, paddingX);
scanout_templat.height0 = align(scanout_templat.height0, paddingY);
scanout = renderonly_scanout_for_resource(&scanout_templat,
screen->ro, &handle);
if (!scanout)
return NULL;
assert(handle.type == WINSYS_HANDLE_TYPE_FD);
handle.modifier = modifier;
rsc = etna_resource(pscreen->resource_from_handle(pscreen, templat,
&handle,
PIPE_HANDLE_USAGE_WRITE));
close(handle.handle);
if (!rsc)
return NULL;
rsc->scanout = scanout;
return &rsc->base;
}
rsc = CALLOC_STRUCT(etna_resource);
if (!rsc)
return NULL;
rsc->base = *templat;
rsc->base.screen = pscreen;
rsc->base.nr_samples = nr_samples;
rsc->layout = layout;
rsc->halign = halign;
pipe_reference_init(&rsc->base.reference, 1);
list_inithead(&rsc->list);
size = setup_miptree(rsc, paddingX, paddingY, msaa_xscale, msaa_yscale);
uint32_t flags = DRM_ETNA_GEM_CACHE_WC;
if (templat->bind & PIPE_BIND_VERTEX_BUFFER)
flags |= DRM_ETNA_GEM_FORCE_MMU;
struct etna_bo *bo = etna_bo_new(screen->dev, size, flags);
if (unlikely(bo == NULL)) {
BUG("Problem allocating video memory for resource");
goto free_rsc;
}
rsc->bo = bo;
rsc->ts_bo = 0; /* TS is only created when first bound to surface */
if (DBG_ENABLED(ETNA_DBG_ZERO)) {
void *map = etna_bo_map(bo);
memset(map, 0, size);
}
return &rsc->base;
free_rsc:
FREE(rsc);
return NULL;
}
/* Create a new resource object, using the given template info */
struct pipe_resource *
etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout,
const struct pipe_resource *templat)
{
struct etna_screen *screen = etna_screen(pscreen);
unsigned size;
DBG_F(ETNA_DBG_RESOURCE_MSGS,
"target=%d, format=%s, %ux%ux%u, array_size=%u, "
"last_level=%u, nr_samples=%u, usage=%u, bind=%x, flags=%x",
templat->target, util_format_name(templat->format), templat->width0,
templat->height0, templat->depth0, templat->array_size,
templat->last_level, templat->nr_samples, templat->usage,
templat->bind, templat->flags);
/* Determine scaling for antialiasing, allow override using debug flag */
int nr_samples = templat->nr_samples;
if ((templat->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) &&
!(templat->bind & PIPE_BIND_SAMPLER_VIEW)) {
if (DBG_ENABLED(ETNA_DBG_MSAA_2X))
nr_samples = 2;
if (DBG_ENABLED(ETNA_DBG_MSAA_4X))
nr_samples = 4;
}
int msaa_xscale = 1, msaa_yscale = 1;
if (!translate_samples_to_xyscale(nr_samples, &msaa_xscale, &msaa_yscale, NULL)) {
/* Number of samples not supported */
return NULL;
}
/* If we have the TEXTURE_HALIGN feature, we can always align to the
* resolve engine's width. If not, we must not align resources used
* only for textures. */
bool rs_align = VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) ||
!etna_resource_sampler_only(templat);
/* Determine needed padding (alignment of height/width) */
unsigned paddingX = 0, paddingY = 0;
unsigned halign = TEXTURE_HALIGN_FOUR;
etna_layout_multiple(layout, screen->specs.pixel_pipes, rs_align, &paddingX,
&paddingY, &halign);
assert(paddingX && paddingY);
if (templat->bind != PIPE_BUFFER) {
unsigned min_paddingY = 4 * screen->specs.pixel_pipes;
if (paddingY < min_paddingY)
paddingY = min_paddingY;
}
struct etna_resource *rsc = CALLOC_STRUCT(etna_resource);
if (!rsc)
return NULL;
rsc->base = *templat;
rsc->base.screen = pscreen;
rsc->base.nr_samples = nr_samples;
rsc->layout = layout;
rsc->halign = halign;
pipe_reference_init(&rsc->base.reference, 1);
list_inithead(&rsc->list);
size = setup_miptree(rsc, paddingX, paddingY, msaa_xscale, msaa_yscale);
uint32_t flags = DRM_ETNA_GEM_CACHE_WC;
if (templat->bind & PIPE_BIND_VERTEX_BUFFER)
flags |= DRM_ETNA_GEM_FORCE_MMU;
struct etna_bo *bo = etna_bo_new(screen->dev, size, flags);
if (unlikely(bo == NULL)) {
BUG("Problem allocating video memory for resource");
return NULL;
}
rsc->bo = bo;
rsc->ts_bo = 0; /* TS is only created when first bound to surface */
if (templat->bind & PIPE_BIND_SCANOUT)
rsc->scanout = renderonly_scanout_for_resource(&rsc->base, screen->ro);
if (DBG_ENABLED(ETNA_DBG_ZERO)) {
void *map = etna_bo_map(bo);
memset(map, 0, size);
}
return &rsc->base;
}