int do_flash_write(uint32_t addr, uint32_t len, uint32_t erase) {
struct uart_buf ub;
uint8_t digest[16];
uint32_t num_written = 0, num_erased = 0;
struct MD5Context ctx;
MD5Init(&ctx);
if (addr % FLASH_SECTOR_SIZE != 0) return 0x32;
if (len % FLASH_SECTOR_SIZE != 0) return 0x33;
if (SPIUnlock() != 0) return 0x34;
ub.nr = 0;
ub.pr = ub.pw = ub.data;
ets_isr_attach(ETS_UART_INUM, uart_isr, &ub);
SET_PERI_REG_MASK(UART_INT_ENA(0), UART_RX_INTS);
ets_isr_unmask(1 << ETS_UART_INUM);
SLIP_send(&num_written, 4);
while (num_written < len) {
volatile uint32_t *nr = &ub.nr;
/* Prepare the space ahead. */
while (erase && num_erased < num_written + SPI_WRITE_SIZE) {
const uint32_t num_left = (len - num_erased);
if (num_left > FLASH_BLOCK_SIZE && addr % FLASH_BLOCK_SIZE == 0) {
if (SPIEraseBlock(addr / FLASH_BLOCK_SIZE) != 0) return 0x35;
num_erased += FLASH_BLOCK_SIZE;
} else {
/* len % FLASH_SECTOR_SIZE == 0 is enforced, no further checks needed */
if (SPIEraseSector(addr / FLASH_SECTOR_SIZE) != 0) return 0x36;
num_erased += FLASH_SECTOR_SIZE;
}
}
/* Wait for data to arrive. */
while (*nr < SPI_WRITE_SIZE) {
}
MD5Update(&ctx, ub.pr, SPI_WRITE_SIZE);
if (SPIWrite(addr, ub.pr, SPI_WRITE_SIZE) != 0) return 0x37;
ets_intr_lock();
*nr -= SPI_WRITE_SIZE;
ets_intr_unlock();
num_written += SPI_WRITE_SIZE;
addr += SPI_WRITE_SIZE;
ub.pr += SPI_WRITE_SIZE;
if (ub.pr >= ub.data + UART_BUF_SIZE) ub.pr = ub.data;
SLIP_send(&num_written, 4);
}
ets_isr_mask(1 << ETS_UART_INUM);
MD5Final(digest, &ctx);
SLIP_send(digest, 16);
return 0;
}
void ICACHE_FLASH_ATTR deinit_GPIOs_intr(void)
{
if(GPIO_INT_init_flg) {
ets_isr_mask(1 << ETS_GPIO_INUM); // запрет прерываний GPIOs
gpio_pin_intr_state_set(GPIO_TEST1, GPIO_PIN_INTR_DISABLE);
gpio_pin_intr_state_set(GPIO_TEST2, GPIO_PIN_INTR_DISABLE);
// ets_isr_attach(ETS_GPIO_INUM, NULL, NULL);
GPIO_INTR_INIT = 0;
GPIO_INT_init_flg = 0;
os_printf("GPIOs_intr deinit (%d,%d) ", GPIO_TEST1, GPIO_TEST2);
}
}
void ICACHE_FLASH_ATTR timer0_stop(void)
{
ets_isr_mask(BIT(ETS_FRC_TIMER0_INUM));
TIMER0_CTRL = 0;
INTC_EDGE_EN &= ~BIT(1);
}
