static void
mainbus_attach(device_t parent, device_t self, void *aux)
{
size_t i;
mainbus_found = true;
aprint_normal("\n");
#if defined(PCI_NETBSD_CONFIGURE)
{
struct extent *ioext, *memext;
ioext = extent_create("pciio", 0x00001000, 0x00003fff,
NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem", 0, BONITO_PCILO_SIZE,
NULL, 0, EX_NOWAIT);
pci_configure_bus(&gdium_configuration.gc_pc, ioext, memext,
NULL, 0, mips_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
}
#endif /* PCI_NETBSD_CONFIGURE */
for (i = 0; i < __arraycount(mainbusdevs); i++) {
struct mainbus_attach_args maa;
maa.maa_name = mainbusdevs[i];
(void) config_found(self, &maa, mainbus_print);
}
}
void
pci_addr_fixup(void *v, int maxbus)
{
struct shpcic_softc *sc = v;
const char *verbose_header =
"[%s]-----------------------\n"
" device vendor product\n"
" register space address size\n"
"--------------------------------------------\n";
const char *verbose_footer =
"--------------------------[%3d devices bogus]\n";
sc->extent_mem = extent_create("PCI I/O memory space",
sc->sc_membus_space.bus_base,
sc->sc_membus_space.bus_base + sc->sc_membus_space.bus_size,
M_DEVBUF, 0, 0, EX_NOWAIT);
KASSERT(sc->extent_mem);
sc->extent_port = extent_create("PCI I/O port space",
sc->sc_iobus_space.bus_base,
sc->sc_iobus_space.bus_base + sc->sc_iobus_space.bus_size,
M_DEVBUF, 0, 0, EX_NOWAIT);
KASSERT(sc->extent_port);
/*
* 1. check & reserve system BIOS setting.
*/
PCIBIOS_PRINTV((verbose_header, "System BIOS Setting"));
pci_device_foreach(sc, &sc->sc_pci_chipset, maxbus,
pciaddr_resource_reserve);
pci_device_foreach(sc, &sc->sc_pci_chipset, maxbus,
pciaddr_resource_reserve_disabled);
PCIBIOS_PRINTV((verbose_footer, sc->nbogus));
{
struct extent_region *rp;
struct extent *ex = sc->extent_mem;
for (rp = LIST_FIRST(&ex->ex_regions);
rp; rp = LIST_NEXT(rp, er_link)) {
}
}
{
struct extent_region *rp;
struct extent *ex = sc->extent_port;
for (rp = LIST_FIRST(&ex->ex_regions);
rp; rp = LIST_NEXT(rp, er_link)) {
}
}
/*
* 4. do fixup
*/
PCIBIOS_PRINTV((verbose_header, "PCIBIOS fixup stage"));
sc->nbogus = 0;
pci_device_foreach(sc, &sc->sc_pci_chipset, maxbus,
pciaddr_resource_allocate);
PCIBIOS_PRINTV((verbose_footer, sc->nbogus));
}
static void
mainbus_attach(device_t parent, device_t self, void *aux)
{
struct mainbus_attach_args ma;
const struct mainbusdev *md;
#if defined(PCI_NETBSD_ENABLE_IDE) || defined(PCI_NETBSD_CONFIGURE)
struct malta_config *mcp = &malta_configuration;
pci_chipset_tag_t pc = &mcp->mc_pc;
#endif
#if defined(PCI_NETBSD_ENABLE_IDE)
pcitag_t idetag;
pcireg_t idetim;
#endif
mainbus_found = true;
printf("\n");
#if defined(PCI_NETBSD_CONFIGURE)
struct mips_cache_info * const mci = &mips_cache_info;
struct extent *ioext = extent_create("pciio", 0x00001000, 0x0000efff,
NULL, 0, EX_NOWAIT);
struct extent *memext = extent_create("pcimem", MALTA_PCIMEM1_BASE,
MALTA_PCIMEM1_BASE + MALTA_PCIMEM1_SIZE,
NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, ioext, memext, NULL, 0, mci->mci_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
#endif /* PCI_NETBSD_CONFIGURE */
#if defined(PCI_NETBSD_ENABLE_IDE)
/*
* Perhaps PMON has not enabled the IDE controller. Easy to
* fix -- just set the ENABLE bits for each channel in the
* IDETIM register. Just clear all the bits for the channel
* except for the ENABLE bits -- the `pciide' driver will
* properly configure it later.
*/
idetim = 0;
if (PCI_NETBSD_ENABLE_IDE & 0x01)
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 0);
if (PCI_NETBSD_ENABLE_IDE & 0x02)
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1);
/* pciide0 is pci device 10, function 1 */
idetag = pci_make_tag(pc, 0, 10, 1);
pci_conf_write(pc, idetag, PIIX_IDETIM, idetim);
#endif
for (md = mainbusdevs; md->md_name != NULL; md++) {
ma.ma_name = md->md_name;
ma.ma_addr = md->md_addr;
ma.ma_intr = md->md_intr;
(void) config_found_sm_loc(self, "mainbus", NULL, &ma,
mainbus_print, mainbus_submatch);
}
}
void
i80321_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct i80321_softc *sc = cookie;
struct extent *ioext, *memext;
uint32_t busno;
#endif
pc->pc_conf_v = cookie;
pc->pc_attach_hook = i80321_pci_attach_hook;
pc->pc_bus_maxdevs = i80321_pci_bus_maxdevs;
pc->pc_make_tag = i80321_pci_make_tag;
pc->pc_decompose_tag = i80321_pci_decompose_tag;
pc->pc_conf_read = i80321_pci_conf_read;
pc->pc_conf_write = i80321_pci_conf_write;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
/*
* Configure the PCI bus.
*
* XXX We need to revisit this. We only configure the Secondary
* bus (and its children). The bus configure code needs changes
* to support how the busses are arranged on this chip. We also
* need to only configure devices in the private device space on
* the Secondary bus.
*/
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
ioext = extent_create("pciio",
sc->sc_ioout_xlate + sc->sc_ioout_xlate_offset,
sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
#ifdef I80321_USE_DIRECT_WIN
memext = extent_create("pcimem", VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SKIP,
VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SIZE- 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
#else
memext = extent_create("pcimem", sc->sc_owin[0].owin_xlate_lo,
sc->sc_owin[0].owin_xlate_lo + VERDE_OUT_XLATE_MEM_WIN_SIZE - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
#endif
aprint_normal("%s: configuring PCI bus\n", sc->sc_dev.dv_xname);
pci_configure_bus(pc, ioext, memext, NULL, busno, arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
#endif
}
void
pci_init_extents(void)
{
bios_memmap_t *bmp;
u_int64_t size;
if (pciio_ex == NULL) {
/*
* We only have 64K of addressable I/O space.
* However, since BARs may contain garbage, we cover
* the full 32-bit address space defined by PCI of
* which we only make the first 64K available.
*/
pciio_ex = extent_create("pciio", 0, 0xffffffff, M_DEVBUF,
NULL, 0, EX_NOWAIT | EX_FILLED);
if (pciio_ex == NULL)
return;
extent_free(pciio_ex, 0, 0x10000, M_NOWAIT);
}
if (pcimem_ex == NULL) {
pcimem_ex = extent_create("pcimem", 0, 0xffffffff, M_DEVBUF,
NULL, 0, EX_NOWAIT);
if (pcimem_ex == NULL)
return;
for (bmp = bios_memmap; bmp->type != BIOS_MAP_END; bmp++) {
/*
* Ignore address space beyond 4G.
*/
if (bmp->addr >= 0x100000000ULL)
continue;
size = bmp->size;
if (bmp->addr + size >= 0x100000000ULL)
size = 0x100000000ULL - bmp->addr;
/* Ignore zero-sized regions. */
if (size == 0)
continue;
if (extent_alloc_region(pcimem_ex, bmp->addr, size,
EX_NOWAIT))
printf("memory map conflict 0x%llx/0x%llx\n",
bmp->addr, bmp->size);
}
/* Take out the video buffer area and BIOS areas. */
extent_alloc_region(pcimem_ex, IOM_BEGIN, IOM_SIZE,
EX_CONFLICTOK | EX_NOWAIT);
}
}
void
becc_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct becc_softc *sc = cookie;
struct extent *ioext, *memext;
#endif
pc->pc_conf_v = cookie;
pc->pc_attach_hook = becc_pci_attach_hook;
pc->pc_bus_maxdevs = becc_pci_bus_maxdevs;
pc->pc_make_tag = becc_pci_make_tag;
pc->pc_decompose_tag = becc_pci_decompose_tag;
pc->pc_conf_read = becc_pci_conf_read;
pc->pc_conf_write = becc_pci_conf_write;
pc->pc_conf_interrupt = becc_pci_conf_interrupt;
pc->pc_intr_v = cookie;
pc->pc_intr_map = becc_pci_intr_map;
pc->pc_intr_string = becc_pci_intr_string;
pc->pc_intr_evcnt = becc_pci_intr_evcnt;
pc->pc_intr_establish = becc_pci_intr_establish;
pc->pc_intr_disestablish = becc_pci_intr_disestablish;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
/*
* Configure the PCI bus.
*
* XXX We need to revisit this. We only configure the Secondary
* bus (and its children). The bus configure code needs changes
* to support how the busses are arranged on this chip. We also
* need to only configure devices in the private device space on
* the Secondary bus.
*/
/* Reserve the bottom 32K of the PCI address space. */
ioext = extent_create("pciio", sc->sc_ioout_xlate + (32 * 1024),
sc->sc_ioout_xlate + (64 * 1024) - 1,
NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem", sc->sc_owin_xlate[0],
sc->sc_owin_xlate[0] + BECC_PCI_MEM1_SIZE - 1,
NULL, 0, EX_NOWAIT);
aprint_normal("%s: configuring PCI bus\n", device_xname(sc->sc_dev));
pci_configure_bus(pc, ioext, memext, NULL, 0, arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
#endif
}
static void
rmixl_pcix_init(rmixl_pcix_softc_t *sc)
{
pci_chipset_tag_t pc = &sc->sc_pci_chipset;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct extent *ioext, *memext;
#endif
pc->pc_conf_v = (void *)sc;
pc->pc_attach_hook = rmixl_pcix_attach_hook;
pc->pc_bus_maxdevs = rmixl_pcix_bus_maxdevs;
pc->pc_make_tag = rmixl_pcix_make_tag;
pc->pc_decompose_tag = rmixl_pcix_decompose_tag;
pc->pc_conf_read = rmixl_pcix_conf_read;
pc->pc_conf_write = rmixl_pcix_conf_write;
pc->pc_intr_v = (void *)sc;
pc->pc_intr_map = rmixl_pcix_intr_map;
pc->pc_intr_string = rmixl_pcix_intr_string;
pc->pc_intr_evcnt = rmixl_pcix_intr_evcnt;
pc->pc_intr_establish = rmixl_pcix_intr_establish;
pc->pc_intr_disestablish = rmixl_pcix_intr_disestablish;
pc->pc_conf_interrupt = rmixl_conf_interrupt;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
/*
* Configure the PCI bus.
*/
struct rmixl_config *rcp = &rmixl_configuration;
aprint_normal_dev(sc->sc_dev, "%s: configuring PCI bus\n");
ioext = extent_create("pciio",
rcp->rc_pci_io_pbase,
rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem",
rcp->rc_pci_mem_pbase,
rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, ioext, memext, NULL, 0,
mips_cache_info.mci_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
#endif
}
void
sandpoint_bus_space_init(void)
{
int error;
ioport_ex = extent_create("ioport", 0, 0x00bfffff, M_DEVBUF,
(caddr_t)ioport_ex_storage, sizeof(ioport_ex_storage),
EX_NOCOALESCE|EX_NOWAIT);
error = extent_alloc_region(ioport_ex, 0x10000, 0x7F0000, EX_NOWAIT);
if (error)
panic("sandpoint_bus_space_init: can't block out reserved I/O space 0x10000-0x7fffff: error=%d\n", error);
iomem_ex = extent_create("iomem", 0x80000000, 0xfdffffff, M_DEVBUF,
(caddr_t)iomem_ex_storage, sizeof(iomem_ex_storage),
EX_NOCOALESCE|EX_NOWAIT);
}
int
b3_617_init(struct b3_617_softc *sc)
{
unsigned int i;
if (b3_617_reset(sc))
return (-1);
/* all maps invalid */
for (i = MR_PCI_VME; i < MR_PCI_VME + MR_PCI_VME_SIZE; i += 4)
write_mapmem(sc, i, MR_RAM_INVALID);
for (i = MR_VME_PCI; i < MR_VME_PCI + MR_VME_PCI_SIZE; i += 4)
write_mapmem(sc, i, MR_RAM_INVALID);
for (i = MR_DMA_PCI; i < MR_DMA_PCI + MR_DMA_PCI_SIZE; i += 4)
write_mapmem(sc, i, MR_RAM_INVALID);
/*
* set up scatter page allocation control
*/
sc->vmeext = extent_create("pcivme", MR_PCI_VME,
MR_PCI_VME + MR_PCI_VME_SIZE - 1,
sc->vmemap, sizeof(sc->vmemap),
EX_NOCOALESCE);
#if 0
sc->pciext = extent_create("vmepci", MR_VME_PCI,
MR_VME_PCI + MR_VME_PCI_SIZE - 1,
sc->pcimap, sizeof(sc->pcimap),
EX_NOCOALESCE);
sc->dmaext = extent_create("dmapci", MR_DMA_PCI,
MR_DMA_PCI + MR_DMA_PCI_SIZE - 1,
sc->dmamap, sizeof(sc->dmamap),
EX_NOCOALESCE);
#endif
/*
* init int handler queue,
* enable interrupts if PCI interrupt available
*/
TAILQ_INIT(&(sc->intrhdls));
sc->strayintrs = 0;
if (sc->sc_ih)
write_csr_byte(sc, LOC_INT_CTRL, LIC_INT_ENABLE);
/* no error ints */
write_csr_byte(sc, REM_CMD2, 0); /* enables VME IRQ */
return (0);
}
void
i80312_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct i80312_softc *sc = cookie;
struct extent *ioext, *memext;
pcireg_t binfo;
int sbus;
#endif
pc->pc_conf_v = cookie;
pc->pc_attach_hook = i80312_pci_attach_hook;
pc->pc_bus_maxdevs = i80312_pci_bus_maxdevs;
pc->pc_make_tag = i80312_pci_make_tag;
pc->pc_decompose_tag = i80312_pci_decompose_tag;
pc->pc_conf_read = i80312_pci_conf_read;
pc->pc_conf_write = i80312_pci_conf_write;
pc->pc_conf_interrupt = i80312_pci_conf_interrupt;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
/*
* Configure the PCI bus.
*
* XXX We need to revisit this. We only configure the Secondary
* bus (and its children). The bus configure code needs changes
* to support how the busses are arranged on this chip. We also
* need to only configure devices in the private device space on
* the Secondary bus.
*/
binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
/* pbus = PPB_BUSINFO_PRIMARY(binfo); */
sbus = PPB_BUSINFO_SECONDARY(binfo);
ioext = extent_create("pciio", sc->sc_sioout_base,
sc->sc_sioout_base + sc->sc_sioout_size - 1,
NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem", sc->sc_smemout_base,
sc->sc_smemout_base + sc->sc_smemout_size - 1,
NULL, 0, EX_NOWAIT);
aprint_normal_dev(sc->sc_dev, "configuring Secondary PCI bus\n");
pci_configure_bus(pc, ioext, memext, NULL, sbus, arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
#endif
}
/* create default bus_space_tag */
bus_space_tag_t
bus_space_create(bus_space_tag_t t, const char *name,
bus_addr_t addr, bus_size_t size)
{
struct playstation2_bus_space *pbs = (void *)t; /* discard const */
if (pbs == 0)
pbs = malloc(sizeof(*pbs), M_DEVBUF, M_NOWAIT);
KDASSERT(pbs);
memset(pbs, 0, sizeof(*pbs));
/* set default method */
*pbs = _default_bus_space;
pbs->pbs_cookie = pbs;
/* set access region */
if (size == 0) {
pbs->pbs_base_addr = addr; /* no extent */
} else {
pbs->pbs_extent = extent_create(name, addr, addr + size - 1,
M_DEVBUF, 0, 0, EX_NOWAIT);
if (pbs->pbs_extent == 0) {
panic("%s:: unable to create bus_space for "
"0x%08lx-%#lx\n", __FUNCTION__, addr, size);
}
}
return (pbs);
}
/*
* initialise the UltraSPARC IOMMU (Hypervisior):
* - allocate and setup the iotsb.
* - enable the IOMMU
* - create a private DVMA map.
*/
void
viommu_init(char *name, struct iommu_state *is, int tsbsize,
u_int32_t iovabase)
{
/*
* Setup the iommu.
*
* The sun4v iommu is accessed through the hypervisor so we will
* deal with it here..
*/
is->is_tsbsize = tsbsize;
if (iovabase == (u_int32_t)-1) {
is->is_dvmabase = IOTSB_VSTART(is->is_tsbsize);
is->is_dvmaend = IOTSB_VEND;
} else {
is->is_dvmabase = iovabase;
is->is_dvmaend = iovabase + IOTSB_VSIZE(tsbsize) - 1;
}
/*
* Allocate a dvma map.
*/
printf("dvma map %x-%x", is->is_dvmabase, is->is_dvmaend);
is->is_dvmamap = extent_create(name,
is->is_dvmabase, (u_long)is->is_dvmaend + 1,
M_DEVBUF, 0, 0, EX_NOWAIT);
mtx_init(&is->is_mtx, IPL_HIGH);
printf("\n");
}
static void
necpbattach(device_t parent, device_t self, void *aux)
{
struct necpb_softc *sc = device_private(self);
struct pcibus_attach_args pba;
pci_chipset_tag_t pc;
int i;
sc->sc_dev = self;
necpbfound = 1;
aprint_normal("\n");
sc->sc_ncp = &necpb_main_context;
necpb_init(sc->sc_ncp);
pc = &sc->sc_ncp->nc_pc;
#ifdef PCI_NETBSD_CONFIGURE
pc->pc_ioext = extent_create("necpbio", 0x00100000, 0x01ffffff,
NULL, 0, EX_NOWAIT);
pc->pc_memext = extent_create("necpbmem", 0x08000000, 0x3fffffff,
NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0,
mips_cache_info.mci_dcache_align);
#endif
out32(RD94_SYS_PCI_INTMASK, 0xf);
for (i = 0; i < 4; i++)
necpb_inttbl[i] = NULL;
(*platform->set_intr)(MIPS_INT_MASK_2, necpb_intr, ARC_INTPRI_PCIISA);
pba.pba_iot = &sc->sc_ncp->nc_iot;
pba.pba_memt = &sc->sc_ncp->nc_memt;
pba.pba_dmat = &sc->sc_ncp->nc_dmat;
pba.pba_dmat64 = NULL;
pba.pba_pc = pc;
pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
config_found_ia(self, "pcibus", &pba, pcibusprint);
}
/*
* Initialize the external I/O extent map.
*/
void
iomap_init(void)
{
/* extiobase is initialized by pmap_bootstrap(). */
extio_ex = extent_create("extio", (u_long) extiobase,
(u_long) extiobase + (ptoa(EIOMAPSIZE) - 1), M_DEVBUF,
(void *) extio_ex_storage, sizeof(extio_ex_storage),
EX_NOCOALESCE|EX_NOWAIT);
}
void
x86_bus_space_init()
{
/*
* Initialize the I/O port and I/O mem extent maps.
* Note: we don't have to check the return value since
* creation of a fixed extent map will never fail (since
* descriptor storage has already been allocated).
*
* N.B. The iomem extent manages _all_ physical addresses
* on the machine. When the amount of RAM is found, the two
* extents of RAM are allocated from the map (0 -> ISA hole
* and end of ISA hole -> end of RAM).
*/
ioport_ex = extent_create("ioport", 0x0, 0xffff, M_DEVBUF,
(caddr_t)ioport_ex_storage, sizeof(ioport_ex_storage),
EX_NOCOALESCE|EX_NOWAIT);
iomem_ex = extent_create("iomem", 0x0, 0xffffffff, M_DEVBUF,
(caddr_t)iomem_ex_storage, sizeof(iomem_ex_storage),
EX_NOCOALESCE|EX_NOWAIT);
}
void
arc_bus_space_init_extent(bus_space_tag_t bst, void *storage,
size_t storagesize)
{
bst->bs_extent = extent_create(bst->bs_name,
bst->bs_start, bst->bs_start + bst->bs_size, M_DEVBUF,
storage, storagesize, EX_NOWAIT);
if (bst->bs_extent == NULL)
panic("arc_bus_space_init_extent: cannot create extent map %s",
bst->bs_name);
}
/*
* PCI resource handling
*/
struct extent *
octeon_pcibus_get_resource_extent(pci_chipset_tag_t pc, int io)
{
struct octeon_pcibus_softc *sc = pc->pc_conf_v;
struct extent *ex;
char *exname;
int exnamesz;
int errors;
exnamesz = 1 + 16 + 4;
exname = (char *)malloc(exnamesz, M_DEVBUF, M_NOWAIT);
if (exname == NULL)
return NULL;
snprintf(exname, exnamesz, "%s%s", sc->sc_dev.dv_xname,
io ? "_io" : "_mem");
ex = extent_create(exname, 0, 0xffffffffffffffff, M_DEVBUF, NULL, 0,
EX_NOWAIT | EX_FILLED);
if (ex == NULL)
goto out;
exname = NULL;
errors = 0;
if (io) {
if (extent_free(ex, _OCTEON_PCIBUS_PCIIO_BASE, _OCTEON_PCIBUS_PCIIO_SIZE,
EX_NOWAIT) != 0)
errors++;
} else {
if (extent_free(ex, _OCTEON_PCIBUS_PCIMEM_BASE, _OCTEON_PCIBUS_PCIMEM_SIZE,
EX_NOWAIT) != 0)
errors++;
}
if (errors != 0) {
extent_destroy(ex);
ex = NULL;
}
#ifdef OCTEON_PCIBUS_DEBUG
extent_print(ex);
#endif
out:
if (exname != NULL)
free(exname, M_DEVBUF);
return ex;
}
static void
vmeattach_mainbus(device_t parent, device_t self, void *aux)
{
#if defined(SUN4)
struct mainbus_attach_args *ma = aux;
struct sparcvme_softc *sc = device_private(self);
struct vmebus_attach_args vba;
vme_attached = 1;
sc->sc_bustag = ma->ma_bustag;
sc->sc_dmatag = ma->ma_dmatag;
/* VME interrupt entry point */
sc->sc_vmeintr = vmeintr4;
/*XXX*/ sparc_vme_chipset_tag.cookie = sc;
/*XXX*/ sparc_vme_chipset_tag.vct_dmamap_create = sparc_vct4_dmamap_create;
/*XXX*/ sparc_vme_chipset_tag.vct_dmamap_destroy = sparc_vct_dmamap_destroy;
/*XXX*/ sparc_vme4_dma_tag._cookie = sc;
vba.va_vct = &sparc_vme_chipset_tag;
vba.va_bdt = &sparc_vme4_dma_tag;
vba.va_slaveconfig = 0;
/* Fall back to our own `range' construction */
sc->sc_range = vmebus_translations;
sc->sc_nrange =
sizeof(vmebus_translations)/sizeof(vmebus_translations[0]);
vme_dvmamap = extent_create("vmedvma", VME4_DVMA_BASE, VME4_DVMA_END,
0, 0, EX_NOWAIT);
if (vme_dvmamap == NULL)
panic("vme: unable to allocate DVMA map");
printf("\n");
(void)config_found(self, &vba, 0);
#endif /* SUN4 */
return;
}
void
dvma_init(void)
{
vaddr_t segmap_addr;
/*
* Create phys_map covering the entire DVMA space,
* then allocate the segment pool from that. The
* remainder will be used as the DVMA page pool.
*
* Note that no INTRSAFE is needed here because the
* dvma_extent manages things handled in interrupt
* context.
*/
phys_map = uvm_map_create(pmap_kernel(),
DVMA_MAP_BASE, DVMA_MAP_END, 0);
if (phys_map == NULL)
panic("unable to create DVMA map");
/*
* Reserve the DVMA space used for segment remapping.
* The remainder of phys_map is used for DVMA scratch
* memory pages (i.e. driver control blocks, etc.)
*/
segmap_addr = uvm_km_alloc(phys_map, dvma_segmap_size, 0,
UVM_KMF_VAONLY | UVM_KMF_WAITVA);
if (segmap_addr != DVMA_MAP_BASE)
panic("dvma_init: unable to allocate DVMA segments");
/*
* Create the VM pool used for mapping whole segments
* into DVMA space for the purpose of data transfer.
*/
dvma_extent = extent_create("dvma", segmap_addr,
segmap_addr + (dvma_segmap_size - 1), M_DEVBUF,
NULL, 0, EX_NOCOALESCE|EX_NOWAIT);
}
int
tx3912video_framebuffer_alloc(struct video_chip *chip, paddr_t fb_start,
paddr_t *fb_end /* buffer allocation hint */)
{
struct extent_fixed ex_fixed[10];
struct extent *ex;
u_long addr, size;
int error;
/* calcurate frame buffer size */
size = (chip->vc_fbwidth * chip->vc_fbheight * chip->vc_fbdepth) /
NBBY;
/* extent V-RAM region */
ex = extent_create("Frame buffer address", fb_start, *fb_end,
(void *)ex_fixed, sizeof ex_fixed,
EX_NOWAIT);
if (ex == 0)
return (1);
/* Allocate V-RAM area */
error = extent_alloc_subregion(ex, fb_start, fb_start + size - 1,
size, TX3912_FRAMEBUFFER_ALIGNMENT,
TX3912_FRAMEBUFFER_BOUNDARY, EX_FAST|EX_NOWAIT, &addr);
extent_destroy(ex);
if (error != 0)
return (1);
chip->vc_fbpaddr = addr;
chip->vc_fbvaddr = MIPS_PHYS_TO_KSEG1(addr);
chip->vc_fbsize = size;
*fb_end = addr + size;
return (0);
}
/*
* Attach the mainbus.
*/
void
mainbus_attach(device_t parent, device_t self, void *aux)
{
struct pcibus_attach_args pba;
#if NPCI > 0
struct genppc_pci_chipset_businfo *pbi;
#endif
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif
mainbus_found = 1;
aprint_normal("\n");
/* attach cpu */
config_found_ia(self, "mainbus", NULL, mainbus_print);
/*
* XXX Note also that the presence of a PCI bus should
* XXX _always_ be checked, and if present the bus should be
* XXX 'found'. However, because of the structure of the code,
* XXX that's not currently possible.
*/
#if NPCI > 0
genppc_pct = malloc(sizeof(struct genppc_pci_chipset), M_DEVBUF,
M_NOWAIT);
KASSERT(genppc_pct != NULL);
mvmeppc_pci_get_chipset_tag(genppc_pct);
pbi = malloc(sizeof(struct genppc_pci_chipset_businfo),
M_DEVBUF, M_NOWAIT);
KASSERT(pbi != NULL);
pbi->pbi_properties = prop_dictionary_create();
KASSERT(pbi->pbi_properties != NULL);
SIMPLEQ_INIT(&genppc_pct->pc_pbi);
SIMPLEQ_INSERT_TAIL(&genppc_pct->pc_pbi, pbi, next);
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("pciio", 0x00008000, 0x0000ffff,
NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem", 0x00000000, 0x0fffffff,
NULL, 0, EX_NOWAIT);
pci_configure_bus(genppc_pct, ioext, memext, NULL, 0, CACHELINESIZE);
extent_destroy(ioext);
extent_destroy(memext);
#endif
pba.pba_iot = &prep_io_space_tag;
pba.pba_memt = &prep_mem_space_tag;
pba.pba_dmat = &pci_bus_dma_tag;
pba.pba_dmat64 = NULL;
pba.pba_pc = genppc_pct;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
config_found_ia(self, "pcibus", &pba, pcibusprint);
#endif
}
static void
macepci_attach(device_t parent, device_t self, void *aux)
{
struct macepci_softc *sc = device_private(self);
pci_chipset_tag_t pc = &sc->sc_pc;
struct mace_attach_args *maa = aux;
struct pcibus_attach_args pba;
u_int32_t control;
int rev;
if (bus_space_subregion(maa->maa_st, maa->maa_sh,
maa->maa_offset, 0, &pc->ioh) )
panic("macepci_attach: couldn't map");
pc->iot = maa->maa_st;
rev = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_REVISION);
printf(": rev %d\n", rev);
pc->pc_bus_maxdevs = macepci_bus_maxdevs;
pc->pc_conf_read = macepci_conf_read;
pc->pc_conf_write = macepci_conf_write;
pc->pc_intr_map = macepci_intr_map;
pc->pc_intr_string = macepci_intr_string;
pc->intr_establish = mace_intr_establish;
pc->intr_disestablish = mace_intr_disestablish;
bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR, 0);
bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS, 0);
/* Turn on PCI error interrupts */
bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONTROL,
MACE_PCI_CONTROL_SERR_ENA |
MACE_PCI_CONTROL_PARITY_ERR |
MACE_PCI_CONTROL_PARK_LIU |
MACE_PCI_CONTROL_OVERRUN_INT |
MACE_PCI_CONTROL_PARITY_INT |
MACE_PCI_CONTROL_SERR_INT |
MACE_PCI_CONTROL_IT_INT |
MACE_PCI_CONTROL_RE_INT |
MACE_PCI_CONTROL_DPED_INT |
MACE_PCI_CONTROL_TAR_INT |
MACE_PCI_CONTROL_MAR_INT);
/*
* Enable all MACE PCI interrupts. They will be masked by
* the CRIME code.
*/
control = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_CONTROL);
control |= CONTROL_INT_MASK;
bus_space_write_4(pc->iot, pc->ioh, MACEPCI_CONTROL, control);
#if NPCI > 0
pc->pc_ioext = extent_create("macepciio", 0x00001000, 0x01ffffff,
NULL, 0, EX_NOWAIT);
pc->pc_memext = extent_create("macepcimem", 0x80100000, 0x81ffffff,
NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0,
mips_cache_info.mci_dcache_align);
memset(&pba, 0, sizeof pba);
/*XXX*/ pba.pba_iot = SGIMIPS_BUS_SPACE_IO;
/*XXX*/ pba.pba_memt = SGIMIPS_BUS_SPACE_MEM;
pba.pba_dmat = &pci_bus_dma_tag;
pba.pba_dmat64 = NULL;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY |
PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
pba.pba_pc = pc;
#ifdef MACEPCI_IO_WAS_BUGGY
if (rev == 0)
pba.pba_flags &= ~PCI_FLAGS_IO_OKAY; /* Buggy? */
#endif
cpu_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc);
config_found_ia(self, "pcibus", &pba, pcibusprint);
#endif
}
void
hppa_init()
{
extern int kernel_text, end;
struct pdc_hwtlb pdc_hwtlb PDC_ALIGNMENT;
struct pdc_coproc pdc_coproc PDC_ALIGNMENT;
vm_offset_t v, vstart, vend;
register int pdcerr;
int usehpt;
/* init PDC iface, so we can call em easy */
pdc_init();
/* calculate cpu speed */
cpu_hzticks = (PAGE0->mem_10msec * 100) / hz;
delay_init();
/*
* get cache parameters from the PDC
*/
if ((pdcerr = pdc_call((iodcio_t)pdc, 0, PDC_CACHE, PDC_CACHE_DFLT,
&pdc_cache)) < 0) {
#ifdef DIAGNOSTIC
printf("Warning: PDC_CACHE call Ret'd %d\n", pdcerr);
#endif
}
dcache_line_mask = pdc_cache.dc_conf.cc_line * 16 - 1;
dcache_size = pdc_cache.dc_size;
dcache_stride = pdc_cache.dc_stride;
icache_stride = pdc_cache.ic_stride;
/*
* purge TLBs and flush caches
*/
if (pdc_call((iodcio_t)pdc, 0, PDC_BLOCK_TLB, PDC_BTLB_PURGE_ALL) < 0)
printf("WARNING: BTLB purge failed\n");
ptlball();
fcacheall();
/* calculate HPT size */
hpt_hashsize = PAGE0->imm_max_mem / NBPG;
mtctl(hpt_hashsize - 1, CR_HPTMASK);
/*
* If we want to use the HW TLB support, ensure that it exists.
*/
if (pdc_call((iodcio_t)pdc, 0, PDC_TLB, PDC_TLB_INFO, &pdc_hwtlb) &&
!pdc_hwtlb.min_size && !pdc_hwtlb.max_size) {
printf("WARNING: no HW tlb walker\n");
usehpt = 0;
} else {
usehpt = 1;
#ifdef DEBUG
printf("hwtlb: %u-%u, %u/",
pdc_hwtlb.min_size, pdc_hwtlb.max_size, hpt_hashsize);
#endif
if (hpt_hashsize > pdc_hwtlb.max_size)
hpt_hashsize = pdc_hwtlb.max_size;
else if (hpt_hashsize < pdc_hwtlb.min_size)
hpt_hashsize = pdc_hwtlb.min_size;
#ifdef DEBUG
printf("%u (0x%x)\n", hpt_hashsize,
hpt_hashsize * sizeof(struct hpt_entry));
#endif
}
totalphysmem = PAGE0->imm_max_mem / NBPG;
resvmem = ((vm_offset_t)&kernel_text) / NBPG;
vstart = hppa_round_page(&end);
vend = VM_MAX_KERNEL_ADDRESS;
/* we hope this won't fail */
hppa_ex = extent_create("mem", 0x0, 0xffffffff, M_DEVBUF,
(caddr_t)mem_ex_storage,
sizeof(mem_ex_storage),
EX_NOCOALESCE|EX_NOWAIT);
if (extent_alloc_region(hppa_ex, 0, (vm_offset_t)PAGE0->imm_max_mem,
EX_NOWAIT))
panic("cannot reserve main memory");
/*
* Allocate space for system data structures. We are given
* a starting virtual address and we return a final virtual
* address; along the way we set each data structure pointer.
*
* We call allocsys() with 0 to find out how much space we want,
* allocate that much and fill it with zeroes, and the call
* allocsys() again with the correct base virtual address.
*/
v = vstart;
#define valloc(name, type, num) \
(name) = (type *)v; v = (vm_offset_t)((name)+(num))
#ifdef REAL_CLISTS
valloc(cfree, struct cblock, nclist);
#endif
valloc(callout, struct callout, ncallout);
nswapmap = maxproc * 2;
valloc(swapmap, struct map, nswapmap);
#ifdef SYSVSHM
valloc(shmsegs, struct shmid_ds, shminfo.shmmni);
#endif
#ifdef SYSVSEM
valloc(sema, struct semid_ds, seminfo.semmni);
valloc(sem, struct sem, seminfo.semmns);
/* This is pretty disgusting! */
valloc(semu, int, (seminfo.semmnu * seminfo.semusz) / sizeof(int));
#endif
#ifdef SYSVMSG
valloc(msgpool, char, msginfo.msgmax);
valloc(msgmaps, struct msgmap, msginfo.msgseg);
valloc(msghdrs, struct msg, msginfo.msgtql);
valloc(msqids, struct msqid_ds, msginfo.msgmni);
#endif
#ifndef BUFCACHEPERCENT
#define BUFCACHEPERCENT 10
#endif /* BUFCACHEPERCENT */
if (bufpages == 0)
bufpages = totalphysmem / BUFCACHEPERCENT / CLSIZE;
if (nbuf == 0) {
nbuf = bufpages;
if (nbuf < 16)
nbuf = 16;
}
/* Restrict to at most 70% filled kvm */
if (nbuf * MAXBSIZE >
(VM_MAX_KERNEL_ADDRESS-VM_MIN_KERNEL_ADDRESS) * 7 / 10)
nbuf = (VM_MAX_KERNEL_ADDRESS-VM_MIN_KERNEL_ADDRESS) /
MAXBSIZE * 7 / 10;
/* More buffer pages than fits into the buffers is senseless. */
if (bufpages > nbuf * MAXBSIZE / CLBYTES)
bufpages = nbuf * MAXBSIZE / CLBYTES;
if (nswbuf == 0) {
nswbuf = (nbuf / 2) & ~1; /* force even */
if (nswbuf > 256)
nswbuf = 256; /* sanity */
}
valloc(swbuf, struct buf, nswbuf);
valloc(buf, struct buf, nbuf);
#undef valloc
bzero ((void *)vstart, (v - vstart));
vstart = v;
pmap_bootstrap(&vstart, &vend);
physmem = totalphysmem - btoc(vstart);
/* alloc msgbuf */
if (!(msgbufp = (void *)pmap_steal_memory(sizeof(struct msgbuf),
NULL, NULL)))
panic("cannot allocate msgbuf");
msgbufmapped = 1;
#ifdef DEBUG
printf("mem: %x+%x, %x\n", physmem, resvmem, totalphysmem);
#endif
/* Turn on the HW TLB assist */
if (usehpt) {
if ((pdcerr = pdc_call((iodcio_t)pdc, 0, PDC_TLB,
PDC_TLB_CONFIG, &pdc_hwtlb, hpt_table,
sizeof(struct hpt_entry) * hpt_hashsize,
PDC_TLB_WORD3)) < 0) {
printf("Warning: HW TLB init failed (%d), disabled\n",
pdcerr);
usehpt = 0;
} else
printf("HW TLB(%d entries at 0x%x) initialized (%d)\n",
hpt_hashsize, hpt_table, pdcerr);
}
/*
* Locate any coprocessors and enable them by setting up the CCR.
* SFU's are ignored (since we dont have any). Also, initialize
* the floating point registers here.
*/
if ((pdcerr = pdc_call((iodcio_t)pdc, 0, PDC_COPROC, PDC_COPROC_DFLT,
&pdc_coproc)) < 0)
printf("WARNING: PDC_COPROC call Ret'd %d\n", pdcerr);
else {
#ifdef DEBUG
printf("pdc_coproc: %x, %x\n", pdc_coproc.ccr_enable,
pdc_coproc.ccr_present);
#endif
}
copr_sfu_config = pdc_coproc.ccr_enable;
mtctl(copr_sfu_config & CCR_MASK, CR_CCR);
/*
fprinit(&fpcopr_version);
fpcopr_version = (fpcopr_version & 0x003ff800) >> 11;
mtctl(CR_CCR, 0);
*/
/*
* Clear the FAULT light (so we know when we get a real one)
* PDC_COPROC apparently turns it on (for whatever reason).
*/
pdcerr = PDC_OSTAT(PDC_OSTAT_RUN) | 0xCEC0;
(void) (*pdc)(PDC_CHASSIS, PDC_CHASSIS_DISP, pdcerr);
#ifdef DDB
ddb_init();
#endif
#ifdef DEBUG
printf("hppa_init: leaving\n");
#endif
kernelmapped++;
}
/*
* Machine-dependent startup code
*/
void
cpu_startup()
{
caddr_t v;
int sz;
#ifdef DEBUG
extern int pmapdebug;
int opmapdebug = pmapdebug;
#endif
vaddr_t minaddr, maxaddr;
extern struct user *proc0paddr;
#ifdef DEBUG
pmapdebug = 0;
#endif
if (CPU_ISSUN4M) {
extern int stackgap_random;
stackgap_random = STACKGAP_RANDOM_SUN4M;
}
/*
* fix message buffer mapping, note phys addr of msgbuf is 0
*/
pmap_map(MSGBUF_VA, 0, MSGBUFSIZE, VM_PROT_READ|VM_PROT_WRITE);
initmsgbuf((caddr_t)(MSGBUF_VA + (CPU_ISSUN4 ? 4096 : 0)), MSGBUFSIZE);
proc0.p_addr = proc0paddr;
/*
* Good {morning,afternoon,evening,night}.
*/
printf(version);
/*identifycpu();*/
printf("real mem = %u (%uMB)\n", ptoa(physmem),
ptoa(physmem)/1024/1024);
/*
* Find out how much space we need, allocate it,
* and then give everything true virtual addresses.
*/
sz = (int)allocsys((caddr_t)0);
if ((v = (caddr_t)uvm_km_alloc(kernel_map, round_page(sz))) == 0)
panic("startup: no room for tables");
if (allocsys(v) - v != sz)
panic("startup: table size inconsistency");
/*
* Determine how many buffers to allocate.
* We allocate bufcachepercent% of memory for buffer space.
*/
if (bufpages == 0)
bufpages = physmem * bufcachepercent / 100;
/* Restrict to at most 25% filled kvm */
if (bufpages >
(VM_MAX_KERNEL_ADDRESS-VM_MIN_KERNEL_ADDRESS) / PAGE_SIZE / 4)
bufpages = (VM_MAX_KERNEL_ADDRESS-VM_MIN_KERNEL_ADDRESS) /
PAGE_SIZE / 4;
/*
* Allocate a submap for exec arguments. This map effectively
* limits the number of processes exec'ing at any time.
*/
minaddr = vm_map_min(kernel_map);
exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
16*NCARGS, VM_MAP_PAGEABLE, FALSE, NULL);
/*
* Allocate a map for physio. Others use a submap of the kernel
* map, but we want one completely separate, even though it uses
* the same pmap.
*/
dvma_base = CPU_ISSUN4M ? DVMA4M_BASE : DVMA_BASE;
dvma_end = CPU_ISSUN4M ? DVMA4M_END : DVMA_END;
#if defined(SUN4M)
if (CPU_ISSUN4M) {
/*
* The DVMA space we want partially overrides kernel_map.
* Allocate it in kernel_map as well to prevent it from being
* used for other things.
*/
if (uvm_map(kernel_map, &dvma_base,
vm_map_max(kernel_map) - dvma_base,
NULL, UVM_UNKNOWN_OFFSET, 0,
UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE,
UVM_ADV_NORMAL, 0)))
panic("startup: can not steal dvma map");
}
#endif
phys_map = uvm_map_create(pmap_kernel(), dvma_base, dvma_end,
VM_MAP_INTRSAFE);
if (phys_map == NULL)
panic("unable to create DVMA map");
/*
* Allocate DVMA space and dump into a privately managed
* resource map for double mappings which is usable from
* interrupt contexts.
*/
if (uvm_km_valloc_wait(phys_map, (dvma_end-dvma_base)) != dvma_base)
panic("unable to allocate from DVMA map");
dvmamap_extent = extent_create("dvmamap", dvma_base, dvma_end,
M_DEVBUF, NULL, 0, EX_NOWAIT);
if (dvmamap_extent == 0)
panic("unable to allocate extent for dvma");
#ifdef DEBUG
pmapdebug = opmapdebug;
#endif
printf("avail mem = %lu (%luMB)\n", ptoa(uvmexp.free),
ptoa(uvmexp.free)/1024/1024);
/*
* Set up buffers, so they can be used to read disk labels.
*/
bufinit();
/* Early interrupt handlers initialization */
intr_init();
}
static void
pchbattach(device_t parent, device_t self, void *aux)
{
struct plb_attach_args *paa = aux;
struct pcibus_attach_args pba;
char devinfo[256];
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#ifdef PCI_CONFIGURE_VERBOSE
extern int pci_conf_debug;
pci_conf_debug = 1;
#endif
#endif
pci_chipset_tag_t pc = 0;
pcitag_t tag;
int class, id;
pci_machdep_init();
tag = pci_make_tag(pc, 0, 0, 0);
class = pci_conf_read(pc, tag, PCI_CLASS_REG);
id = pci_conf_read(pc, tag, PCI_ID_REG);
aprint_normal("\n");
pcifound = true;
/*
* All we do is print out a description. Eventually, we
* might want to add code that does something that's
* possibly chipset-specific.
*/
pci_devinfo(id, class, 0, devinfo, sizeof(devinfo));
aprprint_normal_dev(self, "%s (rev. 0x%02x)\n", devinfo,
PCI_REVISION(class));
pci_machdep_init(); /* Redundant... */
ibm4xx_setup_pci();
#ifdef PCI_CONFIGURE_VERBOSE
ibm4xx_show_pci_map();
#endif
if (bus_space_init(&pchb_io_tag, "pchbio", NULL, 0))
panic("pchbattach: can't init IO tag");
if (bus_space_init(&pchb_mem_tag, "pchbmem", NULL, 0))
panic("pchbattach: can't init MEM tag");
#ifdef PCI_NETBSD_CONFIGURE
memext = extent_create("pcimem", MIN_PCI_MEMADDR_NOPREFETCH,
MIN_PCI_MEMADDR_NOPREFETCH + 0x1fffffff, M_DEVBUF, NULL, 0,
EX_NOWAIT);
ioext = extent_create("pciio", MIN_PCI_PCI_IOADDR,
MIN_PCI_PCI_IOADDR + 0xffff, M_DEVBUF, NULL, 0, EX_NOWAIT);
pci_configure_bus(0, ioext, memext, NULL, 0, 32);
extent_destroy(memext);
extent_destroy(ioext);
#endif /* PCI_NETBSD_CONFIGURE */
#ifdef PCI_CONFIGURE_VERBOSE
printf("running config_found PCI\n");
#endif
/* IO window located @ e8000000 and maps to 0-0xffff */
pba.pba_iot = &pchb_io_tag;
/* PCI memory window is directly mapped */
pba.pba_memt = &pchb_mem_tag;
pba.pba_dmat = paa->plb_dmat;
pba.pba_dmat64 = NULL;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY;
config_found_ia(self, "pcibus", &pba, pchbprint);
}
static void
shpcic_attach(device_t parent, device_t self, void *aux)
{
struct pcibus_attach_args pba;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif
pcireg_t id, class;
char devinfo[256];
shpcic_found = 1;
aprint_naive("\n");
id = _reg_read_4(SH4_PCICONF0);
class = _reg_read_4(SH4_PCICONF2);
pci_devinfo(id, class, 1, devinfo, sizeof(devinfo));
aprint_normal(": %s\n", devinfo);
/* allow PCIC request */
_reg_write_4(SH4_BCR1, _reg_read_4(SH4_BCR1) | BCR1_BREQEN);
/* Initialize PCIC */
_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_RSTCTL);
delay(10 * 1000);
_reg_write_4(SH4_PCICR, PCICR_BASE);
/* Class: Host-Bridge */
_reg_write_4(SH4_PCICONF2,
PCI_CLASS_CODE(PCI_CLASS_BRIDGE, PCI_SUBCLASS_BRIDGE_HOST, 0x00));
#if !defined(DONT_INIT_PCIBSC)
#if defined(PCIBCR_BCR1_VAL)
_reg_write_4(SH4_PCIBCR1, PCIBCR_BCR1_VAL);
#else
_reg_write_4(SH4_PCIBCR1, _reg_read_4(SH4_BCR1) | BCR1_MASTER);
#endif
#if defined(PCIBCR_BCR2_VAL)
_reg_write_4(SH4_PCIBCR2, PCIBCR_BCR2_VAL);
#else
_reg_write_4(SH4_PCIBCR2, _reg_read_2(SH4_BCR2));
#endif
#if defined(SH4) && defined(SH7751R)
if (cpu_product == CPU_PRODUCT_7751R) {
#if defined(PCIBCR_BCR3_VAL)
_reg_write_4(SH4_PCIBCR3, PCIBCR_BCR3_VAL);
#else
_reg_write_4(SH4_PCIBCR3, _reg_read_2(SH4_BCR3));
#endif
}
#endif /* SH4 && SH7751R && PCIBCR_BCR3_VAL */
#if defined(PCIBCR_WCR1_VAL)
_reg_write_4(SH4_PCIWCR1, PCIBCR_WCR1_VAL);
#else
_reg_write_4(SH4_PCIWCR1, _reg_read_4(SH4_WCR1));
#endif
#if defined(PCIBCR_WCR2_VAL)
_reg_write_4(SH4_PCIWCR2, PCIBCR_WCR2_VAL);
#else
_reg_write_4(SH4_PCIWCR2, _reg_read_4(SH4_WCR2));
#endif
#if defined(PCIBCR_WCR3_VAL)
_reg_write_4(SH4_PCIWCR3, PCIBCR_WCR3_VAL);
#else
_reg_write_4(SH4_PCIWCR3, _reg_read_4(SH4_WCR3));
#endif
#if defined(PCIBCR_MCR_VAL)
_reg_write_4(SH4_PCIMCR, PCIBCR_MCR_VAL);
#else
_reg_write_4(SH4_PCIMCR, _reg_read_4(SH4_MCR));
#endif
#endif /* !DONT_INIT_PCIBSC */
/* set PCI I/O, memory base address */
_reg_write_4(SH4_PCIIOBR, SH4_PCIC_IO);
_reg_write_4(SH4_PCIMBR, SH4_PCIC_MEM);
/* set PCI local address 0 */
_reg_write_4(SH4_PCILSR0, (64 - 1) << 20);
_reg_write_4(SH4_PCILAR0, 0xac000000);
_reg_write_4(SH4_PCICONF5, 0xac000000);
/* set PCI local address 1 */
_reg_write_4(SH4_PCILSR1, (64 - 1) << 20);
_reg_write_4(SH4_PCILAR1, 0xac000000);
_reg_write_4(SH4_PCICONF6, 0x8c000000);
/* Enable I/O, memory, bus-master */
_reg_write_4(SH4_PCICONF1, PCI_COMMAND_IO_ENABLE
| PCI_COMMAND_MEM_ENABLE
| PCI_COMMAND_MASTER_ENABLE
| PCI_COMMAND_STEPPING_ENABLE
| PCI_STATUS_DEVSEL_MEDIUM);
/* Initialize done. */
_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_CFINIT);
/* set PCI controller interrupt priority */
intpri_intr_priority(SH4_INTEVT_PCIERR, shpcic_intr_priority[0]);
intpri_intr_priority(SH4_INTEVT_PCISERR, shpcic_intr_priority[1]);
/* PCI bus */
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("pciio",
SH4_PCIC_IO, SH4_PCIC_IO + SH4_PCIC_IO_SIZE - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem",
SH4_PCIC_MEM, SH4_PCIC_MEM + SH4_PCIC_MEM_SIZE - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
pci_configure_bus(NULL, ioext, memext, NULL, 0, sh_cache_line_size);
extent_destroy(ioext);
extent_destroy(memext);
#endif
/* PCI bus */
memset(&pba, 0, sizeof(pba));
pba.pba_iot = shpcic_get_bus_io_tag();
pba.pba_memt = shpcic_get_bus_mem_tag();
pba.pba_dmat = shpcic_get_bus_dma_tag();
pba.pba_dmat64 = NULL;
pba.pba_pc = NULL;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
config_found(self, &pba, NULL);
}
void
__C(CHIP,_bus_mem_init)(bus_space_tag_t t, void *v)
{
#ifdef CHIP_D_MEM_W1_SYS_START
struct extent *dex;
#endif
struct extent *sex;
/*
* Initialize the bus space tag.
*/
/* cookie */
t->abs_cookie = v;
/* mapping/unmapping */
t->abs_map = __C(CHIP,_mem_map);
t->abs_unmap = __C(CHIP,_mem_unmap);
t->abs_subregion = __C(CHIP,_mem_subregion);
t->abs_translate = __C(CHIP,_mem_translate);
t->abs_get_window = __C(CHIP,_mem_get_window);
/* allocation/deallocation */
t->abs_alloc = __C(CHIP,_mem_alloc);
t->abs_free = __C(CHIP,_mem_free);
/* get kernel virtual address */
t->abs_vaddr = __C(CHIP,_mem_vaddr);
/* mmap for user */
t->abs_mmap = __C(CHIP,_mem_mmap);
/* barrier */
t->abs_barrier = __C(CHIP,_mem_barrier);
/* read (single) */
t->abs_r_1 = __C(CHIP,_mem_read_1);
t->abs_r_2 = __C(CHIP,_mem_read_2);
t->abs_r_4 = __C(CHIP,_mem_read_4);
t->abs_r_8 = __C(CHIP,_mem_read_8);
/* read multiple */
t->abs_rm_1 = __C(CHIP,_mem_read_multi_1);
t->abs_rm_2 = __C(CHIP,_mem_read_multi_2);
t->abs_rm_4 = __C(CHIP,_mem_read_multi_4);
t->abs_rm_8 = __C(CHIP,_mem_read_multi_8);
/* read region */
t->abs_rr_1 = __C(CHIP,_mem_read_region_1);
t->abs_rr_2 = __C(CHIP,_mem_read_region_2);
t->abs_rr_4 = __C(CHIP,_mem_read_region_4);
t->abs_rr_8 = __C(CHIP,_mem_read_region_8);
/* write (single) */
t->abs_w_1 = __C(CHIP,_mem_write_1);
t->abs_w_2 = __C(CHIP,_mem_write_2);
t->abs_w_4 = __C(CHIP,_mem_write_4);
t->abs_w_8 = __C(CHIP,_mem_write_8);
/* write multiple */
t->abs_wm_1 = __C(CHIP,_mem_write_multi_1);
t->abs_wm_2 = __C(CHIP,_mem_write_multi_2);
t->abs_wm_4 = __C(CHIP,_mem_write_multi_4);
t->abs_wm_8 = __C(CHIP,_mem_write_multi_8);
/* write region */
t->abs_wr_1 = __C(CHIP,_mem_write_region_1);
t->abs_wr_2 = __C(CHIP,_mem_write_region_2);
t->abs_wr_4 = __C(CHIP,_mem_write_region_4);
t->abs_wr_8 = __C(CHIP,_mem_write_region_8);
/* set multiple */
t->abs_sm_1 = __C(CHIP,_mem_set_multi_1);
t->abs_sm_2 = __C(CHIP,_mem_set_multi_2);
t->abs_sm_4 = __C(CHIP,_mem_set_multi_4);
t->abs_sm_8 = __C(CHIP,_mem_set_multi_8);
/* set region */
t->abs_sr_1 = __C(CHIP,_mem_set_region_1);
t->abs_sr_2 = __C(CHIP,_mem_set_region_2);
t->abs_sr_4 = __C(CHIP,_mem_set_region_4);
t->abs_sr_8 = __C(CHIP,_mem_set_region_8);
/* copy */
t->abs_c_1 = __C(CHIP,_mem_copy_region_1);
t->abs_c_2 = __C(CHIP,_mem_copy_region_2);
t->abs_c_4 = __C(CHIP,_mem_copy_region_4);
t->abs_c_8 = __C(CHIP,_mem_copy_region_8);
#ifdef CHIP_D_MEM_W1_SYS_START
/* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */
dex = extent_create(__S(__C(CHIP,_bus_dmem)), 0x0UL,
0xffffffffffffffffUL,
(void *)CHIP_D_MEM_EX_STORE(v), CHIP_D_MEM_EX_STORE_SIZE(v),
EX_NOWAIT);
extent_alloc_region(dex, 0, 0xffffffffffffffffUL, EX_NOWAIT);
#ifdef CHIP_D_MEM_W1_BUS_START
#ifdef EXTENT_DEBUG
printf("dmem: freeing from 0x%lx to 0x%lx\n",
CHIP_D_MEM_W1_BUS_START(v), CHIP_D_MEM_W1_BUS_END(v));
#endif
extent_free(dex, CHIP_D_MEM_W1_BUS_START(v),
CHIP_D_MEM_W1_BUS_END(v) - CHIP_D_MEM_W1_BUS_START(v) + 1,
EX_NOWAIT);
#endif
#ifdef EXTENT_DEBUG
extent_print(dex);
#endif
CHIP_D_MEM_EXTENT(v) = dex;
#endif /* CHIP_D_MEM_W1_SYS_START */
/* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */
sex = extent_create(__S(__C(CHIP,_bus_smem)), 0x0UL,
0xffffffffffffffffUL,
(void *)CHIP_S_MEM_EX_STORE(v), CHIP_S_MEM_EX_STORE_SIZE(v),
EX_NOWAIT);
extent_alloc_region(sex, 0, 0xffffffffffffffffUL, EX_NOWAIT);
#ifdef CHIP_S_MEM_W1_BUS_START
#ifdef EXTENT_DEBUG
printf("smem: freeing from 0x%lx to 0x%lx\n",
CHIP_S_MEM_W1_BUS_START(v), CHIP_S_MEM_W1_BUS_END(v));
#endif
extent_free(sex, CHIP_S_MEM_W1_BUS_START(v),
CHIP_S_MEM_W1_BUS_END(v) - CHIP_S_MEM_W1_BUS_START(v) + 1,
EX_NOWAIT);
#endif
#ifdef CHIP_S_MEM_W2_BUS_START
if (CHIP_S_MEM_W2_BUS_START(v) != CHIP_S_MEM_W1_BUS_START(v)) {
#ifdef EXTENT_DEBUG
printf("smem: freeing from 0x%lx to 0x%lx\n",
CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v));
#endif
extent_free(sex, CHIP_S_MEM_W2_BUS_START(v),
CHIP_S_MEM_W2_BUS_END(v) - CHIP_S_MEM_W2_BUS_START(v) + 1,
EX_NOWAIT);
} else {
#ifdef EXTENT_DEBUG
printf("smem: window 2 (0x%lx to 0x%lx) overlaps window 1\n",
CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v));
#endif
}
#endif
#ifdef CHIP_S_MEM_W3_BUS_START
if (CHIP_S_MEM_W3_BUS_START(v) != CHIP_S_MEM_W1_BUS_START(v) &&
CHIP_S_MEM_W3_BUS_START(v) != CHIP_S_MEM_W2_BUS_START(v)) {
#ifdef EXTENT_DEBUG
printf("smem: freeing from 0x%lx to 0x%lx\n",
CHIP_S_MEM_W3_BUS_START(v), CHIP_S_MEM_W3_BUS_END(v));
#endif
extent_free(sex, CHIP_S_MEM_W3_BUS_START(v),
CHIP_S_MEM_W3_BUS_END(v) - CHIP_S_MEM_W3_BUS_START(v) + 1,
EX_NOWAIT);
} else {
#ifdef EXTENT_DEBUG
printf("smem: window 2 (0x%lx to 0x%lx) overlaps window 1\n",
CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v));
#endif
}
#endif
#ifdef EXTENT_DEBUG
extent_print(sex);
#endif
CHIP_S_MEM_EXTENT(v) = sex;
}
void
__C(CHIP,_bus_mem_init)(
bus_space_tag_t t,
void *v)
{
struct extent *ex;
/*
* Initialize the bus space tag.
*/
/* cookie */
t->abs_cookie = v;
/* mapping/unmapping */
t->abs_map = __C(CHIP,_mem_map);
t->abs_unmap = __C(CHIP,_mem_unmap);
t->abs_subregion = __C(CHIP,_mem_subregion);
t->abs_translate = __C(CHIP,_mem_translate);
t->abs_get_window = __C(CHIP,_mem_get_window);
/* allocation/deallocation */
t->abs_alloc = __C(CHIP,_mem_alloc);
t->abs_free = __C(CHIP,_mem_free);
/* get kernel virtual address */
t->abs_vaddr = __C(CHIP,_mem_vaddr);
/* mmap for user */
t->abs_mmap = __C(CHIP,_mem_mmap);
/* barrier */
t->abs_barrier = __C(CHIP,_mem_barrier);
/* read (single) */
t->abs_r_1 = __C(CHIP,_mem_read_1);
t->abs_r_2 = __C(CHIP,_mem_read_2);
t->abs_r_4 = __C(CHIP,_mem_read_4);
t->abs_r_8 = __C(CHIP,_mem_read_8);
/* read multiple */
t->abs_rm_1 = __C(CHIP,_mem_read_multi_1);
t->abs_rm_2 = __C(CHIP,_mem_read_multi_2);
t->abs_rm_4 = __C(CHIP,_mem_read_multi_4);
t->abs_rm_8 = __C(CHIP,_mem_read_multi_8);
/* read region */
t->abs_rr_1 = __C(CHIP,_mem_read_region_1);
t->abs_rr_2 = __C(CHIP,_mem_read_region_2);
t->abs_rr_4 = __C(CHIP,_mem_read_region_4);
t->abs_rr_8 = __C(CHIP,_mem_read_region_8);
/* write (single) */
t->abs_w_1 = __C(CHIP,_mem_write_1);
t->abs_w_2 = __C(CHIP,_mem_write_2);
t->abs_w_4 = __C(CHIP,_mem_write_4);
t->abs_w_8 = __C(CHIP,_mem_write_8);
/* write multiple */
t->abs_wm_1 = __C(CHIP,_mem_write_multi_1);
t->abs_wm_2 = __C(CHIP,_mem_write_multi_2);
t->abs_wm_4 = __C(CHIP,_mem_write_multi_4);
t->abs_wm_8 = __C(CHIP,_mem_write_multi_8);
/* write region */
t->abs_wr_1 = __C(CHIP,_mem_write_region_1);
t->abs_wr_2 = __C(CHIP,_mem_write_region_2);
t->abs_wr_4 = __C(CHIP,_mem_write_region_4);
t->abs_wr_8 = __C(CHIP,_mem_write_region_8);
/* set multiple */
t->abs_sm_1 = __C(CHIP,_mem_set_multi_1);
t->abs_sm_2 = __C(CHIP,_mem_set_multi_2);
t->abs_sm_4 = __C(CHIP,_mem_set_multi_4);
t->abs_sm_8 = __C(CHIP,_mem_set_multi_8);
/* set region */
t->abs_sr_1 = __C(CHIP,_mem_set_region_1);
t->abs_sr_2 = __C(CHIP,_mem_set_region_2);
t->abs_sr_4 = __C(CHIP,_mem_set_region_4);
t->abs_sr_8 = __C(CHIP,_mem_set_region_8);
/* copy */
t->abs_c_1 = __C(CHIP,_mem_copy_region_1);
t->abs_c_2 = __C(CHIP,_mem_copy_region_2);
t->abs_c_4 = __C(CHIP,_mem_copy_region_4);
t->abs_c_8 = __C(CHIP,_mem_copy_region_8);
ex = extent_create(__S(__C(CHIP,_bus_mem)), 0x0UL, 0xffffffffUL,
(void *)CHIP_MEM_EX_STORE(v), CHIP_MEM_EX_STORE_SIZE(v),
EX_NOWAIT|EX_NOCOALESCE);
CHIP_MEM_EXTENT(v) = ex;
}
void
pci_addr_fixup(struct pcibios_softc *sc, pci_chipset_tag_t pc, int maxbus)
{
extern paddr_t avail_end;
const char *verbose_header =
"[%s]-----------------------\n"
" device vendor product\n"
" register space address size\n"
"--------------------------------------------\n";
const char *verbose_footer =
"--------------------------[%3d devices bogus]\n";
const struct {
bus_addr_t start;
bus_size_t size;
char *name;
} system_reserve [] = {
{ 0xfec00000, 0x100000, "I/O APIC" },
{ 0xfee00000, 0x100000, "Local APIC" },
{ 0xfffe0000, 0x20000, "BIOS PROM" },
{ 0, 0, 0 }, /* terminator */
}, *srp;
paddr_t start;
int error;
sc->extent_mem = extent_create("PCI I/O memory space",
PCIADDR_MEM_START, PCIADDR_MEM_END, M_DEVBUF, 0, 0, EX_NOWAIT);
KASSERT(sc->extent_mem);
sc->extent_port = extent_create("PCI I/O port space",
PCIADDR_PORT_START, PCIADDR_PORT_END, M_DEVBUF, 0, 0, EX_NOWAIT);
KASSERT(sc->extent_port);
/*
* 1. check & reserve system BIOS setting.
*/
PCIBIOS_PRINTV((verbose_header, "System BIOS Setting"));
pci_device_foreach(sc, pc, maxbus, pciaddr_resource_reserve);
pci_device_foreach(sc, pc, maxbus, pciaddr_resource_reserve_disabled);
PCIBIOS_PRINTV((verbose_footer, sc->nbogus));
/*
* 2. reserve non-PCI area.
*/
for (srp = system_reserve; srp->size; srp++) {
error = extent_alloc_region(sc->extent_mem, srp->start,
srp->size, EX_NOWAIT| EX_MALLOCOK);
if (error != 0)
printf("WARNING: can't reserve area for %s.\n",
srp->name);
}
/*
* 3. determine allocation space
*/
start = round_page(avail_end + 1);
if (start < PCIADDR_ISAMEM_RESERVE)
start = PCIADDR_ISAMEM_RESERVE;
sc->mem_alloc_start = (start + 0x100000 + 1) & ~(0x100000 - 1);
sc->port_alloc_start = PCIADDR_ISAPORT_RESERVE;
PCIBIOS_PRINTV((" Physical memory end: 0x%08x\n PCI memory mapped I/O "
"space start: 0x%08x\n", avail_end, sc->mem_alloc_start));
/*
* 4. do fixup
*/
PCIBIOS_PRINTV((verbose_header, "PCIBIOS fixup stage"));
sc->nbogus = 0;
pci_device_foreach(sc, pc, maxbus, pciaddr_resource_allocate);
PCIBIOS_PRINTV((verbose_footer, sc->nbogus));
}
static void
giopci_attach(struct device *parent, struct device *self, void *aux)
{
struct giopci_softc *sc = (void *)self;
pci_chipset_tag_t pc = &sc->sc_pc;
struct gio_attach_args *ga = aux;
uint32_t pci_off, pci_len, arb;
struct pcibus_attach_args pba;
u_long m_start, m_end;
#ifdef PCI_NETBSD_CONFIGURE
extern int pci_conf_debug;
pci_conf_debug = giopci_debug;
#endif
sc->sc_iot = ga->ga_iot;
sc->sc_slot = ga->ga_slot;
sc->sc_gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product);
if (mach_type == MACH_SGI_IP22 &&
mach_subtype == MACH_SGI_IP22_FULLHOUSE)
arb = GIO_ARB_RT | GIO_ARB_MST | GIO_ARB_PIPE;
else
arb = GIO_ARB_RT | GIO_ARB_MST;
if (gio_arb_config(ga->ga_slot, arb)) {
printf(": failed to configure GIO bus arbiter\n");
return;
}
#if (NIMC > 0)
imc_disable_sysad_parity();
#endif
switch (sc->sc_gprid) {
case PHOBOS_G100:
case PHOBOS_G130:
case PHOBOS_G160:
pci_off = PHOBOS_PCI_OFFSET;
pci_len = PHOBOS_PCI_LENGTH;
m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_START);
m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_END);
break;
case SETENG_GFE:
/*
* NB: The SetEng board does not allow the ThunderLAN's DMA
* engine to properly transfer segments that span page
* boundaries. See sgimips/autoconf.c where we catch a
* tl(4) device attachment and create an appropriate
* proplib entry to enable the workaround.
*/
pci_off = SETENG_PCI_OFFSET;
pci_len = SETENG_PCI_LENGTH;
m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_START);
m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_END);
bus_space_write_4(ga->ga_iot, ga->ga_ioh,
SETENG_MAGIC_OFFSET, SETENG_MAGIC_VALUE);
break;
default:
panic("giopci_attach: unsupported GIO product id 0x%02x",
sc->sc_gprid);
}
if (bus_space_subregion(ga->ga_iot, ga->ga_ioh, pci_off, pci_len,
&sc->sc_ioh)) {
printf("%s: unable to map PCI registers\n",sc->sc_dev.dv_xname);
return;
}
sc->sc_pci_len = pci_len;
pc->pc_bus_maxdevs = giopci_bus_maxdevs;
pc->pc_conf_read = giopci_conf_read;
pc->pc_conf_write = giopci_conf_write;
pc->pc_conf_hook = giopci_conf_hook;
pc->pc_intr_map = giopci_intr_map;
pc->pc_intr_string = giopci_intr_string;
pc->intr_establish = giopci_intr_establish;
pc->intr_disestablish = giopci_intr_disestablish;
pc->iot = ga->ga_iot;
pc->ioh = ga->ga_ioh;
pc->cookie = sc;
printf(": %s\n", gio_product_string(sc->sc_gprid));
#ifdef PCI_NETBSD_CONFIGURE
pc->pc_memext = extent_create("giopcimem", m_start, m_end,
M_DEVBUF, NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, NULL, pc->pc_memext, NULL, 0, mips_dcache_align);
#endif
memset(&pba, 0, sizeof(pba));
pba.pba_memt = SGIMIPS_BUS_SPACE_MEM;
pba.pba_dmat = ga->ga_dmat;
pba.pba_pc = pc;
pba.pba_flags = PCI_FLAGS_MEM_ENABLED;
/* NB: do not set PCI_FLAGS_{MRL,MRM,MWI}_OKAY -- true ?! */
config_found_ia(self, "pcibus", &pba, pcibusprint);
}
