static int pm_callback_change_dvfs_level(struct kbase_device *kbdev)
{
struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context;
mali_bool enabledebug = MALI_FALSE;
if(kbdev->vendor_callbacks->get_poweron_dbg)
enabledebug = kbdev->vendor_callbacks->get_poweron_dbg();
if (enabledebug)
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u,
#ifdef CONFIG_EXYNOS_ASV
"asv table[%u] "
#endif
"clk[%d to %d]MHz, vol[%d (margin : %d) real: %d]mV\n",
#ifdef CONFIG_EXYNOS_ASV
exynos_get_table_ver(),
#endif
gpu_get_cur_clock(platform), platform->gpu_dvfs_start_clock,
gpu_get_cur_voltage(platform), platform->voltage_margin, platform->cur_voltage);
gpu_set_target_clk_vol(platform->gpu_dvfs_start_clock, false);
gpu_dvfs_reset_env_data(kbdev);
return 0;
}
static void __init set_volt_table_CA53(void)
{
unsigned int i;
unsigned int asv_volt = 0;
for (i = 0; i < CPUFREQ_LEVEL_END_CA53; i++) {
asv_volt = get_match_volt(ID_CL0, exynos7420_freq_table_CA53[i].frequency);
if (!asv_volt)
exynos7420_volt_table_CA53[i] = asv_voltage_7420_CA53[i];
else
exynos7420_volt_table_CA53[i] = asv_volt;
pr_info("CPUFREQ of CA53 L%d : %d uV\n", i,
exynos7420_volt_table_CA53[i]);
exynos7420_abb_table_CA53[i] =
get_match_abb(ID_CL0, exynos7420_freq_table_CA53[i].frequency);
pr_info("CPUFREQ of CA53 L%d : ABB %d\n", i,
exynos7420_abb_table_CA53[i]);
}
switch (exynos_get_table_ver()) {
case 0 :
case 1 :
case 4 :
max_support_idx_CA53 = L6; break; /* 1.4GHz */
case 5 :
max_support_idx_CA53 = L8; break; /* 1.2GHz */
default :
#ifdef CONFIG_AP_FIVE
max_support_idx_CA53 = L5; /* 1.5GHz */
#else
#ifdef CONFIG_AP_SIX
max_support_idx_CA53 = L4; /* 1.6GHz */
#else
#ifdef CONFIG_AP_SEVEN
max_support_idx_CA53 = L3; /* 1.7GHz */
#endif
#endif
#endif
}
#ifdef CONFIG_AP_MIN_FOUR
min_support_idx_CA53 = L16; /* 400MHz */
#else
#ifdef CONFIG_AP_MIN_TWO
min_support_idx_CA53 = L18; /* 200MHz */
#endif
#endif
pr_info("CPUFREQ of CA53 max_freq : L%d %u khz\n", max_support_idx_CA53,
exynos7420_freq_table_CA53[max_support_idx_CA53].frequency);
pr_info("CPUFREQ of CA53 min_freq : L%d %u khz\n", min_support_idx_CA53,
exynos7420_freq_table_CA53[min_support_idx_CA53].frequency);
}
static void __init set_volt_table_CA57(void)
{
unsigned int i;
unsigned int asv_volt = 0;
for (i = 0; i < CPUFREQ_LEVEL_END_CA57; i++) {
asv_volt = get_match_volt(ID_CL1, exynos7420_freq_table_CA57[i].frequency);
if (!asv_volt)
exynos7420_volt_table_CA57[i] = asv_voltage_7420_CA57[i];
else
exynos7420_volt_table_CA57[i] = asv_volt;
pr_info("CPUFREQ of CA57 L%d : %d uV\n", i,
exynos7420_volt_table_CA57[i]);
exynos7420_abb_table_CA57[i] =
get_match_abb(ID_CL1, exynos7420_freq_table_CA57[i].frequency);
pr_info("CPUFREQ of CA57 L%d : ABB %d\n", i,
exynos7420_abb_table_CA57[i]);
}
#if defined(CONFIG_CPU_THERMAL) && defined(CONFIG_EXYNOS5_DYNAMIC_CPU_HOTPLUG)
switch (exynos_get_table_ver()) {
case 0 :
case 1 :
case 4 :
max_support_idx_CA57 = L7; break; /* 1.8GHz */
case 5 :
max_support_idx_CA57 = L10; break; /* 1.5GHz */
default :
max_support_idx_CA57 = L4; /* 2.1GHz */
}
#else
max_support_idx_CA57 = L13; /* 1.2 GHz */
#endif
#ifdef CONFIG_S6_LOW_IDLE
min_support_idx_CA57 = L21; /* 400 MHz */
#else
min_support_idx_CA57 = L17; /* 800 MHz */
#endif
pr_info("CPUFREQ of CA57 max_freq : L%d %u khz\n", max_support_idx_CA57,
exynos7420_freq_table_CA57[max_support_idx_CA57].frequency);
pr_info("CPUFREQ of CA57 min_freq : L%d %u khz\n", min_support_idx_CA57,
exynos7420_freq_table_CA57[min_support_idx_CA57].frequency);
}
static void __init set_volt_table_CA53(void)
{
unsigned int i;
unsigned int asv_volt = 0;
for (i = 0; i < CPUFREQ_LEVEL_END_CA53; i++) {
asv_volt = get_match_volt(ID_CL0, exynos7420_freq_table_CA53[i].frequency);
if (!asv_volt)
exynos7420_volt_table_CA53[i] = asv_voltage_7420_CA53[i];
else
exynos7420_volt_table_CA53[i] = asv_volt;
pr_info("CPUFREQ of CA53 L%d : %d uV\n", i,
exynos7420_volt_table_CA53[i]);
exynos7420_abb_table_CA53[i] =
get_match_abb(ID_CL0, exynos7420_freq_table_CA53[i].frequency);
pr_info("CPUFREQ of CA53 L%d : ABB %d\n", i,
exynos7420_abb_table_CA53[i]);
}
switch (exynos_get_table_ver()) {
case 0 :
case 1 :
case 4 :
max_support_idx_CA53 = L6; break; /* 1.4GHz */
case 5 :
max_support_idx_CA53 = L8; break; /* 1.2GHz */
case 12 :
max_support_idx_CA53 = L7; break; /* 1.3GHz */
default :
max_support_idx_CA53 = EXYNOS7420_CPU_MAX_FREQ_LITTLE;
}
min_support_idx_CA53 = EXYNOS7420_CPU_MIN_FREQ_LITTLE;
pr_info("CPUFREQ of CA53 max_freq : L%d %u khz\n", max_support_idx_CA53,
exynos7420_freq_table_CA53[max_support_idx_CA53].frequency);
pr_info("CPUFREQ of CA53 min_freq : L%d %u khz\n", min_support_idx_CA53,
exynos7420_freq_table_CA53[min_support_idx_CA53].frequency);
}
